388 results about "Cache hit rate" patented technology

The invention relates to the technical field of data storage and processing, in particular to an RAID card static cache management method and device based on data popularity, and the method comprises the steps that the physical position of a data block needing to be accessed in an SSD array is acquired according to a read-write request; historical data access information of the RAID card is collected, a historical data set is generated, and a neural network model is trained by using the historical data set to obtain a cache management model; predicting and outputting data blocks which are possibly accessed in the future and the access probability of the data blocks through the cache management model; the RAID controller dynamically adjusts a cache strategy in combination with an LRU strategy according to a prediction result output by the cache management model and a read-write request of a file system, and optimizes a storage position and an updating mechanism of a data block in a cache space; and when the hit rate or the data access efficiency does not reach the preset value, adjusting the parameters of the cache strategy and updating the cache strategy. According to the method, cache resources can be more effectively distributed, the cache hit rate is improved, the cache replacement overhead is reduced, and therefore the performance of a storage system is optimized.

The invention provides a cache information processing method and device of a port platform and a medium, and belongs to the technical field of port distributed information processing. An update request is received, and authentication and flow limiting processing are performed on the request; obtaining a cache key prefix and a data structure type, routing a cache key to a fragment node based on a consumption write-back event, executing a write-in operation in a distributed cache service, and setting survival time and multi-copy synchronization; delivering the message body to the message middleware and obtaining delivery confirmation; the messages are pulled from the queue according to the configured concurrency, deduplication verification is carried out on idempotent identifiers of the messages, and data persistence operation is executed after the verification message version is higher than the current version of the database; index collection points are implanted into all modules of the whole link, and the request delay, the cache hit rate and the message accumulation depth index are visually displayed. The reasonable distribution and optimization of system resources are realized; the consistency and integrity of the data are guaranteed, and the reliability of message transmission is improved at the same time.

The invention discloses a hybrid expert model reasoning method based on cooperation of a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit), and belongs to the field of deep learning. According to the method, a CPU-GPU computing framework of a hybrid expert model is constructed, heterogeneous computing resource loads are effectively balanced, and the hardware utilization rate is remarkably increased; an intelligent cache management mechanism based on dynamic priority scores is provided, high-demand experts are reserved preferentially, and the transmission overhead caused by cache missing is reduced; through pipeline parallel design for separating calculation and transmission tasks, CPU calculation and PCIe transmission are overlapped in the GPU execution period, and delay is effectively hidden. In addition, in combination with a multi-layer expert activation prediction prospective prefetching mechanism, the expert cache hit rate is improved. The method is compatible with hybrid expert models of different scales and structures, and stable and efficient reasoning acceleration is realized on a resource-limited heterogeneous platform.

The embodiment of the invention provides a data processing method, end side equipment, a storage medium, a chip system and a computer program product, and relates to the technical field of terminals. Due to the fact that the second expert modules in the first storage are formed in the mode that the second thread executes the preloading process based on the expert preference strategy of the first request under the condition that the first thread executes the prefilling stage process through the first model, parallel execution of the preloading process and the prefilling stage process is achieved, I / O delay is reduced, and the processing efficiency is improved. And the reasoning efficiency of the first model is improved. And because the first request has expert preference, and the plurality of second expert modules stored in the first memory are determined according to the first request, the first thread performs the decoding stage flow by using the first model, and the second thread performs the decoding stage flow by using the second model. The first thread can directly obtain the second expert module corresponding to the first expert module from the first storage, so that the cache hit rate is improved, and the reasoning efficiency of the first model is improved.

The invention discloses a performance test and verification method, system and device for a multi-core heterogeneous chip and a medium, and the method comprises the steps: configuring a test parameter set according to a target application scene, the test parameter set comprising a processor core type recognition parameter, a communication topology weight parameter and a load balancing threshold parameter; generating a test case covering the heterogeneous computing core cooperative working mode; the method comprises the following steps: acquiring characteristic data during testing through a reconfigurable monitoring sub-module, wherein the characteristic data comprises inter-core communication delay information, shared cache hit rate information and power consumption distribution thermodynamic information; and performing quantitative analysis on the feature data through a multi-dimensional evaluation model to obtain a performance deviation index and an architecture optimization suggestion parameter. By optimizing the chip performance verification process under the multi-core heterogeneous architecture, the verification precision is effectively improved, and the chip performance verification method can be widely applied to the technical field of chip design.

The invention discloses a cache management method and device for memory access, equipment and a storage medium, and relates to the technical field of storage, and the method comprises the following steps: obtaining a data read-write message of a central processing unit; detecting a data popularity type of an access address of the data read-write message; searching cache data corresponding to the access address from a target cache region; if the cache data is not found in the target cache region, sending a corresponding read-write request to a memory so as to find memory data corresponding to the access address from the memory; by setting the preset cache regions corresponding to the cold data and the hot data respectively, the cache can be partitioned according to the heat of the data, so that cache resources are reasonably allocated, the cost is reduced, the memory access efficiency and speed are improved, finer consistency control can be realized, and the cache hit rate and the system performance are improved; therefore, the required data is searched in the corresponding preset cache region according to the heat of the data, and the memory access speed is increased.

The invention relates to the technical field of data processing, and particularly discloses an intelligent cache replacement method and system based on application awareness, and the method comprises the steps: sensing a cache state of an application scene, and determining a candidate cache replacement strategy according to a cache replacement strategy matching rule; the method comprises the following steps: collecting data of a storage node data access mode, a cache access state, a capacity state and a power consumption state of an application scene, and preprocessing the data to generate historical data; according to historical data, training a GRU model to predict future cache hit information, and determining a cache hit rate of the application scene; calculating strategy benefits according to the cache hit rate and the evaluation index of the cache hit rate, and comparing the candidate cache replacement strategy with the current cache replacement strategy; and when the cache hit rate is lower than a preset threshold value and a strategy benefit comparison result exceeds a set value, configuring the candidate cache replacement strategy as a current cache replacement strategy.

The invention relates to the technical field of chip scheduling and optimization, in particular to a neural network-based main control chip task scheduling and dynamic performance optimization method, which comprises the steps of data acquisition and feature engineering, neural network model design, simulation environment training, model compression and deployment preparation, real-time state monitoring, dynamic decision reasoning, scheduling strategy execution and performance optimization. The data acquisition and feature engineering comprises the following steps: S1, hardware index acquisition; analyzing task attributes (calculation-intensive / IO-intensive), a dependency relationship (DAG), deadline (Deadline) and a resource demand (CPU / GPU occupancy rate); collecting data during chip operation through a performance counter (IPC, cache hit rate and branch prediction error rate), a temperature sensor and a power consumption monitoring unit (PMU); the neural network scheduler can achieve the energy efficiency ratio which is 20%-40% higher than that of a traditional method (such as a CFS scheduler), meanwhile, the neural network scheduler adapts to sudden load changes, and the practicability and the application range of a main control chip are wider.

The invention belongs to the technical field of wireless communication, and discloses an edge computing and cache enabling meta-universe system and an intelligent optimization method, and the technical scheme of the invention comprises the following core optimization objectives: firstly, through an intelligent content cache strategy, a user cache hit rate is maximized, and unnecessary data transmission is reduced; secondly, task unloading decisions are optimized, computing resources are reasonably distributed, and energy consumption of user terminals is reduced; and thirdly, dynamic intelligent allocation of computing resources is realized, and the overall resource utilization efficiency of the system is improved. The ADRL algorithm provided by the invention has the following unique advantages: 1, by introducing an active reasoning mechanism, the decision ability of the algorithm in an uncertain environment is enhanced; secondly, in combination with preference information of the intelligent agent, an optimization strategy is more targeted; and thirdly, comprehensive balance of a multi-dimensional optimization target of the system is realized, and powerful technical support is provided for efficient operation of the element universe network.

The invention discloses a cache space control method of a storage system, electronic equipment and a storage medium, and relates to the technical field of data caching, and the method comprises the steps of identifying dirty data, comparing the size relation between the hit rate of cached data in a cache space and a first hit rate threshold value and a second hit rate threshold value, and when the hit rate is greater than the first hit rate threshold value, controlling the cache space of the storage system. When the hit rate is smaller than a first hit rate threshold value, executing an expansion instruction to control the cache module to expand a cache space, and when the hit rate is smaller than a second hit rate threshold value, controlling the cache module to brush dirty data down to a rear-end memory, executing a reduction instruction to control the cache module to reduce the cache space, and performing a cache hit rate judgment mechanism and a linkage telescopic cache mechanism in a full random access scene. The problems of performance reduction, high delay of data access, high power consumption and the like of the cache system due to the fact that the cache space is fixed and cannot adapt to different application scenes and changes of data loads in the prior art are solved, performance self-adaption of the IO model is achieved, the response speed is increased, and the performance of the cache system in multiple storage scenes is improved.

The invention discloses a content caching and replacing method and system based on context awareness, and relates to the field of content caching, and the method comprises the steps: obtaining context information, constructing a context feature vector, constructing a training sample, training an XGBoost regression model, and carrying out the prediction, thereby obtaining the future content access popularity; a multi-objective optimization function and constraint conditions are designed, an NSGA-II multi-objective evolutionary algorithm is used for solving, a comprehensive scoring function is defined, and a solution with the maximum comprehensive scoring function value is selected from an obtained solution set to serve as a final caching strategy; and designing a cache scoring function, calculating to obtain a cache score, and replacing the cache content by adopting a greedy strategy. According to the content caching and replacing method, the caching hit rate and the resource utilization efficiency can be improved, the service capability and the response efficiency of the edge node in a complex environment can be further enhanced, and therefore a more intelligent and more efficient content caching and replacing strategy is achieved in a dynamic network scene.

The invention discloses an embedded image decoding display system based on an ARM, and relates to the technical field of computers, and the system comprises a dynamic sensing module which is used for monitoring the CPU occupancy rate, the cache hit rate and the memory bandwidth utilization rate of an ARM processor in real time, establishing a three-dimensional resource vector containing a dynamic weight coefficient, and calculating a threshold boundary; the adaptive decoding engine comprises an optimization unit which is used for reconstructing a bit stream processing channel and a register data exchange mechanism based on an SIMD expansion instruction of an ARMv8.2 instruction set; the prediction unit is used for predicting instruction-level hotspot distribution of the decoding task by adopting a TinyLSTM model and generating an instruction transmitting strategy; the hardware optimization module is used for executing a heterogeneous collaboration strategy of the NEON coprocessor and the MaliGPU, and the heterogeneous collaboration strategy comprises the following steps: dividing DCT / IDCT (discrete cosine transform / inverse discrete cosine transform) calculation granularity; determining a mixing precision conversion assembly line of the GPU shader according to the color gamut of the display equipment; and the display driving module is used for implementing a decoding parameter dynamic confusion algorithm in the security domain and forming a tamper-proof closed loop with the optimization unit.

The invention belongs to the field of integrated circuits and computer system structures, and provides a caching method and system for a memory access unit of a superscalar processor, and the method comprises the steps: receiving a plurality of memory access instructions in the same period, and determining a corresponding Bank in a to-be-accessed cache through the memory access instructions; after the memory access instruction obtains a cache access permission, if cache line missing occurs, generating a missing request, merging all the missing requests, and performing parallel prefetching training on the merged missing requests by utilizing a mode of fusing a constant step length prefetching mode and a complex step length prefetching mode to obtain a prefetching request and a prefetching cache address corresponding to the prefetching request; requesting a missing cache line from the first-level cache to the second-level cache based on the missing queue, and writing the missing cache line back to the cache line of the corresponding data cache in the first-level cache; and storing the bus consistency request by using the sniffing queue, judging whether the data in the multi-core cache are consistent or not by using the consistency request, and performing consistency modification according to a judgment result. The cache hit rate and the bandwidth utilization rate are improved.

The invention provides a task scheduling method, which is applied to the technical field of artificial intelligence (AI), and comprises the following steps: obtaining a computational graph, the computational graph comprises a plurality of operators, each of the plurality of operators represents a task, according to the dependency relationship of the plurality of operators in the computational graph, sorting the plurality of operators to obtain an ordered operator sequence, the ordered operator sequence comprises a first operator and a second operator depending on the first operator, the first operator is arranged in front of the first operator, the plurality of operators are grouped according to the ordered operator sequence to obtain a plurality of operator groups, and the plurality of operator groups are sequentially scheduled to equipment according to the priority of the plurality of operator groups. According to the method, the sorted operators are grouped, and task issuing is performed by taking the operator groups as the granularity, so that effective scheduling under limited concurrency of the computational graph is realized, reduction of memory reuse probability and reduction of cache hit rate caused by overlarge concurrency are avoided, and the computational efficiency and performance of the AI model are improved.

The invention discloses a storage and calculation separation key value storage delay optimization method based on prediction driving, and aims to solve the problems of performance bottleneck and high tail delay caused by passive management and high network delay in a key value storage system in a storage and calculation separation scene. The method comprises the following steps: time load prediction: deploying a time sequence prediction model at a client, and predicting a future read-write request based on a historical access sequence; active cache prefetching: according to the predicted read request, actively preloading hotspot data from a server side to a client side for caching so as to improve the cache hit rate and hide network delay; active write-in optimization: according to the predicted write request, executing maintenance at a server side through predictive pre-insertion and active node splitting, and moving high index structure adjustment overhead out of a key request path to eliminate a write delay peak; and structure sensing batch synchronization: pre-fragmenting a local write buffer by using a server index top layer model of a client cache, and combining multiple independent remote insertion operations into one efficient batch update to reduce data synchronization overhead. Compared with an existing passive management system, the characteristics of model prediction and active cooperation are fully utilized, and the average delay and the tail delay of the system are reduced.

The invention provides a method for improving a cache hit strategy and a response speed, and relates to the technical field of cache management policies, the method comprises the following steps: monitoring the use state of a cache in real time, obtaining a cache hit rate, a cache capacity and a data validity index, and generating a real-time monitoring report of the use state of the cache; according to the real-time monitoring report of the cache use state, a cache management strategy is determined from a preset strategy library, and cache data updating is triggered; and when a data request is received, adjusting cache data according to a cache management strategy, including replacing old data and updating data layout, and recording a final access record and a cache state. According to the method, the cache hit rate and the response speed are improved by monitoring the cache state in real time, intelligently selecting the cache strategy, optimizing data access and prefetching, concurrent processing and dynamically adjusting the cache hierarchy, so that the overall performance of the computer is enhanced.

The invention discloses a data cache management method and system based on big data, and relates to the technical field of data cache management, and the method comprises the steps: collecting access mode metadata, constructing a data cache state space and an action space, and screening an effective action set of data cache; on the basis of the state space, calculating a context feature weight, and constructing a CO-IAM model to predict a data caching action; performing data caching action implementation based on a CO-IAM model prediction result; by constructing a state space and an action space of data caching, introducing a CO-IAM model, performing precise modeling and dynamic adjustment based on context feature weight, generating an invalid action mask, filtering useless caching actions, optimizing a caching hit rate and access delay, and improving the performance of the whole caching system.

The invention relates to the technical field of artificial intelligence chips and storage management, in particular to a cache line replacement method and device, a chip and electronic equipment. The method is applied to a chip comprising a data cache, the data cache comprises N cache lines in which data are stored, an access path corresponding to each cache line is managed based on a binary tree structure comprising N-1 nodes in a PLRU algorithm, and a data replacement instruction is responded, obtaining a path status bit from a root node to a leaf node on an access path corresponding to each cache line; for a specified cache line, calculating a PLRU path value according to the path status bit, and calculating a replacement score in combination with the importance level and the corresponding weight of the stored data; determining a replaceable cache line according to the replacement score; and storing the to-be-cached data and the importance level thereof into a replaceable cache line to replace the original data and the original level. Therefore, the cache line replacement priority is evaluated by combining the PLRU path value and the importance level of the stored data, the cache hit rate is effectively improved, and the system performance is optimized.

The invention discloses a data management method based on a real-time data warehouse, and the method comprises the steps: obtaining column type data blocks through vectorization processing according to collected data, dividing data types according to the access frequency of the column type data blocks, and correspondingly setting storage positions; in response to the data request, determining a data access mode according to the cache hit rate of the data request; and according to the real-time monitoring index, a load trend is predicted through a time sequence prediction statistical model, and vectorized nodes and cache capacity are adjusted. Through vectorization processing, cache hit rate analysis and dynamic resource adjustment driven by load prediction, the core problems of low storage efficiency, poor resource utilization rate, high response delay and the like of a traditional data warehouse architecture are solved, and multi-dimensional breakthrough in performance, cost and stability is achieved.

A Collaborative Caching Framework for Multi-edge Systems with Robust Federated Deep Learning is provided. First, we design a new partitioning mechanism for multi-dimensional cache space, enabling precise content recommendations in user classification intervals. Next, we develop a VQ-VAE-based accurate prediction for content popularity by overcoming posterior collapse. Finally, we create a new training mode and proactive cache replacement strategy based on robust federated deep learning. Specifically, residual-based detection for adversarial model updates and similarity-based federated aggregation are integrated to avoid the model destruction caused by adversarial updates, which enables the proactive cache replacement adapting to optimized cache resources and thus enhances cache performance. Using real-world testbed and MovieLens datasets, extensive experiments verify that RoCoCache achieves higher cache hit rates and efficiency than benchmark methods while ensuring better robustness. Moreover, we demonstrate the effectiveness of the components designed in RoCoCache via ablation experiments.

The invention discloses a method for accelerating secure metadata access in a secure memory system, a memory controller and a system, and belongs to the field of secure memory systems, and the method comprises the following steps: when a page table item corresponding to a logic page where data accessed by a processor is located does not hit a TLB, obtaining the page table item from a memory page table, extracting a physical page address from the page table item, and storing the physical page address in a memory; a counter corresponding to a physical page where the data to be accessed is located and a father node of the counter in the integrity tree are prefetched through the physical page address; adding a replacement dirty block address in a miss request sent by the last level of cache, after receiving the miss request containing a field of the replacement dirty block address, executing conventional memory reading and decryption, positioning a counter corresponding to the replacement dirty block address, and performing prefetching by using an idle memory bandwidth; in addition to the secure metadata cache, the prefetching queue is maintained to temporarily store the prefetched metadata. The cache hit rate of the security metadata in the security memory system can be improved, and the performance overhead caused by the cache miss can be reduced.

The embodiment of the invention provides a display device and an advertisement data playing method. According to the method, storage positions are dynamically allocated according to advertisement data characteristics, memory occupation is reduced, and the access speed of key data is increased; a priority score is generated by calculating the access frequency, the resource type weight and the final access time of the advertisement data, and a low-score data block is preferentially removed when the storage space is insufficient, so that the cache hit rate of high-frequency / hot advertisements is ensured; by downloading recent advertisement data to the local in advance, real-time downloading delay during playing is avoided, large file advertisements are stored in blocks, cached parts are read preferentially during playing, meanwhile, remaining data blocks are downloaded in the background, and rapid playing of the advertisement data is achieved. In addition, cloud advertisement data change is monitored, local cache is dynamically synchronized, data timeliness is ensured, a local index table is quickly queried before the advertisement is played, direct playing or playing while playing is selected according to cache integrity, waiting time is shortened, and the problem that the advertisement playing speed is low is solved.

The invention discloses a multi-core scheduling system and method based on interrupt affinity and a storage medium. The technical problem that data locality guarantee and load balancing are difficult to consider at the same time is solved by constructing a self-adaptive optimization closed loop of perception-decision-execution-feedback, and the method comprises the steps that a routing interruption configuration mechanism provides a basis for dynamic adjustment; an interrupt guide task placement mechanism ensures that an interrupt service program and an associated task are executed in the same CPU core, and the cache hit rate is increased; the execution overhead of an interrupt service program is brought into core load statistics through task context switching and a'task + ISR 'two-dimensional precise load evaluation mechanism triggered by ISR inlet / outlet double nodes, and real load awareness is achieved; a load-driven dynamic interrupt routing mechanism is combined with dual control of a hysteresis threshold and cooling time, so that a ping-pong effect is avoided. According to the method, dynamic load balancing is realized on the premise of keeping data locality, and the real-time response performance and throughput of the multi-core system are remarkably improved.

The invention relates to the technical field of data cache management, and discloses a segmented multi-level data cache management method and device, computer equipment and a storage medium. The method comprises the following steps: defining a hierarchical data management module, wherein the data management module comprises a first-level data interaction sub-module and a second-level cache hit management sub-module; receiving an upper-layer data access request, and performing data splitting according to the logic address relationship; querying the module state of the position according to the actual situation, and marking the cache hit management module state of the corresponding position; if the second-level cache hit management sub-modules to which the first-level data interaction sub-modules belong are all hit, realizing data communication with lower-layer storage equipment according to large granularity; and if part of data enters the cache, according to the continuity of the data hit state, respectively constructing commands with corresponding lengths to lower-layer storage equipment. By implementing the method provided by the invention, access requirements of different types of data can be effectively realized, the cache hit rate is improved, and better performance improvement is obtained.

The embodiment of the invention discloses a self-adaptive frequency modulation method and device which are used for improving the frequency modulation accuracy of a processor. The method comprises the steps that the computing device collects real-time monitoring data of the processor, the real-time monitoring data comprises one or more events monitored by a performance monitoring unit (PMU) of the processor, and the events comprise one or more of the following items: the number of instruction execution times, the cache hit rate and the branch prediction error rate. A predicted performance change rate of the processor is calculated based on the real-time monitoring data, the predicted performance change rate is determined based on a current performance change rate of the processor, the current performance change rate is determined based on the real-time monitoring data, and the predicted performance change rate is used for indicating the proportion of a reference performance value to an operation performance value of the processor. And determining a target frequency of the processor based on the target performance loss rate and the predicted performance change rate, wherein the target performance loss rate is used for indicating the predicted performance change rate tolerable by the processor.

The invention provides a cache elimination method and device, equipment, a medium and a program product, relates to the technical field of data processing, and aims to solve the problem of low cache hit rate. The method comprises the following steps: monitoring a key operation event of a Redis node based on an EBPF program to obtain a first key name of a first key value pair operated by the key operation event and access information corresponding to the key operation event; inputting a first service label corresponding to the first key name and the access information into a preset machine learning model for judgment to obtain a target cache elimination strategy of the first key value pair; updating a preset strategy mapping table based on the first service label and the target cache elimination strategy to obtain a first updated strategy mapping table; and performing cache elimination on the key value pair of the Redis node based on the first updating strategy mapping table. The cache hit rate can be improved.

The invention relates to the technical field of computers, and discloses a cache replacement method, system and device based on binary tree status bit management and a medium. The method comprises the following steps: firstly mapping N cache lines of a cache unit into N leaf nodes of a binary tree, then setting status bits of internal nodes and leaf nodes of the binary tree, preferentially replacing the empty cache lines when accessing the cache, then judging whether the cache is hit or not, and if the cache is hit, judging whether the cache is hit or not. Determining state transition of the internal node according to whether the path node corresponding to the hit cache line is the same as the internal node, and updating the state of the leaf node; when the cache is not hit, the historical queue is checked firstly, then the sub-tree is selected according to the node state value to search and replace the cache line, and whether replacement is carried out or not is determined according to the leaf node and the state bit of the new cache. According to the method, relatively low hardware overhead can be kept, frequency locality and time locality can be better balanced, a higher cache hit rate is provided, and relatively good performance is achieved when data of different access modes are processed.

The invention discloses a front-end cache management method, system and device for a lightweight large-model dialogue state and a medium, belongs to the technical field of front-end cache management of a large-model dialogue system, and aims at solving the technical problem of how to overcome the defects that in a traditional scheme, long context cache is low in efficiency, storage redundancy and insufficient in dynamic semantic adaptation capacity, and the large-model dialogue state cannot be managed easily. In order to realize dialogue context volume compression, improve semantic similar request hit rate and reduce cross-end synchronization delay, the adopted technical scheme is as follows: data acquisition and preprocessing: capturing user interaction behaviors in real time through front-end burying points, and performing preprocessing operation on the acquired user behavior data; semantic normalization processing: performing embedded vector conversion and semantic clustering on the text input by the user to generate a unique semantic identifier and a context vector; querying and updating the multi-level cache; and dynamic collaborative updating: dynamically adjusting the cache based on the cache hit rate, the response delay and the user feedback, and optimizing the cache effect in real time.

The invention provides a distributed large model reasoning method and system based on modular cache, and the method comprises the steps: disassembling a prompt into modules which can be independently reused through modular division driven by Schema, and calculating the attention Key-Value state of each module in advance before reasoning for caching. When a user request arrives, the system firstly performs module analysis and cache assembly on a prompt, loads a cache as required and supplements a missed part, and then injects a complete KV state into a reasoning process. Meanwhile, a layered and distributed scheduling mechanism is designed, a global scheduler selects a target GPU based on a cache hit rate and a node load, and a local scheduler manages cache copying and elimination in a node, so that load balancing and cache multiplexing are both considered. According to the scheme, repeated calculation can be remarkably reduced, the first Token delay is reduced, the system throughput rate is increased, and the method is suitable for high-repetition prompt scenes such as code generation and long text question and answer.

The invention provides a many-core processor task scheduling method and device, electronic equipment and a storage medium, and relates to the technical field of data process.The method comprises the steps that priority information of to-be-processed tasks is determined according to task type information, task importance degree information and task deadline of the to-be-processed tasks; and according to the processor residual utilization rate of each processor core, the cache hit rate of each level, the memory read-write bandwidth and the priority information of each to-be-processed task in the many-core processor, calculating the task weight of each to-be-processed task obtained by each processor core so as to perform task scheduling according to the task weight.