Thread group address space scheduling and thread switching method under multi-core environment

An address space and thread group technology, applied in the computer field, can solve problems such as poor flexibility, achieve the effect of improving the Cache hit rate, reducing the number of address space switching, and improving the overall performance of the system

Inactive Publication Date: 2010-12-22
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

This method is designed to reduce scheduling overhead with the help of hardware implementation, but this method also ignores the address space information of the thread, and has poor flexibility

Method used

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  • Thread group address space scheduling and thread switching method under multi-core environment
  • Thread group address space scheduling and thread switching method under multi-core environment
  • Thread group address space scheduling and thread switching method under multi-core environment

Examples

Experimental program
Comparison scheme
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Embodiment

[0035] Such as figure 1 As shown, this embodiment includes the following steps:

[0036] In the first step, the threads included in each process are divided into thread groups to obtain several thread groups.

[0037] The described thread group division process includes the following steps:

[0038] 1.1) According to Get the number of thread groups divided by each process, where: P i Is the number of thread groups divided by the i-th thread, A is the number of cores of the processor, B i is the parallelism factor of the i-th thread, C i Is the number of threads of the i thread, the total number of threads of all threads in D;

[0039] 1.2) The sum of the thread instruction access mode difference and the thread data access mode difference is used as a difference function between threads;

[0040] 1.3) The K-medoids clustering method is used to divide the thread groups.

[0041] In the second step, the thread group is allocated, the CPU cores of each thread group are res...

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Abstract

The invention relates to a thread group address space scheduling and thread switching method under a multi-core environment in the technical field of computers, wherein a thread grouping strategy is introduced to aggregate potential threads which can be benefited through CPU core distribution and scheduling order arrangement, the address space switching frequency in the scheduling process are reduced, and the Cache hit rate is improved, thereby improving the throughput rate of a system and enhancing the overall performance of the system; adjustment can be flexibly carried out by adopting a thread grouping method according to the characteristics and the application characteristics of a hardware platform, so that thread group division adapted to a specific situation can be created; and the method also can be combined with other scheduling methods for use. In the invention, a task queue is equipped for each core of a processor by grouping the threads, the threads with scheduling benefits are sequentially scheduled, and the invention has the advantages of less scheduling spending, large task throughput and high scheduling flexibility.

Description

technical field [0001] The invention relates to a method in the field of computer technology, in particular to a method for thread group address space scheduling and thread switching in a multi-core environment. Background technique [0002] On-chip multicore processors (CMPs) are a fast-growing parallel solution. With the development of silicon technology, more and more processor cores can be integrated on a single chip. As a bridge between users and hardware, the operating system's multi-core resource scheduling strategy and scheduling method play a vital role in the overall performance of the system. [0003] Modern operating systems widely adopt a multi-threaded computing model. That is, a process is a static environment abstraction for computing, including binary code, address space, data, and resources. Thread is the dynamic execution abstraction of process, including processor context, running stack and thread state. There are one or more execution threads under t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/50G06F9/48
Inventor 过敏意李阳王稳寅丁孟为杨蓝麒伍倩沈耀
Owner SHANGHAI JIAO TONG UNIV
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