Cache replacing method, cache controller and processor

Abstract

The embodiment of the invention provides a cache replacing method, a cache controller and a processor. The method comprises the following steps that: the cache controller determines an associated cache pool of a cache line to be replaced, wherein each associated cache row in the associated cache pool and the cache row to be replaced belong to the same memory row; a cache row to be written back is further determined from the associated cache pool according to the access information of the associated cache row; and data in the cache row to be replaced and the cache row to be written back are simultaneously written into a memory. The cache row to be replaced and the cache row to be written back belong to the same memory row, so that the hit rate of the cache region can be improved; and the memory access performance is improved. The cache controller further determines the cache row to be written back from the associated cache pool according to the access information of the associated cache row, and only the cache row to be written back in the associated cache pool is written into the memory, so that the number of the memory writing times can be reduced; and the service life of the memory is prolonged.

Description

technical field [0001] Embodiments of the present invention relate to communication technologies, and in particular, to a cache replacement method, a cache controller, and a processor. Background technique [0002] With the development of big data applications, there are higher and higher requirements for memory capacity and access speed, and the commonly used Dynamic Random-Access Memory (Dynamic Random-Access Memory, DRAM for short) can no longer meet the requirements. A new type of non-volatile memory (Non-Volatile Memory, referred to as NVM) born thereupon is expected to replace DRAM as a memory system in a computer system due to its advantages of large capacity and low power consumption. However, the read and write latency of existing NVM is higher than that of DRAM, and the number of writes is limited. [0003] The read-write mechanism inside NVM is similar to that of DRAM. NVM has a row buffer (Rowbuffer) to save the data in the most recently accessed memory row. The...

AI Technical Summary

Problems solved by technology

In the existing mechanism, affected by the cache (cache) replacement strategy, the address of the request sent to the memory is relatively random. Therefore, the line buffer hit rate is poor, which affects the memory access performance

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