5660results about "Memory systems" patented technology

Systems and methods for managing divergence of best effort transactional support mechanisms in various transactional memory implementations using a portable transaction interface are described. This interface may be implemented by various combinations of best effort hardware features, including none at all. Because the features offered by this interface may be best effort, a default (e.g., software) implementation may always be possible without the need for special hardware support. Software may be written to the interface, and may be executable on a variety of platforms, taking advantage of best effort hardware features included on each one, while not depending on any particular mechanism. Multiple implementations of each operation defined by the interface may be included in one or more portable transaction interface libraries. Systems and / or application software may be written as platform-independent and / or portable, and may call functions of these libraries to implement the operations for a targeted execution environment.

A system and method is described for internationalization of web pages by extracting translatable content from extensible mark-up language (XML), or similar data-centric meta-language representations of web pages or data used to build web pages. The extracted translatable content is stored in a translation task repository (TTR) accessible by the web developer and the translator. The XML representation is then modified to include selection control logic to select the appropriate translations for insertion into the final web page. The translator accesses the TTR to translate the appropriate content and saves the translations back to the TTR associated with the original translatable data. The translations are obtained from the TTR as selection cases for the selection control logic of the XML representation. As the XML is converted into the web source code, the selection logic and translations are embedded therein facilitating building the web site in multiple different languages.

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for multi-agent AI collaboration. The system provides a universal multi-modal key-value subsystem for sharing partial computations, implements hybrid placement strategies for dynamic memory management, and incorporates quantum-resistant secure enclaves. The architecture integrates hardware acceleration through GPU-FPGA hybrid caching and neuromorphic processors, applies adaptive energy and thermal management across hardware generations, and implements autonomous flash resource orchestration with multi-dimensional wear management. The system orchestrates tensor workflows using hierarchical scheduling, enables cross-agent collaboration with privacy preservation, and supports continuous learning without catastrophic forgetting. This integration delivers unprecedented computational efficiency and security in high-dimensional decision-making environments while supporting incremental adoption through modular interfaces.

A method to share remote DMA (RDMA) pointers to a key-value store among a plurality of clients. The method allocates a shared memory and accesses the key-value store with a key from a client and receives an information from the key-value store. The method further generates a RDMA pointer from the information, maps the key to a location in the shared memory, and generates a RDMA pointer record at the location. The method further stores the RDMA pointer and the key in the RDMA pointer record and shares the RDMA pointer record among the plurality of clients.

A system for adaptively caching network communication protocols enhances efficiency across heterogeneous device environments through a multi-level cache architecture with device-capability-based tiers. The system collects endpoint telemetry data including device capabilities and operational constraints to classify endpoints and generate context-aware protocol variants optimized for specific device types. Protocol optimization opportunities are determined through structural analysis of message patterns and state transitions. The system performs protocol deduplication by identifying functionally equivalent variants and maintaining canonical representations to reduce cache redundancy. Cache synchronization across distributed nodes uses enhanced Merkle tree structures with protocol normalization processing. The system predicts communication needs based on historical patterns, network context, and endpoint constraints, enabling proactive cache management tailored to device capabilities. Integration with event-driven data communication systems enables seamless protocol selection and translation while maintaining compatibility between diverse endpoint types, from high-performance servers to resource-constrained IoT devices.

Systems and methods for dynamic knowledge integration in LLM systems including receiving multimodal input data comprising text, image, audio, video, and / or code data, extracting information by processing the multimodal input data through a document processor, storing the extracted information in a dynamic knowledge base, receiving a user query at a query processor, identifying knowledge domains related to the user query using domain-specific agents, retrieving real-time information from the dynamic knowledge base responsive to the identified knowledge domains, integrating the real-time information into the processing of an LLM by a dynamic knowledge integrator, and generating a response using the LLM with the real-time information.

The invention relates to the technical field of artificial intelligence, can be applied to the fields of financial science and technology and medical health, and discloses a reasoning optimization method, device, equipment and medium for a multi-modal large language model.The method comprises the steps that an input long context sequence is obtained, and key value projection is conducted on the long context sequence to generate an initial key value cache; for each attention layer of the multi-modal large language model, calculating an attention matrix of the attention layer according to the vector dimension of the long context sequence and the initial key value cache; calculating a cross-modal attention entropy according to the attention matrix, and determining a cache size of an attention layer according to the cross-modal attention entropy; optimizing the initial key value cache based on a cumulative attention scoring mechanism and a window strategy to obtain a target key value cache; and reasoning the long context sequence according to the cache size and the target key value cache to generate a long context reasoning result. And the reasoning efficiency and the reasoning accuracy are improved.

One aspect of the instant disclosure may provide a system and method for processing scatter-gather direct memory access (S-G DMA) instructions. During operation, the system may receive an S-G DMA instruction associated with a message and gather instruction context for the S-G DMA instruction. An S-G DMA processor may process the S-G DMA instruction based on the gathered instruction context and determine whether there exists a pending S-G DMA instruction associated with the message. In response to the presence of the pending S-G DMA instruction, the system stores the instruction context in a hot context cache at an address corresponding to the pending S-G DMA instruction. In response to the absence of the pending S-G DMA instruction, the system stores the instruction context in a cold context cache.

A system and method for extending mobile-optimized multi-stage language model processing with federated persistent cognitive architecture. The system processes prompts through a first large language model to generate “thoughts,” which are cached and processed with the original prompt through a smaller language model. Building upon the three-tier thought caching, the system implements a federated multi-tier hierarchy with local device, domain-specific branch, and global collective caches. A federated cognitive orchestrator coordinates operations across multiple domain-specialized instances, managing thought routing, state synchronization, and cross-domain knowledge sharing while maintaining domain boundaries. During user inactivity, autonomous reasoning continues in cloud environments, generating insights from existing thoughts and interaction history. The system performs memory consolidation, thought cache optimization, and cross-domain pattern recognition without consuming mobile device resources, while maintaining privacy boundaries. This persistent cognitive architecture functions as an evolving reasoning partner rather than merely a responsive tool.

The invention discloses a memory data migration method and electronic equipment, and relates to the technical field of computers, and the method comprises the steps: determining the access heat of a storage device accepting the access of a computing node based on a memory access task executed by a switching controller and an address mapping table, so as to determine a source device and a candidate data unit, according to the access parameter of the candidate data unit and the state parameter of the storage device, calculating a performance score after the candidate data unit is stored in the storage device so as to determine the data unit to be migrated and the target device, so that cold and hot data identification from the perspective of a computer fast interconnection memory heterogeneous system is realized; the rationality of data migration is improved on the basis of quantitative performance scores; according to the method, the to-be-migrated data unit is controlled to be migrated from the source device to the target device, and the address mapping table is updated, so that the data migration task is prevented from influencing the host work of the computing node, and a cold and hot data migration scheme without being perceived by the host in the computer fast interconnection memory heterogeneous system is realized.

The invention provides a priority resetting method of a cache line and an artificial intelligence chip, and relates to the technical field of artificial intelligence chips, the method comprises the following steps: detecting that a cache group contains a cache line of a first priority state (namely, the priority is greater than a preset level), and in addition, detecting that the cache group contains the cache line of the first priority state (namely, the priority is greater than the preset level); detecting a request state between the processing core and the cache when the target duration (namely the interval duration from the previous access of the data request carrying the priority prompt to the cache group) is greater than the preset duration; when the request state is that the data request sent by the processing core is not detected, spontaneously initiating a priority resetting process, and adjusting the priority of the cache line in the first priority state in the cache group to a preset level; in this way, hardware can automatically reset the priority of the cache line, the situation that the cache line with the high priority occupies the cache space for a long time is avoided, the cache space reserved for non-important data access is improved, the overall performance of the cache is improved, and meanwhile processing of a data request (normal access) of a processing core is not affected.

The invention discloses a parallel processor dynamic resource allocation system and method based on reconfigurable hardware, and relates to the technical field of computer chips, and the system comprises a workload monitoring module which is responsible for monitoring the workload type and the resource demand of a task processed by a parallel processor in real time, and determining the task type and the resource demand by identifying the task type and the resource demand; a monitoring result is fed back to the resource allocation control module; the resource allocation control module is responsible for generating a corresponding resource allocation control signal based on feedback information of the workload monitoring module and dynamically configuring the reconfigurable hardware module; the reconfigurable hardware module is responsible for realizing efficient adaptation to diversified tasks through a plurality of reconfigurable units formed by programmable logic devices according to different working load dynamic reconfiguration functions and connection modes; and the data caching and transmission module is responsible for cross-module data circulation and global data storage. Different task requirements can be accurately adapted, and the resource utilization rate is improved.

The invention relates to a final-stage cache design method based on near memory calculation, and belongs to the technical field of near memory calculation. And compared with a near memory processor near a traditional main memory, data access and calculation can be carried out more quickly, and the calculation throughput rate can be improved. According to the near storage calculation, a near storage processor and a last-stage cache storage array are directly designed in an integrated mode, faster memory access is achieved through an internal bus interconnection mode, and the problem of a storage wall between the calculation speed and the memory access speed and the problem of a power consumption wall of data handling are relieved to a certain degree. The last-stage cache controller cooperates with the embedded processor, and can dynamically coordinate between a standard cache function and a calculation mode. Through a synchronization mechanism in a last-stage cache controller, a memory access request from a host CPU and a calculation task executed by an embedded processor in a last-stage cache are transparently balanced, so that efficient near-memory calculation under cache consistency is realized.

Disclosed in the present application are a data processing system and method, and a device, a medium and a computer program product in the technical field of computers. The data processing system comprises: at least one processor device and at least one target device connected to the at least one processor device, wherein the processor device and the target device each comprise a consistency function processing device and at least one consistency interface. In the same device, the consistency function processing device is in communication connection with the at least one consistency interface; and two consistency interfaces in different processor devices are in communication connection with each other, two consistency interfaces in different target devices are in communication connection with each other, or two consistency interfaces in any processor device and any target device are in communication connection with each other, such that the cache consistency between different processor devices, the cache consistency between different target devices, or the cache consistency between any processor device and any target device is realized.

The invention relates to the technical field of computer system structures and storage, in particular to a non-volatile memory quick recovery method based on metadata priority and on-demand loading. The method comprises the following steps: in response to a system fault signal detected by a voltage monitoring unit, freezing a processor context and traversing a page table structure to extract system configuration information; writing the system configuration information and business data codes in the volatile memory into a nonvolatile medium to generate a persistent state mirror image; analyzing the persistent state mirror image, extracting address conversion metadata, and reconstructing a mapping relation from a virtual address to a physical page frame in a volatile memory; and generating an address mapping table, wherein the physical page frame pointed by the address mapping table is set to be in an existing state but is not associated with the effective service data. According to the method, decoupling of the control flow and the data flow is realized by constructing a virtual ready state, and quick starting of the system and immediate response of key services are realized on the premise of not depending on the total capacity of a memory.

The invention belongs to the related technical field of high-performance computing, and provides a memory architecture-oriented dual-precision general matrix multiplication optimization method and system in order to solve the problems of limited computing power and access efficiency and the like in the prior art. Decomposing the matrix into a plurality of sub-matrix blocks according to the slave core array topology; the slave core receives the sub-matrix blocks issued by the master core, divides the sub-matrix blocks into small sub-matrix blocks based on a uniform blocking rule, loads the small sub-matrix blocks to an independent buffer area of a local data memory based on a DMA double-buffer protocol, divides the small sub-matrix blocks in the buffer area into SIMD vectors according to the SIMD unit characteristics of the slave core, and sends the SIMD vectors to the slave core; vectorization calculation and caching operation are alternately switched according to an iteration period through different independent buffer areas; and after all the slave cores finish calculation, the master core collects results written back to the master memory by the slave cores to obtain a final operation result, and double breakthrough of calculation power and memory access efficiency is realized.

A bank of a memory device is divided into column planes. Each column plane is associated with column selects. A portion of a column plane associated with one column select used to store metadata associated with data of the remaining column selects. Both the metadata and the data are provided to an error correction code circuit as a combined code word that provides error correction for both the data and the metadata.

Methods, systems, products, services, and apparatuses for generative AI systems configured to produce computer program code using a knowledge base that includes a client-specific code base, including: receiving one or more input tokens associated with a computer program; accessing information describing a domain-specific codebase; and generating, based on the one or more input tokens associated with the computer program and information describing a domain-specific codebase, suggested code to insert into the computer program.

The invention discloses a storage and calculation separation method and device based on multi-level cache and intelligent scheduling and a server, and belongs to the technical field of data processing, and the method comprises the following steps: collecting operation behavior data of a user, carrying out distributed storage, and dynamically distributing and calculating node cache space; performing classification marking to form marked user data; performing intelligent scheduling layer analysis tasks on the marked user data, and screening and distributing adaptive computing nodes; the computing node receives the analyzed task to check the local cache, obtains corresponding data from the local or request remote storage according to the validity of the local corresponding data, computes the corresponding data, and caches the computed data to the local or remote storage according to the user access probability; and carrying out dynamic scheduling and hierarchical storage on the calculated data between local cache and remote storage according to access frequency and heat factors. According to the invention, the problems of low transmission efficiency and unbalanced resource utilization of the existing storage and calculation separation architecture are solved.

The invention relates to the technical field of electric digital data processing, and discloses a multi-dimensional data logic processing method based on an artificial intelligence algorithm, which comprises the following steps: receiving a target discrete data packet, extracting metadata, and calculating to generate a dimension entropy feature vector representing data logic complexity; inputting the vector into a preset topological mapping model, and outputting an initial adjacent matrix; calling a feedback suppression mask matrix generated based on a historical operator utility state, and executing bitwise logic AND operation with the initial adjacent matrix to generate a corrected effective topological matrix; the matrix is analyzed, a logic operator function pointer is dynamically indexed in an instruction cache, and a directed acyclic execution linked list is constructed; according to the method, redundant logic nodes in AI prediction are definitely eliminated through a bit operation mask mechanism based on historical feedback, and deterministic convergence of processing delay and optimal matching of computing power resources are achieved.

A metadata access method, apparatus, and computer-readable storage medium for efficient metadata retrieval through cache management. The method receives metadata query requests including target index information from processes and performs matching operations on a global cache file containing records with index information and slot identifiers. Each cache description array corresponds to memory blocks caching metadata. Upon successful matching, the target cache description array is accessed using the target slot identifier. The data state of target metadata is determined from the cache description array, and target address information indicating the location of the target memory block in shared memory is obtained and returned to the requesting process, enabling efficient shared memory-based metadata access.

The invention discloses a data processing method, a product, electronic equipment and a computer readable storage medium, relates to the technical field of computers, and aims to solve the problems of large GPU (Graphic Processing Unit) space occupation and high access delay in data processing in related technologies. Reading corresponding historical key value cache data from a key value cache of the memory extension equipment according to a historical key value cache data acquisition request sent by a host end; returning the historical key value cache data to the host end, and enabling the host end to process the current input data based on the historical key value cache data by adopting a local model to obtain key value data; and obtaining key value cache data corresponding to the key value data sent by the host end, and sending the key value cache data to a key value cache of the memory extension equipment for storage. The key value cache data is stored in the key value cache of the memory extension equipment, and the historical key value cache data is read from the key value cache, so that the occupation of the memory space of the GPU and the consumption of the memory bandwidth can be reduced, and the access delay is reduced.

Implementations of this specification provide key-value cache management, model reasoning, and data processing methods and apparatuses for large language models. In an implementation, a method comprises allocating a virtual memory block in a virtual address slot to newly-added token key-value data of a model reasoning request, in response to determining that a scheduling result of the model reasoning request indicates the model reasoning request is scheduled for execution, maintaining a mapping relationship between an occupied virtual address slot and a physical graphics memory block allocated to the model reasoning request, and copying the newly-added token key-value data to the physical graphics memory block.

The invention discloses a data access method and device, electronic equipment and a storage medium. The data access method comprises the steps that target access features of a target memory area in the running process of a target program are obtained; according to the target access feature, determining a cache attribute corresponding to the target memory region; under the condition that the cache attribute corresponding to the target memory area is a cacheable attribute, performing data access according to a cache process; and under the condition that the cache attribute corresponding to the target memory area is a non-cacheable attribute, skipping the cache, and performing data access in the main memory. By applying the technical scheme provided by the invention, the cache attribute of the memory region can be dynamically determined, and the cache resource utilization efficiency and the data access efficiency are improved.

A method for automated control code generation and verification includes: receiving a natural language command, the natural language command being configured to instruct the large language model to output a code text that meets control requirements corresponding to the natural language command; performing matching retrieval on a vector database according to the natural language command to obtain a sample code snippet; obtaining API structured information corresponding to the sample code snippet from a knowledge graph database; generating an initial control code according to the sample code snippet and the API structured information; and performing a multi-level virtual operation verification on the initial control code in a software motion control system, and generating a target control code according to multi-level verification results confirmed multiple times by the user and the initial control code.

A semiconductor device may include: a first conductive line including an opening passing through the first conductive line; a second conductive line disposed over the first conductive line and spaced apart from the first conductive line; a first electrode layer buried in the opening; a selector layer disposed in the opening and surrounding side surfaces of the first electrode layer; and a variable resistance layer disposed over the selector layer and the first electrode layer.

The invention provides a real-time data acquisition buffer throughput management method and device and electronic equipment, and relates to the field of data processing. Receiving a data object containing a sampling value, a timestamp, a measuring point number and a state mark through an input memory queue, and constructing a logic mapping identifier by a mapping agent unit to generate a logic write-in state; the logic write-in state is stored in a delay sensing buffer area, and a transaction confirmation delay sequence returned by a target database is monitored in combination with a distributed delay monitoring unit; establishing a time regression model based on the delay sequence, and generating a prediction projection window of transaction confirmation time; when the window meets a confidence threshold condition, releasing the logic write-in state to an output memory queue; and finally, writing into a database through an output thread, generating a completion mark table, and feeding back for delay buffer dynamic management. By implementing the technical scheme provided by the invention, the buffer data release rhythm and the database processing capability are conveniently coordinated, so that the overall throughput efficiency is improved.

A method, computer program product, and computing system for processing a dataset of query-answer pairs. Synthetic variations of queries are generated and each of the synthetic variations of queries are mapped to a corresponding answer from the dataset. An embedding dataset is generated by transforming the synthetic variations into synthetic query embeddings and the queries into query embeddings. A first set of embeddings is defined for storage in a semantic cache and a second set of embeddings are defined and are not stored in the semantic cache. A separate distance threshold is assigned to each embedding of the first set of embeddings and a pairwise distance between each query and the synthetic variations is determined. Distance thresholds for respective pairwise distances between a query and synthetic variations of the query are generated. Subsequent queries are processed using the semantic cache and the distance thresholds.

The embodiment of the invention provides a model reasoning data caching method and device for a caching system and a storage medium, and the method comprises the steps: configuring a first virtual address mapped to a high-performance memory of the caching system for a data caching pool, and generating a first reasoning data according to the data size of the first reasoning data generated by a target reasoning model; determining a target memory space of the high-performance memory mapped by the first virtual address, and enabling the data volume of the first reasoning data to be in direct proportion to the memory space volume of the target memory space mapped by the first virtual address, thereby creating a dynamic data buffer pool of the target reasoning model, and then caching the first reasoning data based on the target memory space corresponding to the dynamic data buffer pool, thereby realizing on-demand allocation of the high-performance memory in the cache system, and improving the utilization efficiency and the use flexibility of the high-performance memory in the cache system.