10 results about "Reconfigurability" patented technology

The invention relates to a method for deploying a spiking neural network to a hardware device. The method includes providing the spiking neural network, training the spiking neural network to obtain a trained spiking neural network, mapping neurons and synapses in the trained spiking neural network to corresponding components of the hardware device, simulating deployment of the trained spiking neural network on a hardware device using the obtained mapping, and deploying the trained spiking neural network to the hardware device using the mapping and the simulation. The training, mapping, simulation and deployment steps are executed by using hardware information of the hardware device; wherein the hardware information comprises at least one of hardware resource constraints, hardware connection constraints, dynamic range of hardware design parameters, characterization or statistics of neurons and synapses, reconfigurability, programmability, yield, computing resources, temporal characteristics, constraints on pre-processing, interfaces and peripheral devices, and available encoders and / or decoders.

A network slice deployment and reconfiguration method includes: deploying virtual nodes in each network slice sequentially; if the deployment of the current virtual node in the current network slice fails, identifying the congested physical node causing the failure, and selecting the congested physical node with the highest congestion as the current congested physical node; selecting the network slice with the lowest importance that was successfully deployed as the current successfully deployed network slice; for the current congested physical node, if the currently successfully deployed network slice is reconfigurable, reconfiguring the currently successfully deployed network slice and redeploying the current virtual node of the current network slice; otherwise, selecting the next successfully deployed network slice as the current successfully deployed network slice and returning to the reconfigurability determination step; if there is no next successfully deployed network slice, selecting the next congested physical node as the current congested physical node and returning to the reconfigurability determination step; if there is no reconfigurable successfully deployed network slice for each congested physical node, rejecting the deployment of the current network slice.

The invention discloses an interconnection architecture applied to an accelerator cluster, which can be applied to any interconnection architecture capable of prolonging a transmission distance, reducing signal loss, reducing transmission cost and power consumption and having exchange capacity, namely any architecture capable of connecting two ends in the accelerator cluster to serve as interconnection components. The characteristics of data routing and forwarding at the two connected ends are utilized, the expandability and dynamic reconfigurability of the accelerator cluster are enhanced, the resource utilization rate is improved, and the requirement of the accelerator cluster for a high-capacity switch can be directly reduced. In addition, an interconnection network deployment mode of independent networking can be achieved without using a switch, and collaborative / hybrid deployment with a traditional switch can also be achieved. In addition, the invention also has the following advantages: 1, networking is allowed under the condition that a traditional switch is not used, and the reliability and fault tolerance of the system are improved through a mode of connecting a plurality of active switching connectors in parallel; 2, on the basis of mixed use of a novel high-performance interconnection architecture and a traditional switch, the requirement of networking on high-capacity traditional switching equipment can be reduced; and 3, the expandability of the accelerator cluster is enhanced, and the system can be expanded more conveniently.

This invention discloses a highly reliable control method for aerospace servo system software framework, comprising the following steps: S1: establishing monitoring modules corresponding to each function of the aerospace servo system software framework; S2: a fault judgment module performs fault judgment on the status of the monitoring modules; S3: a fault handling module performs reset recovery, hot switching, fault-tolerant operation, and shutdown on the monitoring modules based on the fault judgment results. This invention not only achieves precise fault location and isolation, directly addressing the root cause and avoiding a crude, one-size-fits-all approach, but also improves the system's reconfigurability and recovery efficiency. Because the fault is precisely located in a specific software function module, the recovery strategy can be extremely refined and rapid, greatly shortening the fault recovery time and improving system availability and mission success rate.

The invention discloses a low-code operation integration method, system and equipment based on a reconfigurable meta-model and a medium, mainly relates to the technical field of low-code operation, and is used for solving the problems that a traditional low-code platform depends on black box type model construction, is lack of transparency and reconfigurability, is difficult to balance platform performance and flexibility, and is not easy to operate in the prior art. And an incremental updating mechanism is incomplete. Comprising the steps of obtaining operation data of a low-code platform through a preset visual interface; constructing a meta-model according to the operation data; running the data meta-model, the process meta-model, the interface meta-model and the platform meta-model by using a preset running framework in the lightweight running container to generate a corresponding running platform; and acquiring newly added / modified operation data through a preset API (Application Program Interface), updating the newly added / modified operation data to a preset visual interface, and replacing contents corresponding to the meta-model description file in the lightweight operation container by the lightweight operation container through an incremental loading mechanism.

The invention discloses a UART-SPI conversion system and method based on an FPGA, and belongs to the technical field of data communication. The system comprises an upper computer, an FPGA board and a chip to be tested; a UART-SPI communication protocol conversion circuit is integrated in the FPGA board, and the UART-SPI communication protocol conversion circuit comprises a UART interface module, a system control module, a register configuration module, an SPI interface module, a clock and reset management module, a peripheral signal generation module, an asynchronous FIFO module and a clock domain crossing synchronization module. And the system control module analyzes the configuration data packet from the upper computer and executes various configuration instructions. The UART data frame structure and the SPI data frame structure are dynamically configured through the instruction, flexible configuration of an SPI mode, a clock, UART parameters and various peripheral signals is supported, the reconfigurability of an FPGA is fully utilized, the adaptability to diversified communication protocols in scenes such as chip testing is remarkably improved, and the method has the advantages of being short in development period and wide in applicability.

The application discloses a low-power single-precision floating-point multiplier based on a logarithmic approximation algorithm and belongs to the technical field of integrated circuits.The application approximates and optimizes an accurate floating-point multiplier in multiple aspects, mainly including a preprocessing module and a mantissa multiplier.The application adopts a hybrid precision architecture combining a logarithmic approximation algorithm and probability statistical truncation compensation, and divides mantissa multiplication into high-weight segmented array multiplication and low-weight segmented logarithmic multiplication.The application retains accurate calculation of high-weight segments and realizes low-weight segment calculation at a low cost, and errors of various approximate circuits can be offset to each other.The approximate multiplier provided by the application can significantly improve accuracy and can achieve a better balance between hardware overhead and accuracy requirements.The floating-point multiplier has reconfigurability and can be reconfigured and designed according to accuracy requirements to realize fine-grained adjustment of accuracy.The application is suitable for fault-tolerant applications with requirements for circuit delay and power consumption.

The application relates to the technical field of digital signal processing, in particular to a non-scaling reconfigurable CORDIC calculation method based on a lookup table and a micro-rotation angle set, which comprises the following steps: input angle and a mode selection signal are acquired; based on the mode selection signal, a first-stage rotation operation is performed on the input angle through the lookup table, the input angle is mapped to a small-angle region, and a first-rotation-vector value and a first residual angle after the first-stage rotation operation are output; a multi-stage iterative micro-rotation operation is performed on the first residual angle by using the micro-rotation angle set, and a final-rotation-vector value is output; wherein the circular rotation and the hyperbolic rotation share the address of the lookup table, the micro-rotation angle set and the rotation operation hardware resources, and the mode switching is performed through the mode selection signal, so that the high reconfigurability of the hardware resources is realized. The method can solve the technical problem that the existing CORDIC architecture is difficult to balance among the convergence range, the hardware resources, the calculation accuracy and the reconfigurability.

This invention provides a dynamically reconfigurable binning method, comprising: acquiring logic units in a reconfigurable region and a static region respectively; detecting interaction signals connecting the static region and the reconfigurable region; and creating input logic units and output logic units with interface connections between the static region and the reconfigurable region based on the interaction signals. By parsing the input and output ports of the reconfigurable region module, a data interaction interface is generated to realize interaction between the static region and the reconfigurable region. This allows for the rational layout and routing of individually packaged reconfigurable logic unit blocks and the generation of dynamically reconfigurable code streams, overcoming the difficulty of achieving dynamic local reconfigurability and improving system flexibility and compilation efficiency. The reconfigurable module and FPGA chip provided by this invention have corresponding advantages.

The invention discloses an Internet of Things equipment system dynamic reconfigurable method based on virtual machine construction. The method comprises the following steps: standardized construction of a system mirror image; after standardization construction of the system mirror image is completed, mirror image format conversion and compression optimization are carried out; network starting and PXE environment establishment are carried out, and target equipment is started from the network through a PXE protocol and enters a Debian installation environment; constructing a PXE server, and deploying key components; automatic programming is carried out, and after the target equipment is started through the PXE to enter a Debian installation environment, an automatic script is inserted through a partman / earlycover configured in preseed.cfg; a system partition is automatically expanded, a cloud-init tool is introduced, and a root partition is automatically expanded when the system is started for the first time. The method has high standardization, automation and dynamic reconfigurable capabilities, and is suitable for IoT scenes with limited resources and batch deployment.