3 results about "Reconfigurability" patented technology

The application discloses a low-power single-precision floating-point multiplier based on a logarithmic approximation algorithm and belongs to the technical field of integrated circuits.The application approximates and optimizes an accurate floating-point multiplier in multiple aspects, mainly including a preprocessing module and a mantissa multiplier.The application adopts a hybrid precision architecture combining a logarithmic approximation algorithm and probability statistical truncation compensation, and divides mantissa multiplication into high-weight segmented array multiplication and low-weight segmented logarithmic multiplication.The application retains accurate calculation of high-weight segments and realizes low-weight segment calculation at a low cost, and errors of various approximate circuits can be offset to each other.The approximate multiplier provided by the application can significantly improve accuracy and can achieve a better balance between hardware overhead and accuracy requirements.The floating-point multiplier has reconfigurability and can be reconfigured and designed according to accuracy requirements to realize fine-grained adjustment of accuracy.The application is suitable for fault-tolerant applications with requirements for circuit delay and power consumption.

The application relates to the technical field of digital signal processing, in particular to a non-scaling reconfigurable CORDIC calculation method based on a lookup table and a micro-rotation angle set, which comprises the following steps: input angle and a mode selection signal are acquired; based on the mode selection signal, a first-stage rotation operation is performed on the input angle through the lookup table, the input angle is mapped to a small-angle region, and a first-rotation-vector value and a first residual angle after the first-stage rotation operation are output; a multi-stage iterative micro-rotation operation is performed on the first residual angle by using the micro-rotation angle set, and a final-rotation-vector value is output; wherein the circular rotation and the hyperbolic rotation share the address of the lookup table, the micro-rotation angle set and the rotation operation hardware resources, and the mode switching is performed through the mode selection signal, so that the high reconfigurability of the hardware resources is realized. The method can solve the technical problem that the existing CORDIC architecture is difficult to balance among the convergence range, the hardware resources, the calculation accuracy and the reconfigurability.

This invention provides a dynamically reconfigurable binning method, comprising: acquiring logic units in a reconfigurable region and a static region respectively; detecting interaction signals connecting the static region and the reconfigurable region; and creating input logic units and output logic units with interface connections between the static region and the reconfigurable region based on the interaction signals. By parsing the input and output ports of the reconfigurable region module, a data interaction interface is generated to realize interaction between the static region and the reconfigurable region. This allows for the rational layout and routing of individually packaged reconfigurable logic unit blocks and the generation of dynamically reconfigurable code streams, overcoming the difficulty of achieving dynamic local reconfigurability and improving system flexibility and compilation efficiency. The reconfigurable module and FPGA chip provided by this invention have corresponding advantages.