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13292results about How to "Large capacity" patented technology

Runtime adaptable search processor

ActiveUS20060136570A1Reduce stacking processImproving host CPU performanceWeb data indexingMultiple digital computer combinationsData packInternal memory
A runtime adaptable search processor is disclosed. The search processor provides high speed content search capability to meet the performance need of network line rates growing to 1 Gbps, 10 Gbps and higher. he search processor provides a unique combination of NFA and DFA based search engines that can process incoming data in parallel to perform the search against the specific rules programmed in the search engines. The processor architecture also provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. Further, a runtime adaptable processor is coupled to the protocol processing hardware and may be dynamically adapted to perform hardware tasks as per the needs of the network traffic being sent or received and/or the policies programmed or services or applications being supported. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A high performance content search and rules processing security processor is disclosed which may be used for application layer and network layer security. scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer. A security system is also disclosed that enables a new way of implementing security capabilities inside enterprise networks in a distributed manner using a protocol processing hardware with appropriate security features.
Owner:MEMORY ACCESS TECH LLC

Thin-film deposition apparatus

A gas-feeding apparatus configured to be connected to an evacuatable reaction chamber includes a gas-distribution head for introducing gases into the chamber through a head surface. The gas-feeding head includes a first section for discharging a gas through the head surface toward a susceptor and a second section for discharging a gas through the head surface toward the susceptor. The first and the second sections are isolated from each other in the gas-distribution head, at least one of which section is coupled to an exhaust system for purging therefrom a gas present in the corresponding section without passing through the head surface.
Owner:ASM JAPAN

Runtime adaptable search processor

A runtime adaptable search processor is disclosed. The search processor provides high speed content search capability to meet the performance need of network line rates growing to 1 Gbps, 10 Gbps and higher. The search processor provides a unique combination of NFA and DFA based search engines that can process incoming data in parallel to perform the search against the specific rules programmed in the search engines. The processor architecture also provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. Further, a runtime adaptable processor is coupled to the protocol processing hardware and may be dynamically adapted to perform hardware tasks as per the needs of the network traffic being sent or received and / or the policies programmed or services or applications being supported. A set of engines may perform pass-through packet classification, policy processing and / or security processing enabling packet streaming through the architecture at nearly the full line rate. A high performance content search and rules processing security processor is disclosed which may be used for application layer and network layer security. Scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to / from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer. A security system is also disclosed that enables a new way of implementing security capabilities inside enterprise networks in a distributed manner using a protocol processing hardware with appropriate security features.
Owner:MEMORY ACCESS TECH LLC

Memory sensing circuit and method for low voltage operation

A sensing module operates with a sense amplifier sensing a conduction current of a memory cell via a coupled bit line under constant voltage condition in order to minimize bit-line to bit-line coupling. The rate of discharge of a dedicated capacitor as measured by a change in the voltage drop there across in a predetermined period is used to indicate the magnitude of the conduction current. The voltage cannot drop below a minimum level imposed by a circuit for maintaining the constant voltage condition on the bit line. A voltage shifter is used to boost the voltage during the discharge and to unboost the voltage after the discharge, so that the change in voltage drop properly reflects the rate of discharge without running into the minimum level.
Owner:SANDISK TECH LLC

High density integrated circuit packaging with chip stacking and via interconnections

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement. The carrier may be of the same material as the chip stacks to match coefficients of thermal expansion. High-density circuit packages may also be in the form of removable memory modules in generally planar or prism shaped form similar to a pen or as a thermal conduction module.
Owner:INT BUSINESS MASCH CORP

NMR logging of natural gas reservoirs

A method is provided to estimate the pore volume of a formation occupied by hydrocarbon phase or phases, the method comprising the steps of: obtaining a first pulsed NMR log of the formation, the pulse sequence of the first NMR log comprising an initial 90 DEG radio frequency pulse, followed by a series of 180 DEG radio frequency pulses starting at a time period tcp1 after the initial 90 DEG pulse, and the series of pulses comprising magnetic pulses each separated by a time period 2tcp1; obtaining a second pulsed NMR log of the formation, the pulse sequence of the second NMR log comprising an initial 90 DEG radio frequency pulse, followed by a series of 180 DEG pulses starting at a time period tcp2 after the initial 90 DEG pulse, and the series of 180 DEG pulses comprising radio frequency pulses each separated by a time period 2tcp2 wherein the time tcp2 is a time that is different from tcp1 by an amount of time sufficient to separate resultant peaks of transverse relaxation times attributable to the hydrocarbon phase or phases within the formation; and determining, from the first and the second NMR logs, the pore volume of a formation occupied by hydrocarbon phase or phases within the formation. In a preferred embodiment, pore volume occupied by hydrocarbon gas is determined, and tcp2 is a time that is greater than that which results in the measured transverse relaxation time of the hydrocarbon gas being less than about 2x10-3 seconds and tcp1 is a time that is less than that which results in the measured transverse relaxation time of the hydrocarbon gas being greater than about 4x10-3 seconds.
Owner:SHELL OIL CO

High density integrated circuit packaging with chip stacking and via interconnections

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement. The carrier may be of the same material as the chip stacks to match coefficients of thermal expansion. High-density circuit packages may also be in the form of removable memory modules in generally planar or prism shaped form similar to a pen or as a thermal conduction module.
Owner:IBM CORP

Reconfigurable service provision via a communication network

InactiveUS6330586B1Customer base for information services is particularly wideLarge capacityMultiplex system selection arrangementsData processing applicationsReconfigurabilityReusable software
A services provision system provides information services over one or more communications networks and has a software infrastructure divided into domains. Each domain has an intelligent software agent and this community of agents sits in a computing environment represented in each domain by a DPE kernel. The community of agents co-operates to provide service and service management functionality to a user. At least one of the agents is reconfigurable to change the functionality the system makes available. Reconfigurability is based on the use of a plurality of reusable software modules, the agent reconfiguring by selecting a new combination of modules. The software modules themselves incorporate rules, or policies, which determine process steps offered by the modules at run-time. These policies are external to the modules and may be loaded at run-time, allowing dynamic modification to functionality of the system. The system as a whole offers functionality associated with using services, providing them and managing them and the reconfigurability allows it to offer the different types of functionality in an efficient way. It also allows access control to functionality at different levels with particularly good security against fraudulent use.
Owner:BRITISH TELECOMM PLC

Storage device and information processing system

A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.
Owner:SONY CORP
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