11 results about "Unit memory" patented technology

A method includes determining an address associated with a data transform command in a container data structure which is in the data transform accelerator. The data transform accelerator is in communication with a host computing unit. In response to a determination that the address is in the container data structure, the method includes accessing the data transform command based on the address. The data transform command is in the host computing unit. The method includes obtaining metadata based on information in the data transform command. The metadata is in the data transform accelerator or spread out in the host computing unit memory and in the memory of data transform accelerator. The method includes configuring a data transform pipeline based on the metadata. The metadata can be shared in its entirety or partially by multiple data transform commands grouped together.

A communication system includes a target unit provided in a vehicle and including at least one target unit processor and at least one target unit memory coupled to each other; and a communication tool coupled to the target unit for bidirectional communication and including at least one communication tool processor and at least one communication tool memory coupled to each other. The communication tool processor transmits certain information including first certain data and a first padding value to the target unit. The target unit processor determines whether the first padding value matches a preset specific padding value, and transmits abnormality information to the communication tool when the first padding value does not match the specific padding value. Upon receiving the abnormality information, the communication tool processor transmits the certain information including the first certain data and a second padding value different from the first padding value to the target unit.

The application provides a data scheduling method and device and electronic equipment. The embodiment automatically identifies a cold unit memory (referred to as a cold unit memory) in a first memory, whose access frequency per unit time is less than a first set threshold, and a hot unit memory (referred to as a hot unit memory) in a second memory, whose access frequency per unit time is greater than or equal to a second set threshold, automatically schedules data in the hot unit memory in the second memory to move to an idle unit memory in the first memory, and automatically schedules data in the cold unit memory in the first memory to move to an idle unit memory in the second memory, so that data with high access frequency is stored in the local first memory of the system, and data with low access frequency is stored in the second memory which is expanded, the advantages of local memory high-speed access and memory capacity expansion are maximized, and the data access efficiency is improved.

Provided in the present application are a data scheduling method and apparatus, and an electronic device. In the embodiment, a unit memory (which is referred to as a cold unit memory), an access frequency per unit time of which is lower than a first set threshold, in a first memory and a unit memory (which is referred to as a hot memory unit), an access frequency per unit time of which is greater than or equal to a second set threshold, in a second memory are automatically identified, data in the hot unit memory in the second memory is automatically scheduled and migrated into an idle unit memory in the first memory, and data in the cold unit memory in the first memory is automatically scheduled and migrated into an idle unit memory in the second memory, such that data with high access frequency is stored in the local first memory of a system, and data with low access frequency is stored in the extended second memory, so as to maximize the advantages of high-speed access performed by means of a local memory and memory capacity expansion performed by means of an extended memory, thereby improving the data access efficiency.

To execute reprogramming under conditions that require the use of an electronic device.SOLUTION: A target unit memory includes a first memory region that stores an application for operating a target unit. A central unit memory includes a second memory region for temporarily storing at least a part of the application stored in the first memory region. A target unit processors performs update processing which causes the second memory region to store at least a part of the application stored in the first memory region, disables the at least a part of the application stored in the first memory region, and writes an updated application to the first memory region based on update data transferred from a communication unit. A central unit processor operates at least a part of functions of the target unit using the application stored in the second memory region, at least during a period from the start to the completion of the update processing.SELECTED DRAWING: Figure 8

According to the embodiment of the invention, an embedded flash memory element with a single polycrystalline structure, a manufacturing method of the embedded flash memory element and a neuromorphic hardware element using the embedded flash memory element are provided. The embedded flash memory element may include a plurality of unit memory cells, each unit memory cell including: a coupling transistor including a source region, a drain region, and a floating gate region, the source region and the drain region being connected to a word line; and a readout transistor including a source region connected to a source line and a drain region connected to a bit line, and sharing the floating gate region with the coupling transistor, the coupling transistor and the readout transistor may be configured as a gate-p-i-n diode structure.

A vehicle includes: an object unit including an object unit processor and an object unit memory coupled thereto; a communication unit including a communication unit processor and a communication unit memory coupled thereto; and a central unit including a central unit processor and a central unit memory coupled thereto. The object unit memory includes a first storage to store an application. The central unit memory includes a second storage to store part of the application. The communication unit processor performs a process including transferring update data to the object unit. The object unit processor performs a process including: storing the partial application in the second storage; disabling the partial application stored in the first storage; and performing an update process. The central unit processor causes part of a function of the object unit to operate by the application stored in the second storage at least during the update process.

In an image forming apparatus, an image forming unit can be replaced. An outer cover becomes in an open status when the image forming unit is replaced. An inner cover becomes in an open status with a manual operation with taking a predetermined time after the outer cover becomes in an open status when the image forming unit is replaced. A cover open / close sensor detects open and close statuses of the outer cover. The image forming unit includes a non-volatile unit memory. Further, the controller (a) performs data communication with the unit memory, and (b) if data communication with the unit memory is ongoing when the cover open / close sensor detects that the outer cover becomes in an open status, completes the data communication and cuts off power supply to the image forming unit before the predetermined time elapses.

The invention discloses a WiFi feature data structure optimization method for a mobile terminal, and the method comprises the steps: dividing WiFi feature data into AP, RATIO and MAX unit data for storage, loading MAX units in batches during the APP analysis of the mobile terminal, dispersing the memory use time, and reducing the memory peak value; the assembled unit data follows a fixed byte occupation rule, so that the size of the unit is predictable, excessive memory is prevented from being reserved, and the peak value is further reduced; data are assembled according to a specific sequence rule, a compact structure is formed, redundant intervals are reduced, the storage density is improved, a mobile terminal can efficiently access the data, the average memory overhead is reduced, meanwhile, the data are stored in a fixed sequence, analysis can be accessed in a memory address sequence, the memory utilization efficiency is improved, and the average overhead is also reduced; in addition, a fixed rule and an ordered structure are convenient for accurately distributing and releasing the memory, timely releasing the unit memory, avoiding invalid occupation leakage, reducing memory garbage, improving the memory utilization rate, reducing the management complexity and reducing fragment-related garbage.

According to an embodiment of the present application, provided are an embedded flash memory device of a single poly structure, a manufacturing method therefor, and a neuromorphic hardware device using same. The embedded flash memory device includes a plurality of unit memory cells. Each unit memory cell includes: a coupling transistor including a source region and a drain region which are connected to a word line, and a floating gate region; and a read-out transistor which includes a source region connected to a source line and a drain region connected to a bit line, and shares, with the coupling transistor, the floating gate region, and the coupling transistor and the read-out transistor may be configured in a gated-p-i-n diode structure.