7results about How to "Small cell size" patented technology

The invention belongs to the technical field of polymer foam materials, and particularly relates to an environment-friendly low-smoke flame-retardant PVC (polyvinyl chloride) foam board and a preparation method thereof. The foamed sheet is prepared from the following raw materials: PVC resin powder, a special modified synergistic flame retardant for PVC, a filler, a foaming regulator, a calcium-zinc stabilizer, polyethylene wax, oxidized polyethylene wax and epoxidized soybean oil, wherein the special modified synergistic flame retardant for PVC is a synergistic flame retardant prepared from DPO modified magnesium-aluminum hydrotalcite. A supercritical carbon dioxide twin-screw extrusion foaming device is adopted for preparation, a PVC special modified synergistic flame retardant is added into the raw materials, the hydrotalcite surface contains a long alkane chain, the interaction among the fillers is weakened, good dispersion in PVC can be realized, free radicals generated during combustion can be quenched, a combustion chain reaction can be terminated, and the flame retardant has a good flame retardant effect. Phosphoric acid substances decomposed by heating can promote the polymer base material to be dehydrated into carbon and insulate heat and oxygen. The prepared board can promote flame-retardant and smoke-suppression effects and is excellent in mechanical property.

The invention discloses a floating interactive intelligent display chip based on dynamic distance sensing and a preparation process, and relates to the field of integrated chip preparation, the floating interactive intelligent display chip comprises a substrate layer, a buffer layer, an intrinsic layer, a multi-quantum well layer, a barrier layer, a source electrode, a grid electrode, a p-GaN layer, an anode and a drain electrode, the buffer layer, the intrinsic layer, the multi-quantum well layer and the barrier layer are sequentially arranged on the substrate layer, and the source electrode, the grid electrode, the p-GaN layer, the anode and the drain electrode are sequentially arranged on the substrate layer. The source electrode is arranged on one side of the upper surface of the barrier layer, the grid electrode is arranged in the middle of the upper surface of the barrier layer, the p-GaN layer is arranged on the other side of the upper surface of the barrier layer, and the anode and the drain electrode are sequentially arranged above the p-GaN layer. An InGaN / GaN multi-quantum well structure is embedded into a p-GaN HEMT epitaxial layer structure to form a light-emitting HEMT structure, and a driving transistor, a light source and a photoelectric detector are subjected to monolithic integration, so that a floating interactive intelligent display chip with an epitaxial integrated structural characteristic is realized.

The present disclosure relates to a semiconductor memory device. Embodiments provide a memory capable of reducing a cell size. A memory according to an embodiment includes a laminate including first conductive films and first insulating films alternately laminated in a first direction. The first columnar body includes a first semiconductor portion, a first insulator portion, a second insulator portion, a third insulator portion, and a fourth insulator portion extending in a first direction in the stacked body. The second insulator portion includes: a first portion provided between the first insulator portion and the first conductive film; and a second portion provided between the first insulator portion and the first insulating film, the second portion having a thickness smaller than that of the first portion in a second direction orthogonal to the first direction. The plurality of first insulating films are laminated films of a second insulating film and a third insulating film or are formed by the third insulating film.

This invention discloses a planar gate SiC MOSFET device and its fabrication method. The fabrication method includes: depositing a first silicon oxide layer in a substrate; forming an N+ source region injection window mask through photolithography, development, and etching; covering the surface of the first silicon oxide layer above the P-type region with a first nitride layer; depositing a second silicon oxide layer, a second nitride layer, and a second polysilicon layer; using the second nitride layer as a barrier layer to planarize the second polysilicon layer; and sequentially etching away the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer above the P-type region to form a P+ injection window. This application, by changing the process steps, eliminates the need for a P+ mask, enabling self-alignment of N+ and P+ processes. It also avoids mask alignment problems caused by wafer warpage, reduces registration deviation, improves the accuracy of the injection window region, saves costs, and allows for smaller cell sizes and optimized specific on-resistance.

The invention discloses an SJ-MOSFET device. The SJ-MOSFET device comprises a first conductive type substrate; a first conductive type epitaxial layer; a source region; a body region; a second conductive type doped column; and the trench gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region. On the other hand, the invention discloses a manufacturing method. The grid electrode and the grid electrode groove are arranged on the side face of the doped column, a part of the grid electrode groove is arranged in the doped column, so that the area of the grid electrode groove occupying the MESA is small, the grid electrode groove is arranged towards the interior of the doped column, the cell size and the pitch between two source electrode contact holes can be reduced to the maximum extent, and the manufacturing cost is reduced. And meanwhile, no JFET resistor exists, so that the optimization of the on-resistance is realized.

The invention provides a semiconductor device which comprises an N + substrate, an N-epitaxial layer and a plurality of gate trenches, the N-epitaxial layer comprises a plurality of P + buried layers and a plurality of first N + regions, the first N + regions are alternately clamped in the middle of the N-epitaxial layer, the thickness of each first N + region is larger than that of each P + buried layer, and the thickness of each first N + region is larger than that of each P + buried layer. The two sides, close to the N + substrate and away from the N + substrate, of the first N + region protrude out of the P + buried layer; the plurality of first P + regions and the plurality of second N + regions are alternately arranged on one side, far away from the N + substrate, of the P well region; an opening of each gate trench penetrates through one side, far away from the N + substrate, of the P well region and is located on the N-epitaxial layer between the P well region and the N + substrate, and each second N + region is arranged on the outer side of the corresponding gate trench in a surrounding manner. According to the invention, the gate oxide is protected, the JFET region introduced into the device by the P-type region is reduced, and the on-resistance of the device is reduced.

The utility model discloses an integrated bidirectional switch MOSFET which comprises a first groove group and a second groove group which are symmetrically arranged along the horizontal central axis of an N-epitaxial layer, the first groove group and the second groove group respectively comprise a plurality of same strip-shaped grooves, gate oxide layers grow in the strip-shaped grooves, gate polycrystals are deposited in the gate oxide layers, and the gate polycrystals are deposited in the strip-shaped grooves. The grid polycrystals in the strip-shaped grooves in the first groove group form a first grid of the MOSFET, and the grid polycrystals in the strip-shaped grooves in the second groove group form a second grid of the MOSFET; a first P well layer is formed at the upper part of the N-epitaxial layer outside the first groove group, and a second P well layer is formed at the upper part of the N-epitaxial layer in the second groove group; a first N + active layer is formed at the upper part of the first P well layer, and the first N + active layer is in short circuit with the grid polycrystal in the first groove group to form a first source electrode of the MOSFET; a second N + active layer is formed on the lower portion of the second P well layer, the second N + active layer and the grid polycrystal in the second groove group are in short circuit to form a second source electrode of the MOSFET, and the first source electrode and the second source electrode form a bidirectional switch of the MOSFET.