2results about How to "Small cell size" patented technology

The invention discloses a floating interactive intelligent display chip based on dynamic distance sensing and a preparation process, and relates to the field of integrated chip preparation, the floating interactive intelligent display chip comprises a substrate layer, a buffer layer, an intrinsic layer, a multi-quantum well layer, a barrier layer, a source electrode, a grid electrode, a p-GaN layer, an anode and a drain electrode, the buffer layer, the intrinsic layer, the multi-quantum well layer and the barrier layer are sequentially arranged on the substrate layer, and the source electrode, the grid electrode, the p-GaN layer, the anode and the drain electrode are sequentially arranged on the substrate layer. The source electrode is arranged on one side of the upper surface of the barrier layer, the grid electrode is arranged in the middle of the upper surface of the barrier layer, the p-GaN layer is arranged on the other side of the upper surface of the barrier layer, and the anode and the drain electrode are sequentially arranged above the p-GaN layer. An InGaN / GaN multi-quantum well structure is embedded into a p-GaN HEMT epitaxial layer structure to form a light-emitting HEMT structure, and a driving transistor, a light source and a photoelectric detector are subjected to monolithic integration, so that a floating interactive intelligent display chip with an epitaxial integrated structural characteristic is realized.

This invention discloses a planar gate SiC MOSFET device and its fabrication method. The fabrication method includes: depositing a first silicon oxide layer in a substrate; forming an N+ source region injection window mask through photolithography, development, and etching; covering the surface of the first silicon oxide layer above the P-type region with a first nitride layer; depositing a second silicon oxide layer, a second nitride layer, and a second polysilicon layer; using the second nitride layer as a barrier layer to planarize the second polysilicon layer; and sequentially etching away the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer above the P-type region to form a P+ injection window. This application, by changing the process steps, eliminates the need for a P+ mask, enabling self-alignment of N+ and P+ processes. It also avoids mask alignment problems caused by wafer warpage, reduces registration deviation, improves the accuracy of the injection window region, saves costs, and allows for smaller cell sizes and optimized specific on-resistance.