16results about How to "Small cell size" patented technology

The invention relates to the field of novel polymer materials, and particularly discloses a degradable expandable polylactic acid polymer foam material and a preparation method thereof, the degradable expandable polylactic acid polymer foam material comprises the following raw materials: a polylactic acid-starch-polyamide blending modified mixture, polylactic acid foam material waste leftover materials, a foaming agent, a nucleating agent and an activating agent; the preparation method comprises the following steps: melting and mixing polylactic acid, acylated starch and polyamide in proportion to prepare a polylactic acid-starch-polyamide blending modified mixture, weighing the polylactic acid-starch-polyamide blending modified mixture, mixing the polylactic acid-starch-polyamide blending modified mixture with the polylactic acid foaming material waste leftover materials, the foaming agent, the nucleating agent and the activating agent, and performing extrusion molding to obtain the polylactic acid foaming material. Extruding and pelletizing to obtain foaming master batch, and foaming and forming; the preparation method has the characteristics that the expandable performance of the polylactic acid material is improved, and the prepared polylactic acid foam material is more uniform in cell size distribution, small in cell size and excellent in mechanical property.

The invention relates to a power semiconductor device, in particular to a groove type MOSFET device, and provides a novel shield gate groove type field effect transistor in order to reduce the cellular size of the device and achieve better compromise between breakdown voltage and on resistance. The semiconductor cell trench is composed of a plurality of deep trenches and shallow trenches which are periodically arranged at intervals in the Z direction, the deep trenches are 0.3-4 microns deeper than the shallow trenches, gate electrodes located above the trenches and shield gate electrodes located below the trenches are arranged in the shallow trenches and the deep trenches, and the gate electrodes and the shield gate electrodes are isolated from each other. The gate electrode is isolated from the corresponding side wall of the groove through a gate oxide layer, and the shield gate electrode is isolated from the corresponding side wall of the groove through a groove isolation layer; the gate electrode and the shield gate electrode are connected in the Z direction, and the shield gate electrode changes up and down along with different depths of the groove in the Z direction and is connected to the source electrode metal located on the upper surface at a proper position.

The invention belongs to the technical field of polymer foam materials, and particularly relates to an environment-friendly low-smoke flame-retardant PVC (polyvinyl chloride) foam board and a preparation method thereof. The foamed sheet is prepared from the following raw materials: PVC resin powder, a special modified synergistic flame retardant for PVC, a filler, a foaming regulator, a calcium-zinc stabilizer, polyethylene wax, oxidized polyethylene wax and epoxidized soybean oil, wherein the special modified synergistic flame retardant for PVC is a synergistic flame retardant prepared from DPO modified magnesium-aluminum hydrotalcite. A supercritical carbon dioxide twin-screw extrusion foaming device is adopted for preparation, a PVC special modified synergistic flame retardant is added into the raw materials, the hydrotalcite surface contains a long alkane chain, the interaction among the fillers is weakened, good dispersion in PVC can be realized, free radicals generated during combustion can be quenched, a combustion chain reaction can be terminated, and the flame retardant has a good flame retardant effect. Phosphoric acid substances decomposed by heating can promote the polymer base material to be dehydrated into carbon and insulate heat and oxygen. The prepared board can promote flame-retardant and smoke-suppression effects and is excellent in mechanical property.

The invention relates to the field of polyurethane materials, in particular to polyether polyol and a preparation method thereof as well as polyurethane rigid foam and a preparation method of the polyurethane rigid foam. Polyether polyol with a structure as shown in a formula (II), which is formed by taking a compound with a structure as shown in a formula (I) as an initiator, has a non-planar and rigid large annular hollow structure; a multi-benzene-ring structure can be formed in a polyurethane rigid foam skeleton, so that the strength of the foam skeleton is improved; the volatilized physical foaming agent is adsorbed in the reaction process, especially in the early stage of the reaction, the volatilization rate of the physical foaming agent is reduced, and exchange between the foaming agent in foam holes and air after foam is formed is reduced, so that foam heat conduction and foam heat conduction attenuation are reduced; the polyurethane rigid foam has the advantages of low density, low heat conductivity coefficient, high foam strength and excellent aging resistance.

The invention discloses a floating interactive intelligent display chip based on dynamic distance sensing and a preparation process, and relates to the field of integrated chip preparation, the floating interactive intelligent display chip comprises a substrate layer, a buffer layer, an intrinsic layer, a multi-quantum well layer, a barrier layer, a source electrode, a grid electrode, a p-GaN layer, an anode and a drain electrode, the buffer layer, the intrinsic layer, the multi-quantum well layer and the barrier layer are sequentially arranged on the substrate layer, and the source electrode, the grid electrode, the p-GaN layer, the anode and the drain electrode are sequentially arranged on the substrate layer. The source electrode is arranged on one side of the upper surface of the barrier layer, the grid electrode is arranged in the middle of the upper surface of the barrier layer, the p-GaN layer is arranged on the other side of the upper surface of the barrier layer, and the anode and the drain electrode are sequentially arranged above the p-GaN layer. An InGaN / GaN multi-quantum well structure is embedded into a p-GaN HEMT epitaxial layer structure to form a light-emitting HEMT structure, and a driving transistor, a light source and a photoelectric detector are subjected to monolithic integration, so that a floating interactive intelligent display chip with an epitaxial integrated structural characteristic is realized.

The present disclosure relates to a semiconductor memory device. Embodiments provide a memory capable of reducing a cell size. A memory according to an embodiment includes a laminate including first conductive films and first insulating films alternately laminated in a first direction. The first columnar body includes a first semiconductor portion, a first insulator portion, a second insulator portion, a third insulator portion, and a fourth insulator portion extending in a first direction in the stacked body. The second insulator portion includes: a first portion provided between the first insulator portion and the first conductive film; and a second portion provided between the first insulator portion and the first insulating film, the second portion having a thickness smaller than that of the first portion in a second direction orthogonal to the first direction. The plurality of first insulating films are laminated films of a second insulating film and a third insulating film or are formed by the third insulating film.

This invention discloses a planar gate SiC MOSFET device and its fabrication method. The fabrication method includes: depositing a first silicon oxide layer in a substrate; forming an N+ source region injection window mask through photolithography, development, and etching; covering the surface of the first silicon oxide layer above the P-type region with a first nitride layer; depositing a second silicon oxide layer, a second nitride layer, and a second polysilicon layer; using the second nitride layer as a barrier layer to planarize the second polysilicon layer; and sequentially etching away the second nitride layer, the second silicon oxide layer, the first nitride layer, and the first silicon oxide layer above the P-type region to form a P+ injection window. This application, by changing the process steps, eliminates the need for a P+ mask, enabling self-alignment of N+ and P+ processes. It also avoids mask alignment problems caused by wafer warpage, reduces registration deviation, improves the accuracy of the injection window region, saves costs, and allows for smaller cell sizes and optimized specific on-resistance.

The invention discloses an SJ-MOSFET device. The SJ-MOSFET device comprises a first conductive type substrate; a first conductive type epitaxial layer; a source region; a body region; a second conductive type doped column; and the trench gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region. On the other hand, the invention discloses a manufacturing method. The grid electrode and the grid electrode groove are arranged on the side face of the doped column, a part of the grid electrode groove is arranged in the doped column, so that the area of the grid electrode groove occupying the MESA is small, the grid electrode groove is arranged towards the interior of the doped column, the cell size and the pitch between two source electrode contact holes can be reduced to the maximum extent, and the manufacturing cost is reduced. And meanwhile, no JFET resistor exists, so that the optimization of the on-resistance is realized.

The invention relates to the technical field of communication, in particular to a frequency selective surface structure for a 5G base station and a filtering antenna array of the frequency selective surface structure. The frequency selective surface structure for the 5G base station comprises at least one filtering unit, the filtering unit is in a sheet shape, and the filtering unit comprises an external metal layer, a dielectric substrate, a middle metal layer, another dielectric substrate and another external metal layer which are stacked in sequence; the outer metal layer comprises a plurality of first metal sheets, the first metal sheets are arranged in a square array, the first metal sheets are square metal sheets, aperture windows are formed in the middles of the first metal sheets, gap grooves are formed in the four faces of each first metal sheet, and the aperture windows and the gap grooves are separated through bent connecting parts. According to the frequency selective surface structure for the 5G base station, the requirement of a 5G Massive MIMO antenna base station for a filter in a radio frequency channel can be effectively released, and the frequency selective surface structure has the advantages of being low in loss, wide in scanning angle, good in directional diagram conformality, simple in structure and low in implementation cost.

The invention provides a semiconductor device which comprises an N + substrate, an N-epitaxial layer and a plurality of gate trenches, the N-epitaxial layer comprises a plurality of P + buried layers and a plurality of first N + regions, the first N + regions are alternately clamped in the middle of the N-epitaxial layer, the thickness of each first N + region is larger than that of each P + buried layer, and the thickness of each first N + region is larger than that of each P + buried layer. The two sides, close to the N + substrate and away from the N + substrate, of the first N + region protrude out of the P + buried layer; the plurality of first P + regions and the plurality of second N + regions are alternately arranged on one side, far away from the N + substrate, of the P well region; an opening of each gate trench penetrates through one side, far away from the N + substrate, of the P well region and is located on the N-epitaxial layer between the P well region and the N + substrate, and each second N + region is arranged on the outer side of the corresponding gate trench in a surrounding manner. According to the invention, the gate oxide is protected, the JFET region introduced into the device by the P-type region is reduced, and the on-resistance of the device is reduced.

The utility model discloses an integrated bidirectional switch MOSFET which comprises a first groove group and a second groove group which are symmetrically arranged along the horizontal central axis of an N-epitaxial layer, the first groove group and the second groove group respectively comprise a plurality of same strip-shaped grooves, gate oxide layers grow in the strip-shaped grooves, gate polycrystals are deposited in the gate oxide layers, and the gate polycrystals are deposited in the strip-shaped grooves. The grid polycrystals in the strip-shaped grooves in the first groove group form a first grid of the MOSFET, and the grid polycrystals in the strip-shaped grooves in the second groove group form a second grid of the MOSFET; a first P well layer is formed at the upper part of the N-epitaxial layer outside the first groove group, and a second P well layer is formed at the upper part of the N-epitaxial layer in the second groove group; a first N + active layer is formed at the upper part of the first P well layer, and the first N + active layer is in short circuit with the grid polycrystal in the first groove group to form a first source electrode of the MOSFET; a second N + active layer is formed on the lower portion of the second P well layer, the second N + active layer and the grid polycrystal in the second groove group are in short circuit to form a second source electrode of the MOSFET, and the first source electrode and the second source electrode form a bidirectional switch of the MOSFET.

The invention provides a high-strength light release film and a preparation method thereof. Comprising the following steps: S1, taking 3-6 parts of amphiphilic micron network particles, dispersing the amphiphilic micron network particles in 25 parts of a formamide solution, then adding 5 parts of a 1mg / ml PVA (Polyvinyl Alcohol) aqueous solution, uniformly stirring, then adding 1-2 parts of glutaraldehyde, and stirring for 30 minutes; s2, adding 60 parts of water, uniformly stirring, casting to one surface of the porous foam PS, and carrying out vacuum drying at 40 DEG C for 8 hours; and S3, taking out, casting to the other side of the porous foam PS, and carrying out vacuum drying at 40 DEG C for 24 hours. A three-layer structure is adopted, the middle layer is the porous foam PS, the upper layer and the lower layer are the release layers with the compact surfaces, the middle foam layer can greatly reduce the weight of the release film, the upper layer and the lower layer are the release layers with the compact surfaces, and the strength of the release film can be kept through the microstructure combining internal porosity and compact surfaces.

The invention discloses a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which belongs to the technical field of semiconductors and comprises an N-type substrate, an N-type epitaxial layer is arranged at the top of the N-type substrate, a plurality of P-type well regions are transversely arranged in the N-type epitaxial layer, the distances between the P-type well regions are equal, and the P-type well regions are alternately arranged in a wide-narrow manner in the longitudinal direction. A P body contact region is arranged in a part of the P type well region, an N type source region is arranged in the P type well region, one side of the N type source region is connected with the P body contact region, the top of the N type epitaxial layer is further provided with a source end electrode matched with the P body contact region, the bottom of the source end electrode is connected with the P body contact region, and in the transverse direction, the P body contact region is connected with the N type source region. And the P-type well regions with the P body contact regions and the P-type well regions without the P body contact regions are alternately arranged. The P body contact region is arranged in part of the MOS structure, so that the cellular size of the MOS structure is reduced, the channel density is higher, and the specific on-resistance of the device is smaller.

The present application discloses a super junction power device, including a substrate layer, an epitaxial layer, a gate structure and a dielectric region located below the gate structure, a well region located on both sides of the gate structure and the dielectric region, a source region located in the well region, and a well contact region. A semiconductor layer having a second conductivity type is covered on part of the sidewalls of the dielectric region. The portion of the dielectric region that is not covered by the semiconductor layer is at least located below the gate structure between the source regions. The super junction power device provided by the present application has a significantly reduced cell size and good conduction performance of the device. At the same time, the manufacturing method provided by the present application is simple and easy to implement, which can significantly reduce process time and manufacturing costs.

This invention discloses a compact MIMO antenna system based on a connecting line, comprising a ground plane, a first antenna, a second antenna, and a connecting line disposed outside the first and second antennas. The outer ends of the first antenna and the second antenna are respectively connected to the ground plane. One end of the connecting line is connected to a non-end portion of the first antenna, and the other end of the connecting line is connected to a non-end portion of the second antenna. The compact MIMO antenna system based on the connecting line of this invention features a compact antenna structure, small antenna element size, and close element spacing, achieving a highly integrated, highly compact, highly isolated, and compatible MIMO antenna system with multiple antenna types. This invention is applicable to various wireless communication devices, especially to the application of large-scale arrays in terminal devices.

The invention discloses a C / Ku double-frequency common-caliber phased array scanning antenna, and relates to the technical field of scanning antennae, the C / Ku double-frequency common-caliber phased array scanning antenna comprises a Ku frequency band patch and a C frequency band antenna oscillator, and the Ku frequency band patch and the C frequency band antenna oscillator are distributed on a perforated printed board in a square array according to the caliber surface; all the C-frequency-band antenna oscillators are arranged in the same direction and are perpendicular to the polarization direction of the ku-frequency-band microstrip patch, the Ku-frequency-band patch and the C-frequency-band antenna oscillators both adopt a coaxial feed form, and the Ku-frequency-band patch adopts a coupling slot form to radiate the patch; in the strip line polarization direction of the Ku frequency band microstrip patch, a dummy dummy C oscillator without excitation is arranged between two adjacent C frequency band antenna oscillators in each row and each column of C frequency band antennas. According to the invention, the microstrip patch of the ku frequency band and the oscillator antenna of the C frequency band are reasonably arranged and are in the same spatial range, and a dummy encryption decoupling technology is adopted, so that the dual-frequency antenna array planes with different physical forms are integrated, and the coupling effect is reduced.