44 results about "Thin oxide" patented technology

The invention discloses a surface treatment process of a hydraulic rod and a coating monitoring system, relates to the technical field of electroplating, and aims to solve the problems that various complementary sensing technologies cannot be integrated, information such as thickness, uniformity and microstructure cannot be synchronously acquired in a lossless, in-situ and real-time manner, and closed-loop control cannot be formed based on the information in the background technology. According to the scheme, the method comprises the steps that PR electrolytic degreasing is conducted, a workpiece serves as an anode, an oil film is torn through the oxygen evolution effect, an extremely-thin oxidation film possibly existing on the surface of the workpiece is dissolved, base metal is completely activated, and an optimal combination basis is provided for a follow-up coating; and washing with hot water, namely removing residual alkaline degreasing fluid and emulsified oil stains by using hot water with the temperature higher than 60 DEG C in a stirring and spraying manner. According to the method, multi-dimensional information such as the thickness, the uniformity and the microstructure can be synchronously obtained in a lossless, in-situ and real-time mode in the surface treatment process, closed-loop control is formed based on the information, and it is ensured that plating growth is always located on the optimal track.

Techniques for joining dissimilar materials in microelectronics are provided. Example techniques direct-bond dissimilar materials at an ambient room temperature, using a thin oxide, carbide, nitride, carbonitride, or oxynitride intermediary with a thickness between 100-1000 nanometers. The intermediary may comprise silicon. The dissimilar materials may have significantly different coefficients of thermal expansion (CTEs) and / or significantly different crystal-lattice unit cell geometries or dimensions, conventionally resulting in too much strain to make direct-bonding feasible. A curing period at ambient room temperature after the direct bonding of dissimilar materials allows direct bonds to strengthen by over 200%. A relatively low temperature anneal applied slowly at a rate of 1° C. temperature increase per minute, or less, further strengthens and consolidates the direct bonds. The example techniques can direct-bond lithium tantalate LiTaO3 to various conventional substrates in a process for making various novel optical and acoustic devices.

The invention provides a crystalline silicon cell and a manufacturing method thereof, the crystalline silicon cell comprises an N-type silicon substrate, a tunneling oxide layer, an N + poly layer, AIOx / SiNx, a silver metal electrode, a P + layer and an aluminum metal electrode, and the manufacturing method of the crystalline silicon cell comprises the following operation steps: S1, double-sided cleaning and texturing: adopting an N-type silicon wafer with the size of 182.2 * 183.75, cleaning and texturing the surface of the silicon wafer with alkali, and cleaning and texturing the surface of the N-type silicon wafer with the size of 182.2 * 183.75; s2, phosphorus doping is carried out, an N + layer is formed, a thin oxide layer is deposited firstly, and then phosphorus doping is completed through a low-pressure diffusion furnace. According to the crystalline silicon cell and the manufacturing method thereof, the use amount of silver paste is reduced by about 35% through texturing, phosphorus doping, laser patterning, etching alkali polishing, boron diffusion, cleaning, atomic layer deposition, front and back anti-reflection layer preparation, silk-screen printing and laser-assisted sintering and through a cell back aluminum grid line laser induction process.

A device including an inverter circuit, a hysteresis control circuit, and a high-side input level shifter. The inverter circuit having an output and including at least two series connected PMOS transistors connected, at the output, in series to at least two series connected NMOS transistors. The hysteresis control circuit coupled to the output to provide feedback to the at least two series connected PMOS transistors and to the at least two series connected NMOS transistors. The high-side input level shifter connected to gates of the at least two PMOS transistors and configured to shift a low level of an input signal to a higher level and provide the higher level to one or more of the gates of the at least two PMOS transistors.

To provide a field effect transistor (FET) which is used in a microfabricated semiconductor integrated circuit and has a small off-current.SOLUTION: The field-effect transistor includes a flaky oxide semiconductor having a thickness of 1 nm or more and 30 nm or less and formed substantially perpendicularly to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate having a stripe shape and a width of 10 nm or more and 100 nm or less formed to cover the gate insulating film. In this structure, since the gate covers three sides of the thin piece-like oxide semiconductor, electrons injected from the source and the drain can be efficiently removed, a region between the source and the drain can be substantially depleted, and the off-state current can be reduced.SELECTED DRAWING: Figure 1

The invention relates to the technical field of semiconductor power devices, in particular to a discrete device and a manufacturing method thereof, and the method comprises the steps: providing an N + substrate and growing an N epitaxial layer; depositing and patterning a masking layer to etch to form a deep groove; growing a thin oxide layer and depositing a thick oxide layer; depositing and etching polycrystalline silicon to form a shield gate; removing part of the oxide layer, depositing a new oxide layer, and grinding; depositing an oxide layer as a masking layer, and forming a multidirectional shallow slot pattern through photoetching and etching; adjusting the thickness of the oxide layer through wet etching, growing gate oxide and forming gate polycrystalline silicon; completing the steps of P well and N + source region injection, dielectric layer deposition, contact hole etching and metallization to form a device; the layout design of multidirectional cellular layout is introduced, the process limitation of traditional one-way pitch miniaturization is broken through, on the premise of not depending on a higher-level manufacturing process, the channel density of a unit area is remarkably improved, the on-resistance of the device is effectively reduced, and good process compatibility and reliability are achieved.

The invention provides a method for eliminating the color difference defect on the surface of hot-rolled low-carbon thin strip steel with high efficiency and low cost. According to the method, the chemical components and the strip casting temperature of the hot-rolled low-carbon thin strip steel and the introduction amount of N2 protective atmosphere in the first hot box, the second hot box and the third hot box are optimized, meanwhile, the air flow of the upper surface and the lower surface in the third hot box is controlled, the low oxidation environment is kept, it is guaranteed that rolling lubrication of the hot-rolled low-carbon thin strip steel is guaranteed, and thin oxide skin is generated before rolling; and then the layer cooling outlet temperature and the coiling temperature are controlled, and the uniformity of the strip steel transverse cooling outlet temperature and the coiling temperature is guaranteed. By applying the method, the thickness and the structure of the hot-rolled low-carbon thin strip steel oxide skin can be uniform and consistent, and the defect of color difference on the surface of the thin-strip cast-rolled low-carbon thin strip steel is efficiently eliminated at low cost.

Techniques to utilize thin-oxide devices, such as gate-all-around metal-oxide-semiconductor field-effect transistors (MOSFETs), in high voltage environments, such as to provide a high-voltage based low-power, temperature dependent, thin-oxide-only on-chip high current low drop out (LDO) regulator in a system-on-chip (SoC), such as provide power to configuration random-access memory (CRAM) cells distributed throughout configurable / programmable circuitry. Thin-oxide only circuitry may include thin-oxide-only amplifier circuitry, thin-oxide-only power gate circuitry, thin-oxide-only level shifters that shift voltage swings of control signals to voltage domains of the power gate circuitry, and thin-oxide-only clamp circuitry.

The invention discloses an MOSFET capable of reducing dynamic parameters of a device and a preparation method, and relates to the technical field of semiconductors. The epitaxial layer is provided with an active region groove, and the active region groove is internally provided with grid polycrystalline silicon and first source polycrystalline silicon which are arranged at intervals up and down and is filled with a first dielectric layer; compared with a traditional SGT device structure formed in one step, the IPO thickness is greatly increased, the dynamic parameters of the device are reduced, the reliability is improved, and meanwhile, the additional photomask cost is not increased. The problem of electric field concentration caused by a too thin oxide layer at a grid corner position during the design of a low VTH device under a relatively thin gate oxide due to a relatively thin IPO formed in one step is solved.

The invention discloses a preparation method of a PVD (physical vapor deposition) corrosion-resistant coating on the surface of an aluminum alloy, and belongs to the technical field of corrosion-resistant coatings, the method comprises the following steps: pretreating and cleaning an aluminum alloy matrix, depositing a gradient functional layer by adopting a physical vapor deposition technology, and periodically pausing in the growth process of the gradient functional layer, switching to a reactive sputtering mode for in-situ deposition of an ultrathin oxide hole sealing layer to form a composite structure with alternate gradient layers and hole sealing layers; and then a self-healing outer layer containing corrosion inhibitor microcapsules and an outermost color layer or hydrophobic functional layer are deposited on the surface of the composite structure. Through collaborative integration of gradient component design, periodic in-situ deep hole sealing and a self-repairing function, coating microdefects are effectively blocked, the film-substrate binding force, the corrosion resistance and the damage tolerance are remarkably improved, the technological process is green and environmentally friendly, and the method is suitable for protection of aluminum alloy parts with the strict requirement for corrosion resistance.

The application discloses a Gen type channel field effect transistor structure with low-resistance ohmic contact and a preparation method thereof. The structure comprises a p-type Ge substrate, n-type Ge source / drain regions arranged on both sides of the p-type Ge substrate, ultrathin oxide layers arranged on the n-type Ge source / drain regions, a gate passivation layer, a gate dielectric layer and a gate metal layer arranged from bottom to top between the n-type Ge source / drain regions and on the top of the p-type Ge substrate, and insulating side walls arranged on both sides of the gate metal layer. Source electrode adhesion layers, source electrodes and drain electrode adhesion layers and drain electrodes are arranged on the outside of the insulating side walls and on the ultrathin oxide layers. Gate electrode adhesion layers and gate electrodes are arranged between the insulating side walls and on the gate metal layer. The source electrodes and the drain electrodes are connected with the n-type Ge source / drain regions through conductive filament channels penetrating through the ultrathin oxide layers. The ultrathin oxide layer is embedded between the metal and the n-Ge semiconductor, and the oxide layer is broken through by using an electroforming process, so that the low-resistance ohmic contact is realized.

The present disclosure relates to electrostatic discharge (ESD) protection circuitry of an electronic device, which is capable of protecting thin-oxide metal- oxide-semiconductor (MOS) transistors within the electronic device during an ESD event and / or a power-on transient stage without large current leakage. The disclosed ESD protection circuitry at least includes a protection switch and a switch controller. The protection switch is coupled between an external pin of the electronic device and internal circuitry of the electronic device, which is composed of thin-oxide MOS transistors. The switch controller is configured to control the protection switch to be conducting or non-conducting based on both a status of a first voltage supply powering the ESD protection block and a presence of an ESD event at the external pin, such that the external pin is electrically connected to or disconnected from the internal circuitry.

The application belongs to the technical field of surface defect detection, and particularly relates to a forging part surface defect detection device, which comprises a base and a PLC control host computer, and further comprises: a material clamping and transferring mechanism fixedly arranged on the base and used for fixing an annular forging part to be detected; a pretreatment mechanism fixedly connected to one side of the upper end of the base and used for treating impurities and dirt on the surface of the forging part before detection; a positive heating mechanism fixedly connected to the rear side of the upper end of the base and located directly above the material clamping and transferring mechanism; and a thermal imaging detection mechanism. The application is adapted to high-temperature working conditions by means of non-contact detection, is not affected by material magnetism and conductivity, can penetrate a thin oxide layer, quickly covers a complex curved surface, accurately identifies micro-cracks, pits and other defects, greatly improves detection accuracy and efficiency, and simultaneously reduces manual labor intensity.

A method for forming an oxide layer includes forming a protective interlayer oxide on sidewalls of a trench formed on a substrate, forming a silicon nitride layer on the protective interlayer oxide by a plasma enhanced atomic layer deposition (PEALD) process using a nitrogen-containing process gas, the silicon nitride layer has a concentration gradient of nitrogen that varies from a high concentration away from the protective interlayer oxide to a low concentration near the protective interlayer oxide, and performing a conversion process to oxidize the formed silicon nitride layer to at least partially convert the formed silicon nitride layer to a silicon oxide layer.

The invention discloses a black phosphorus crystal treatment method based on controllable micro-oxidation and application of the black phosphorus crystal treatment method in liquid phase stripping. Firstly, black phosphorus crystals are pretreated in an inert atmosphere, vacuum drying is performed after water washing and alcohol washing, surface impurities are removed to improve oxidation uniformity, and the black phosphorus crystals are crushed to a certain size range for standby application. And then exposing the pretreated black phosphorus crystal in a low-concentration oxygen atmosphere for low-temperature micro-oxidation treatment, inducing the surface and layer edge of the crystal to form an extremely thin oxide layer, immediately quenching in an inert atmosphere after treatment, cooling to room temperature, terminating the oxidation reaction and stabilizing the structure of the oxide layer. And finally, dispersing the quenched black phosphorus sample in a specific solvent system for liquid-phase ultrasonic stripping, thereby effectively improving the stripping efficiency of the black phosphorus crystal and the quality of the black phosphorus nanosheet. Compared with a traditional preparation process, the black phosphorus crystal treatment method based on the controllable micro-oxidation technology realizes interlayer binding force optimization only through surface bonding reconstruction, does not destroy a black phosphorus main body structure, does not need to introduce additional substances, is simple to operate and easy to amplify, and is suitable for large-scale production. The method is suitable for liquid phase stripping large-scale controllable preparation of the high-quality black phosphorus nanosheet.

The invention belongs to the technical field of battery manufacturing, and particularly relates to a method for prolonging the service life of a boron diffusion quartz device, which comprises the following steps: S1, pretreatment: carrying out RCA standard cleaning on a silicon wafer; s2, wafer loading and furnace tube pretreatment: loading the cleaned silicon wafer to a quartz boat, feeding the quartz boat into a tubular diffusion furnace, and carrying out nitrogen purging to remove residual air in the furnace tube; s3, raising the temperature, carrying out closed tube leakage detection, and after stabilization, detecting the sealing performance of the furnace tube in a nitrogen pressure maintaining mode; s4, pre-oxidation: forming a thin oxidation film layer on the surface of the silicon wafer; s5, boron source deposition; s6, carrying out propelling treatment; s7, post-oxidation is carried out, and a BSG layer is prepared; s8, back pressure purging and cooling are carried out; and S9, taking the sheet. The core oxidation temperature can be reduced from 1040 DEG C to 1000 DEG C or below and is far away from the softening temperature of a quartz material, softening deformation of devices such as a quartz furnace tube and a quartz boat is remarkably reduced, the service life of the devices is prolonged, and the accessory replacement and production line shutdown cost is reduced.

A level shifter may include a first transistor stack including at least four transistors arranged from a first voltage source to ground, including second and third transistors coupled with bias voltage source, and a fourth transistor coupled with an input to receive an input signal at a second voltage or ground. The level shifter may include a second transistor stack comprising at least four transistors arranged from the first voltage source to ground, including second and third transistors coupled with the bias voltage source, and a fourth transistor to receive an inverse of the input signal. A first transistor of the first transistor stack is cross-coupled with a first transistor of the second transistor stack. A level shifter may include a first output coupled with the second transistor stack between the second and third transistors to provide a first output signal at the first voltage or ground.

An amplifier circuit with a high pass filter is constructed to include an operational amplifier (op amp) with a feedback loop in which a capacitor is in parallel with a field effect transistor (FET) configured as a gate tunneling resistor. To configure as a gate tunneling resistor, the source and drain of the FET are tied together, and large resistance is provided through the thin oxide layer between the gate and the source / drain. A bias voltage to the FET can be provided through a separate FET, also configured as a gate tunneling resistor. Additional gate tunneling FETs, also in parallel with the capacitor, can be switched into the circuit in order to provide different resistances, and thus different corner frequencies of the filter. Bias voltages may be supplied by one or more gate tunneling FETs. A fully differential op amp can have complementary feedback loops from its differential outputs, each feedback loop employing one or more gate tunneling FETs.

The invention provides a manufacturing method of a semiconductor structure, the method includes providing a substrate, forming two shallow trench isolation structures in the substrate. A first region, a second region and a third region are defined between the two shallow trench isolation structures, and the second region is located between the first region and the third region. Next, an oxide layer is formed in the first region, the second region and the third region, and the oxide layer directly contacts the two shallow trench isolation structures. The oxide layer in the second region is then removed, and another oxide layer is formed in the first region, the second region and the third region, so that a thick oxide layer is formed in the first and third regions, and a thin oxide layer is formed in the second region.

The invention provides a preparation process of a groove type silicon carbide gate oxide layer, a groove type silicon carbide wafer with a gate oxide layer and a metal oxide semiconductor field effect transistor. The method comprises the following steps of: depositing and growing a thin oxide layer after etching a groove, depositing polycrystalline silicon, filling the whole groove with the polycrystalline silicon, only reserving the polycrystalline silicon at the bottom of the groove by adopting a polycrystalline silicon back-etching process, and finally performing a thermal oxidation process. Silicon carbide is oxidized in a high-temperature oxygen atmosphere, and polycrystalline silicon at the bottom of the groove is oxidized into an oxide layer; the method not only can ensure that a layer of high-quality thermal oxide is generated on the side wall of the trench as a gate oxide layer, but also can realize that the oxide layer formed by oxidation of polycrystalline silicon at the bottom of the trench is thicker than the oxide layer on the side wall of the trench, thereby improving the voltage endurance capability of the bottom of the trench device.

The application relates to the technical field of metal materials and preparation technology thereof, in particular to a processing method of nickel-titanium wire material with an ultrathin oxide film, which has the technical scheme as follows: step 1: polishing the surface of the initial wire material to remove the surface oxide film; step 2: placing the wire material into an annealing furnace to perform atmosphere protection annealing; step 3: cold drawing the wire material, and the deformation amount of the wire material after the drawing is 30%-70%; judging whether the diameter d of the wire material is equal to the diameter D of the finished wire material, if the diameter d of the wire material is greater than the diameter D of the finished wire material, repeatedly performing step 2 and step 3, and if the diameter d of the wire material is equal to the diameter D of the finished wire material, entering step 4; step 4: placing the wire material into an annealing furnace to perform atmosphere protection annealing, so that the nickel-titanium wire material has a relatively thin oxide film, the surface smoothness is maintained, and the nickel-titanium wire material has good biocompatibility.

Various embodiments of methods are provided herein for oxidizing a surface of a semiconductor substrate. In the disclosed embodiments, gas-phase oxidizing free radicals are generated and used to oxidize an exposed surface of a material and form a thin oxide film there on. The gas-phase oxidizing free radicals are generated via ultraviolet (UV) photolysis of vaporized peroxide solutions. In some embodiments, an aqueous hydrogen peroxide (H2O2) solution is vaporized and photolyzed with UV light to form gas-phase hydroxyl (HO*) free radicals, which oxidize the exposed surface of the material to form a thin oxide film on the exposed surface of the material.

With this invention, electronic circuit components such as transistors, diodes, zener diodes and varicap diodes, which are conventionally manufactured with semiconductors, can be produced without semiconductors by means of a much simpler and cheaper technology, and by the same technology a compensation capacitor can be manufactured whose capacitance is automatically varied so as to follow changes in the load simultaneously. This principle may also be applied in other areas such as microwaves. In simple terms, the electric and magnetic fields of the main capacitor are blocked by a control voltage and varied between zero and maximum values, and as a result the capacitance of the main capacitor is changed. The fundamental principle here is the control of the electric and magnetic fields between the two conductive plates of a fixed-capacitance capacitor. For this purpose, a control voltage is applied between a third metallic plate, designed as a grid or similar structure so as not to block the electric and magnetic fields of the main capacitor and placed closer to one of the two plates, and the adjacent metallic plate, while a DC voltage (VDD) of suitable value for the circuit is applied across the terminals of the main capacitor. In a slightly different version, two grids are provided so that the structure can be used both as a diode and as a transistor. In both cases, the capacitance value of the main capacitor varies depending on the control voltage, i.e. Co = f(Vi). This means that, similar to classical transistors, the impedance of the circuit varies depending on the control voltage. In this structure, which exhibits behaviour similar to FET transistors, the output voltage is taken across the two outer plates of the capacitor with a design similar to a classical transistor circuit. In the production stage, the dielectric will be formed by coating very thin special plastic or other suitable materials with an appropriate metal of suitable thickness for the design and winding it in roll form. Likewise, dielectric layers may also be formed as very thin oxide or other non-conductive chemical compounds on the surfaces of the metallic 24 plates. That is, use will be made of conventional capacitor technologies such as ceramic, tantalum and electrolytic capacitors. In addition, different methods may be developed depending on the field of application. These designs will find application areas as semiconductor-free transistors, diodes, voltage-controlled variable capacitors, and many other uses, some of which have been explained in this project.

A high-resistance field plate shield gate trench type field effect transistor device and manufacturing method, the present application belongs to power semiconductor device, it includes: the drain metal layer at the bottom, the N+ substrate layer above the drain metal layer, the N type epitaxial layer above the N+ substrate layer, the P doped body area and N+ doped source area on the device upper surface, the N+ doped source area is connected with the source metal on the device upper surface, the N type epitaxial layer is provided with the trench, the trench is filled with shield gate electrode and the gate electrode on the left and right sides or one side of shield gate electrode, the shield gate electrode is connected with the upper surface metal on the top of the device, the high-resistance field plate is arranged below the shield gate electrode, the high-resistance field plate extends to the N+ substrate layer below, the high-resistance field plate and the sidewall of the trench have thin oxide layer isolation, beneficial effect lies in, utilize high-resistance field plate, reduce the electric field intensity in the deep trench, realize the uniform electric field intensity distribution, increase breakdown voltage.

The invention discloses an MEMS microphone, a preparation method and an electro-acoustic conversion device, the MEMS microphone comprises a substrate and a capacitor assembly supported on the substrate, the substrate is provided with a through cavity in a penetrating manner in a preset axis direction, the through cavity comprises a first cavity and a second cavity which are coaxially arranged, the inner diameter of the second cavity is greater than that of the first cavity, and the first cavity and the second cavity are coaxially arranged. The second cavity is closer to the capacitor assembly than the first cavity. Compared with the prior art, according to the MEMS microphone and the preparation method of the MEMS microphone provided by the invention, the MEMS microphone realizes enhancement or suppression of specific frequency sound waves and optimizes frequency response characteristics by adjusting the size proportion of the first cavity and the second cavity. According to the preparation method of the MEMS microphone, oxidation layer deposition and polishing are carried out by dividing the CMP technological process into two or more steps. In this way, the thickness of the oxide layer deposited each time can be reduced, the thin oxide layer can be more easily and evenly removed in the CMP process, and interlayer stripping cannot be caused.

The invention belongs to the technical field of surface defect detection, and particularly relates to a forging part surface defect detection device which comprises a base and a PLC control host, and further comprises a material clamping and transferring mechanism fixedly arranged on the base and used for fixing an annular forging part to be detected; the pretreatment mechanism is fixedly connected to one side of the upper end of the base and used for treating impurities and dirt on the surface of the forging part before the forging part is detected; the active heating mechanism is fixedly connected to the rear side of the upper end of the base and located over the material clamping and transferring mechanism. And a thermal imaging detection mechanism. The device adapts to a high-temperature working condition by means of non-contact detection, is not influenced by material magnetism and conductivity, can penetrate through a thin oxide layer, quickly cover a complex curved surface and accurately identify defects such as microcracks and pits, greatly improves the detection accuracy and efficiency, and reduces the labor intensity of workers at the same time.

Some embodiments of the present disclosure provide a method of forming a memory device, including forming a photoresist on a dielectric structure, forming a trench in the dielectric structure through the photoresist to expose a gate electrode embedded in the dielectric structure, removing the photoresist by an ashing gas, and removing the gate electrode through the photoresist. Wherein the ashing gas has an oxidizing ability to oxidize the surface of the silicon wafer into a thinner oxide layer. The method further includes forming a first spacer nitride as a liner of the trench and covering the gate electrode, and forming a metal layer filling the trench. The oxidizing ability of the ashing gas may reduce the likelihood that the gate electrode forms an oxide, and thus contact resistance between the gate structure and the contact may be reduced, thereby improving performance of the memory device.

The invention relates to the technical field of silver-coated copper powder, in particular to high-thermal-conductivity silver-coated copper powder particles and a preparation method thereof. Comprising the steps of pretreatment, plating solution preparation, copper powder plating, nanowire growth, surface modification, proportioning and mixing and the like, macroscopic gaps are reduced through grading, the contact probability is increased, point contact among particles is changed into surface contact and body contact by adding nanowire microstructures on the surface of a silver layer, the contact area and mechanical interlocking are improved, and the contact efficiency is improved. In addition, the heat transfer efficiency from a polymer matrix to the surface of the filler is improved through chemical bonding by means of surface modification, and interface phonon scattering is reduced.

The present application relates to the technical field of automobile wheel manufacturing technology, and particularly relates to a lightweight hot stamping wheel composite forming manufacturing method, comprising the following steps: S1, sequentially performing surface pretreatment on steel material, and forming a matching passivation protective layer; S2, feeding into a hot stamping die for processing to obtain a spoke and a rim blank with uniform structure; S3, performing composite quenching heat treatment to form a uniform martensite structure in the blank matrix; S4, performing surface cleaning on the quenched spoke and rim blank to remove the thin oxide layer generated in the heat treatment process; S5, annularly welding the spoke and the rim to form a wheel semi-finished product; S6, performing accurate secondary induction heating on the weld and the surrounding annealing area; S7, performing gradient accurate water cooling treatment to re-form a uniform and strengthened martensite structure in the weld and the surrounding area; and S8, obtaining a finished lightweight hot stamping wheel after quality inspection. The present application solves the technical problems that the weld strength cannot be accurately reinforced and the overall performance of the wheel is uneven.

The invention provides a manufacturing method of an NORD type flash memory and an NORD type flash memory device. The method comprises the following steps: providing a semiconductor substrate and forming a floating gate structure with a top sharp corner and a side wall; depositing and back-etching a first dielectric layer on the surface of the floating gate to form a dielectric side wall; cleaning and removing the medium side wall at the sharp corner to expose the sharp corner; depositing a second dielectric layer to form a tunneling oxide layer, so that the thickness at the top sharp corner is smaller than the thickness at the side wall; and finally depositing a conductive material to form a word line. According to the invention, the gradual change type tunneling oxide layer is constructed, the thin oxide layer at the sharp corner is used for improving the erasing efficiency, and the thick oxide layer at the side wall is used for inhibiting the leakage current from the substrate to the word line, so that the contradiction between the erasing efficiency and the device reliability in the NORD type flash memory is effectively solved.