1263results about "Logic circuit coupling/interface arrangements" patented technology

The utility model relates to a phase interpolator circuit, a clock recovery circuit and a chip, and the phase interpolator circuit mainly comprises a first clock filter which is used for filtering a high-frequency harmonic wave of a first clock signal to generate a first filtering signal; the second clock filter is used for filtering the high-frequency harmonic wave of the second clock signal to generate a second filtering signal; the phase mixer is coupled to the first clock filter and the second clock filter and is used for generating a phase mixed signal according to the first filtering signal and the second filtering signal; and the alternating current coupling output circuit is used for receiving the phase mixed signal and generating an interpolation clock signal according to the phase mixed signal. The phase interpolator circuit can support phase interpolation operation in a wide frequency range, the output linearity performance is optimized, the sensitivity of INL and DNL to power supply amplitude changes is weakened, the duty ratio of the output interpolation clock signal can be optimized, and the interpolation clock signal can support a high-speed interface half-rate transmission mode.

A semiconductor die includes a first pin configured to output a first on-die termination (ODT) control signal to a second semiconductor die, the second semiconductor die comprising a plurality of second ODT circuits each having an ODT that is responsive to the first ODT control signal; and a second pin configured to receive a second ODT control signal output from the second semiconductor die, the semiconductor die comprising a plurality of first ODT circuits each having an ODT that is responsive to the second ODT control signal.

The embodiment of the invention is applied to the field of circuit control, and provides a level setting method and electronic equipment. Under the condition that the electronic equipment determines that the keyboard is in the closed state, the level states of all the output pins in the keyboard are configured to be the first level, so that potential difference between the input pins and the output pins is avoided. And under the condition that the keyboard is in the open state, the electronic equipment configures the levels of all output pins corresponding to keys in the keyboard as a second level or a third level. Under the condition that the level of the output pin is the second level or the third level, when the keyboard receives the click operation of the user on the key, interruption can be normally generated, so that the electronic equipment can determine the key clicked by the user based on the interruption. In the application, generation of abnormal oxides can be slowed down by reducing the duration of the potential difference, the probability of keyboard aging is reduced, the service life of the electronic equipment is prolonged, and the use experience of a user is improved.

The invention relates to the technical field of optocouplers, in particular to a planar SSR optocoupler. Through a light emitting diode arranged on an input loop and a bidirectional photosensitive silicon controlled rectifier and a bidirectional thyristor arranged on an output loop, the bidirectional photosensitive silicon controlled rectifier can be driven by light emitted by the light emitting diode to open a gate pole of the bidirectional thyristor, and the thyristors T1 and T2 are driven to control a load LOAD, so that the product can complete the function of a relay; the number of electronic components in the circuit is smaller, the probability that the whole circuit breaks down is greatly reduced, various electronic components can be protected by means of the shading body, the influence of external environment factors on the various electronic components is reduced, and therefore the probability that the electronic components in the circuit break down can be further reduced, and the service life of the circuit is prolonged. The fault probability of the whole circuit is reduced; the problem that the circuit damage probability is increased due to the fact that an existing relay circuit needs to be composed of a plurality of electronic components is solved.

The invention relates to a level control circuit and electric equipment. The level control circuit comprises a level shift circuit, an enable signal processing circuit and a level determination circuit. The level shift circuit is used for receiving a first control signal corresponding to the first voltage domain, converting the first control signal into a second control signal corresponding to the second voltage domain, and outputting the second control signal. The enable signal processing circuit is connected with a first positive power supply end of the first voltage domain and a second positive power supply end of the second voltage domain, and outputs an enable signal on the basis of a second power supply voltage provided by the second positive power supply end under the condition that the first power supply voltage is not connected to the first positive power supply end. And the level determining circuit is connected with the enable signal processing circuit and the output end of the level shifting circuit, and is used for controlling the level of the output end of the level shifting circuit to be in a preset state according to the received enable signal. The level shift circuit is clear in output state and high in output reliability under the condition that the second positive power supply end provides the second power supply voltage.

The invention discloses a radio frequency closed-loop decoupling device and method, and the device comprises a radio frequency sampling module which collects a radio frequency signal of a resonant cavity and converts the radio frequency signal into an intermediate frequency signal; the preprocessing module is used for converting the intermediate frequency signal into an I-path signal and a Q-path signal; the extended state observation module is used for obtaining an I component estimated value, a Q component estimated value and a corresponding generalized disturbance estimator according to the I-path signal and the Q-path signal; the decoupling control module is used for carrying out proportional control according to the I component estimation value and the Q component estimation value, and taking the generalized disturbance estimation quantity as decoupling compensation quantity for superposition to obtain a baseband signal so as to suppress channel coupling and external disturbance; and the radio frequency driving module is used for converting the baseband signal into a driving signal so as to control the amplitude and the phase of the radio frequency output of the power source. According to the invention, dynamic decoupling of the I signal channel and the Q signal channel is realized, and the stability and the control precision of the output amplitude and the phase of the power source are improved.

The utility model provides a level-to-pulse activation circuit and a charger, the circuit comprises a time delay circuit, a driving circuit, a switch control circuit and an output circuit, the time delay circuit comprises a first resistor, a second resistor, a first field effect transistor and a first capacitor, and the driving circuit comprises a seventh resistor and a triode. According to the level-to-pulse activation circuit, when a charger is connected, the triode is turned on, at the moment, current sequentially passes through the fourth resistor and the triode to be grounded, the second field-effect tube is turned on, high level is output at the voltage output end, after the first capacitor is charged for a period of time, the first field-effect tube is turned on and grounded, and the triode and the second field-effect tube are sequentially turned off. Therefore, the voltage output end outputs low level, one pulse period is completed, the rising edge of the pulse signal is fast, and the voltage and the pulse width are appropriate. When the battery is powered on, the battery takes power from the charging anode, and when the battery is not charged, the charging anode has no voltage because the first field effect transistor and the triode are turned off, so that power consumption is avoided.

The invention discloses a control circuit of a serial port transceiver circuit and a clock synchronization method, and belongs to the technical field of data communication. The circuit comprises a clock synchronization circuit and a register value generation circuit, wherein the output end of the register value generation circuit is connected with the first input end of a first selector in a transceiver circuit; the clock synchronization circuit outputs a reference clock rising edge according to the received slow reference clock; the register value generation circuit counts a main clock based on the rising edge of the reference clock and outputs a self-adaptive baud rate count value; the first selector selects the self-adaptive baud rate count value and a configuration signal of the register block and outputs a selection signal; and the transceiving module drives data transceiving with the register group according to the clock corresponding to the selection signal so as to adjust the main clock. According to the circuit, the influence of the deviation between the preset value and the actual value on the communication precision can be reduced under the condition that the main clock of the equipment is unstable.

In some embodiments, bias circuits are provided that can generate resilient output supplies without consuming excessive power. In addition, other resilient and efficient bias circuits may be provided that can be used for biasing level shift and other high supply circuit blocks such as LDOs with thin gate transistors over a relatively wide high supply voltage operational range.

The invention discloses a transformer type differential series resonant cavity, a differential series resonant oscillator, a chip and equipment, the resonant cavity comprises a two-port transformer and a variable capacitance module, the two-port transformer comprises an inductor LP1, an inductor LP2, an inductor LS1 and an inductor LS2 which are mutually coupled, and the variable capacitance module comprises a variable capacitor CP and a variable capacitor CS; one end of the inductor LP1 is connected with the first port, and the other end is connected with the variable capacitor CP; one end of the inductor LP2 is connected with the second port, and the other end is connected with the variable capacitor CP; one end of the inductor LS1 and one end of the inductor LS2 are connected with the third port and the fourth port respectively, and the other end of the inductor LS1 and the other end of the inductor LS2 are connected with each other; two ends of the variable capacitor CS are respectively connected with the third port and the fourth port; a plurality of pole frequencies of the voltage gain function AV are set to be equal such that AV at the zero phase increases. According to the invention, the problem that a series resonant oscillator cannot realize pure differential output in the current pure CMOS process is solved.

Provided are a pin-multiplexed trimming circuit, a trimming chip, and a trimming method for a chip. The pin-multiplexed trimming circuit comprises a first superposition circuit and a trimming chip; the trimming chip comprises a separation circuit, a control circuit, and an in-chip trimming circuit; the first superposition circuit is electrically connected to the separation circuit by means of a power input pin of the trimming chip; the first superposition circuit receives a power supply signal and superposes the power supply signal with a first data signal sent by a controller to obtain a first fused signal; the separation circuit separates the first fused signal to obtain a second data signal and the power supply signal; the power supply signal supplies power to the in-chip trimming circuit, the separation circuit, and the control circuit; the control circuit decodes the second data signal to obtain a third data signal and sends the third data signal to the in-chip trimming circuit.

According to the current compensation-based level shift circuit provided by the invention, one path of low-voltage pulse signal is accessed through the first level input end and the second level output end respectively, so that the two paths of low-voltage pulse signals are converted into two paths of high-voltage pulse signals; the signals are output to the current compensation circuit and the common-mode noise elimination circuit through the first level output end and the second level output end, and the output of the current compensation circuit and the output of the common-mode noise elimination circuit jointly influence the signal states of the R end and the S end in the latch. And the latch is used for restoring the high-voltage pulse signal into a floating square wave signal with the same phase as the input signal. The level shift circuit not only can resist high common-mode noise, but also has a good inhibition effect on differential-mode noise, and the stability and reliability of the level shift circuit are effectively improved.

The utility model relates to the technical field of digital-to-analog conversion, and discloses a Delta-Sigma ADC data reading device, which comprises a power supply circuit, a photoelectric conversion circuit and a minimum system unit, one end of the power supply circuit is connected with an external direct-current power supply, and the other end of the power supply circuit is connected with the power supply end of the photoelectric conversion circuit and the power supply end of the minimum system unit; one end of the photoelectric conversion circuit is connected with an optical signal input end, and the other end of the photoelectric conversion circuit is connected with a signal end of the minimum system unit. According to the utility model, the minimum system unit with the built-in digital filter is adopted to replace a bit stream data conversion chip in the traditional scheme, so that the cost is reduced, and the area of a printed circuit board is saved; and the data interaction process between the active filter chip and the MCU is omitted, and the information transmission efficiency is improved.

The invention discloses a switching-in circuit with a self-adaptive voltage class and a double check logic. The switching-in circuit comprises a high-precision voltage division module, a double-redundancy sampling framework and a double sampling judgment logic executed by an MCU (Microprogrammed Control Unit), the high-precision voltage dividing module adopts a resistance network matched with a temperature coefficient, and can accurately divide input voltage in a wide temperature range; the double-set redundancy sampling architecture performs parallel sampling on the same path of input signals through two sets of completely independent signal conditioning loops, ADCs, digital isolation chips and isolation power supplies to form a physically isolated redundancy channel; the dual sampling discrimination logic executed by the MCU verifies a dual-channel sampling result based on a logic voting mechanism, and finally outputs a reliable input state or an abnormal alarm; according to the invention, through adaptive voltage design and redundancy check, high reliability is ensured, meanwhile, the requirements for spare parts of equipment of different voltage grades are remarkably reduced, and the inventory management cost is effectively reduced.

The invention provides a level conversion circuit and electronic equipment, and belongs to the technical field of electronic circuits. The circuit comprises a pull-up module, a conversion module, a first control unit and a second control unit, the first end and the second end of the pull-up module are respectively used for inputting a first working voltage, the third end of the pull-up module is connected with the first end of the first control unit, and the fourth end of the pull-up module is connected with the first end of the second control unit; the first end and the second end of the conversion module are respectively used for inputting a second working voltage, the third end of the conversion module is used for inputting a first control signal, and the fourth end of the conversion module is used for inputting a second control signal; the second end of the first control unit is connected with the fifth end of the conversion module, and the third end of the first control unit is used for inputting a second control signal; the second end of the second control unit is connected with the sixth end of the conversion module, and the third end of the second control unit is used for inputting a first control signal. According to the invention, the reliability of level conversion can be improved.

A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of a conversion circuit includes a first inverter, a first-stage amplifier and a second-stage amplifier. An input terminal of the first inverter is shorted to an output terminal of the first inverter. The second-stage amplifier of the replica feedback loop circuit is a replica of a half of a differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage that is used to bias the differential amplifier of the CML to CMOS converter, such that a common mode (CM) voltage outputted by the differential amplifier is same as a switching threshold voltage of a second inverter of the CML to CMOS converter.

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

The invention provides a multi-protocol configurable interface circuit. The multi-protocol configurable interface circuit comprises a plurality of channel modules, a plurality of counter modules, an input / output module and a configuration register, the channel module comprises a state machine, a shift register and a cache module. The configuration register obtains configuration information through the system bus, and the configuration information comprises which protocol is selected. The counter module generates a shift signal required by a shift register in the channel module according to the configuration information; the input and output module selects the corresponding pins according to the configuration information and determines the function of each pin; and the channel module determines the mode of each channel and the required state of the state machine according to the configuration information to complete data transmission of the selected protocol. According to the invention, a hardware design which focuses on realizing clock and data transmission by matching a state machine state transition and a shift register with a cache module is adopted, so that software intervention and CPU occupation are reduced, and the overall efficiency is improved; hardware resources are reduced, and hardware flexibility is improved.

The embodiment of the invention provides a level shifter. An input circuit receives an input signal operated in a first level. A second level supplied by a second level line coupled to a pull-up circuit is higher than the first level, and a first coupling point of the pull-up circuit and the input circuit is used as an output end of the level shifter. An acceleration circuit is coupled to the first coupling point to accelerate the low-to-high transition of the output terminal. An acceleration controller coupled to the acceleration circuit includes a plurality of pulse generating transistors having first sides connected in series. Particularly, in the pulse generation transistors connected in series at the first side, different transistors respectively receive driving signals with time differences so as to be instantly conducted, so that the acceleration circuit is enabled in a pulse mode, and the driving signals received by the different transistors are from the input signals.

The invention relates to the technical field of isolation driving chips, and provides a common-mode rejection circuit, an isolation transmission circuit and a motor driving circuit. The common-mode rejection circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a first clamping circuit and a second clamping circuit. The first clamping circuit is coupled between the power supply voltage of the receiver and a common node of the first end of the first transistor and the first end of the second transistor, and is used for clamping the voltage on the first common node; the second clamping circuit is coupled between a common node of the first end of the third transistor and the first end of the fourth transistor and the reference ground of the receiver, and is used for clamping the voltage on a second common node. According to the invention, the common-mode transient interference can be effectively suppressed in the isolation transmission circuit, and the system reliability is improved.

Circuitry is provided that includes a matching circuit, a first mixer coupled to the matching circuit and configured to receive a signal with an oscillation frequency, a second mixer coupled to the matching circuit, a first transmission line path coupled between the matching circuit and an input of the first mixer, and one or more capacitors coupled to the input of the first mixer and configured to reject signals at a harmonic frequency of the oscillation frequency. The wireless circuitry can further include a second transmission line path coupled between the matching circuit and an input of the second mixer. The transmission line path can include a first transmission line for conveying signals between the matching circuit and the first mixer, a second transmission line for conveying signals between the matching circuit and the first mixer, and a floating transmission line interposed between the first and second transmission lines.

The invention discloses a high-speed level shifter applied to a BUCK converter. The high-speed level shifter comprises a level shifting part, a control logic part and an output part, after the level shift part inputs a signal, a low-delay rising edge and a high-delay falling edge of a conversion level A, and a high-delay rising edge and a low-delay falling edge of a conversion level B are output; the input of the control logic part adopts CLK in a BUCK converter to generate a short pulse, a high-voltage domain where SW and BST are located is isolated from a low-voltage domain, when the short pulse is at a high level, an output control signal is high, and when the short pulse is at a low level, the output signal is low; the input of the output part is the output of the level shift part and the control logic, and when the control signal is high, a low-delay rising edge is selected to be output; and when the control signal is low, selecting to output a low-delay falling edge. The level shift result is output through double ports, and low delay of conversion between the rising edge and the falling edge is achieved.

The invention belongs to the field of integrated circuits, and discloses a level shifter with high dv / dt noise resistance and a self-adaptive power tube, which comprises a level shifting main body circuit and an auxiliary pull-up circuit. According to the invention, the auxiliary pull-up circuit which can be adaptively started according to the conduction time of the power tube is added, so that high dv / dt noise resistance can be realized in an application scene that different power tubes are adopted outside a chip.

The present invention discloses an adaptive combination equalization circuit and its adaptive circuit, method, device and equipment, which belong to the field of signal processing and are used for adaptively adjusting the parameters to be adjusted of the combination equalization circuit, solving the problems of poor signal compensation effect and large volume of the adaptive circuit. The first control voltage in the first equalization circuit is first determined by a first integration circuit, the second control voltage of the combination equalization circuit is determined by a second integration circuit, and then the difference between the second control voltage of the combination equalization circuit and the first control voltage is used as the third control voltage of the second equalization circuit, so that the control voltages corresponding to the front-stage equalization circuit and the rear-stage equalization circuit are complementary, and the compensation work for the signal to be compensated can be completed more accurately, and the adaptive control of the combination equalization circuit is realized by using a set of adaptive circuits, which reduces the volume of the adaptive circuit.

The utility model relates to an asynchronous finite state machine, a switching converter and a switching circuit. The asynchronous finite-state machine has a state coupled by transitions implemented by the respective free flip-flops. Each flip-flop supplies bits of an arrival state of a corresponding transition and receives bits of an initial state of the transition at its data input and receives a first signal dedicated to the flip-flop at its control input. The circuitry supplies, for each transition, a second signal requesting the transition. Another circuit generates a pulse of the first signal dedicated to the transitioned flip-flop and a pulse of the first signal dedicated to each flip-flop that supplies bits to the transitioned flip-flop based on the second signal each time a transition is requested and without a pulse of the first signal.

A signal transmission device includes: a signal transmission circuit that transmits a pulse signal from a primary circuit system to a secondary circuit system in an isolated manner; a power supply circuit that generates an output voltage from an input voltage in an isolated manner; first and second abnormality detection circuits that detect an abnormality in the primary circuit system and secondary circuit system; a signal transmission path that transmits an output of the second abnormality detection circuit from the secondary circuit system to the primary circuit system in an isolated manner; and a self-diagnosis circuit that performs self-diagnosis on each of the first and second abnormality detection circuits and the signal transmission path. The first abnormality detection circuit includes, as a diagnostic target, a power supply abnormality detector that detects an abnormality in the power supply circuit. The self-diagnosis circuit first diagnoses on the power supply abnormality detector.

An output circuit of the low-voltage differential signal equipment comprises a first current source and a differential push-pull output circuit, the first current source is connected between a power supply end and the differential push-pull output circuit, and the differential push-pull output circuit is connected with a differential output end of the driver. A first output voltage and a second output voltage are generated according to the first input signal and the second input signal; a turn-off circuit is connected with a differential output end of a driver and is used for turning off a first current source by using a short-circuited power supply on the differential output end when the driver is in a leakage protection state; a first end of a substrate clamping circuit of the low-voltage differential signal driver is connected with a power supply end, a second end of the substrate clamping circuit provides a substrate potential for an MOS tube in a first current source, and when the driver is in a leakage protection state, the substrate clamping circuit is in a turn-off state in the direction from the second end to the first end, so that when the low-voltage differential signal driver is in a power-off state, the substrate clamping circuit is in a turn-off state. And effective leakage protection can be carried out on the low-voltage differential signal driver.

A high-noise-immunity and low-delay level shift circuit for a GaN half-bridge drive chip, relating to the technical field of power management in integrated circuits. By additionally providing a path from a floating power rail VDDH to the ground, the level shift circuit simulates the noise effect caused by a sudden change in the voltage of the floating power rail in the level shift circuit. The level shift circuit has a good noise immunity capability and a simple structure.

Mixer circuitry can include a first pair of transistors coupled to a first tail node and configured to receive a local oscillator signal, a second pair of transistors coupled to a second tail node and configured to receive the local oscillator signal, a first digital-to-analog converter, a second DAC coupled between the first DAC and of the first pair of transistors, and a third DAC coupled between the first DAC and the second pair of transistors. During a first phase, control circuitry can sweep the first DAC to trim a first and / or other odd order local oscillator feedthrough. During a second phase, the control circuitry can sweep the second DAC to trim a second and / or other even order local oscillator feedthrough. During a third phase, the control circuitry can sweep the second and third DACs to reject signals associated with a second harmonic conversion gain of the mixer circuitry.

The invention relates to a coupled inductor current-limiting type hybrid direct-current circuit breaker topology and a working method. The coupled inductor current-limiting type hybrid direct-current circuit breaker comprises a current-carrying part and a breaking part, the current-carrying part is formed by connecting an ultra-fast mechanical switch UFD and a load change-over switch LCS in series, the breaking part comprises a bridge circuit, a first branch circuit, a second branch circuit, a third branch circuit, a fourth branch circuit, a fifth branch circuit and a sixth branch circuit, the fourth branch circuit is formed by connecting a thyristor, a coupling inductor and a primary side inductor in series to form a current-limiting branch circuit, and the fifth branch circuit is formed by connecting a secondary side inductor and a secondary side inductor. The sixth branch is formed by connecting a secondary side inductor of a coupling inductor with a thyristor in series and then connecting the secondary side inductor with a capacitor in parallel; the current limiting of the fault current is realized through the fourth branch, the fault breaking of the primary side inductor of the coupling inductor of the fourth branch is completed through the coupling effect of the secondary side inductor of the coupling inductor of the sixth branch, the peak value of the fault current is obviously reduced, and the breaking time is obviously shortened; the circuit breaker can quickly respond to faults of three working modes of current limiting breaking, reclosing and small current breaking; and the breaking part of the circuit breaker adopts the thyristors instead of the IGBTs, so that the cost of the circuit breaker is reduced.