985results about "Logic circuit coupling/interface arrangements" patented technology

The invention discloses a radio frequency closed-loop decoupling device and method, and the device comprises a radio frequency sampling module which collects a radio frequency signal of a resonant cavity and converts the radio frequency signal into an intermediate frequency signal; the preprocessing module is used for converting the intermediate frequency signal into an I-path signal and a Q-path signal; the extended state observation module is used for obtaining an I component estimated value, a Q component estimated value and a corresponding generalized disturbance estimator according to the I-path signal and the Q-path signal; the decoupling control module is used for carrying out proportional control according to the I component estimation value and the Q component estimation value, and taking the generalized disturbance estimation quantity as decoupling compensation quantity for superposition to obtain a baseband signal so as to suppress channel coupling and external disturbance; and the radio frequency driving module is used for converting the baseband signal into a driving signal so as to control the amplitude and the phase of the radio frequency output of the power source. According to the invention, dynamic decoupling of the I signal channel and the Q signal channel is realized, and the stability and the control precision of the output amplitude and the phase of the power source are improved.

The utility model provides a level-to-pulse activation circuit and a charger, the circuit comprises a time delay circuit, a driving circuit, a switch control circuit and an output circuit, the time delay circuit comprises a first resistor, a second resistor, a first field effect transistor and a first capacitor, and the driving circuit comprises a seventh resistor and a triode. According to the level-to-pulse activation circuit, when a charger is connected, the triode is turned on, at the moment, current sequentially passes through the fourth resistor and the triode to be grounded, the second field-effect tube is turned on, high level is output at the voltage output end, after the first capacitor is charged for a period of time, the first field-effect tube is turned on and grounded, and the triode and the second field-effect tube are sequentially turned off. Therefore, the voltage output end outputs low level, one pulse period is completed, the rising edge of the pulse signal is fast, and the voltage and the pulse width are appropriate. When the battery is powered on, the battery takes power from the charging anode, and when the battery is not charged, the charging anode has no voltage because the first field effect transistor and the triode are turned off, so that power consumption is avoided.

In some embodiments, bias circuits are provided that can generate resilient output supplies without consuming excessive power. In addition, other resilient and efficient bias circuits may be provided that can be used for biasing level shift and other high supply circuit blocks such as LDOs with thin gate transistors over a relatively wide high supply voltage operational range.

The invention discloses a transformer type differential series resonant cavity, a differential series resonant oscillator, a chip and equipment, the resonant cavity comprises a two-port transformer and a variable capacitance module, the two-port transformer comprises an inductor LP1, an inductor LP2, an inductor LS1 and an inductor LS2 which are mutually coupled, and the variable capacitance module comprises a variable capacitor CP and a variable capacitor CS; one end of the inductor LP1 is connected with the first port, and the other end is connected with the variable capacitor CP; one end of the inductor LP2 is connected with the second port, and the other end is connected with the variable capacitor CP; one end of the inductor LS1 and one end of the inductor LS2 are connected with the third port and the fourth port respectively, and the other end of the inductor LS1 and the other end of the inductor LS2 are connected with each other; two ends of the variable capacitor CS are respectively connected with the third port and the fourth port; a plurality of pole frequencies of the voltage gain function AV are set to be equal such that AV at the zero phase increases. According to the invention, the problem that a series resonant oscillator cannot realize pure differential output in the current pure CMOS process is solved.

The utility model relates to the technical field of digital-to-analog conversion, and discloses a Delta-Sigma ADC data reading device, which comprises a power supply circuit, a photoelectric conversion circuit and a minimum system unit, one end of the power supply circuit is connected with an external direct-current power supply, and the other end of the power supply circuit is connected with the power supply end of the photoelectric conversion circuit and the power supply end of the minimum system unit; one end of the photoelectric conversion circuit is connected with an optical signal input end, and the other end of the photoelectric conversion circuit is connected with a signal end of the minimum system unit. According to the utility model, the minimum system unit with the built-in digital filter is adopted to replace a bit stream data conversion chip in the traditional scheme, so that the cost is reduced, and the area of a printed circuit board is saved; and the data interaction process between the active filter chip and the MCU is omitted, and the information transmission efficiency is improved.

The invention discloses a switching-in circuit with a self-adaptive voltage class and a double check logic. The switching-in circuit comprises a high-precision voltage division module, a double-redundancy sampling framework and a double sampling judgment logic executed by an MCU (Microprogrammed Control Unit), the high-precision voltage dividing module adopts a resistance network matched with a temperature coefficient, and can accurately divide input voltage in a wide temperature range; the double-set redundancy sampling architecture performs parallel sampling on the same path of input signals through two sets of completely independent signal conditioning loops, ADCs, digital isolation chips and isolation power supplies to form a physically isolated redundancy channel; the dual sampling discrimination logic executed by the MCU verifies a dual-channel sampling result based on a logic voting mechanism, and finally outputs a reliable input state or an abnormal alarm; according to the invention, through adaptive voltage design and redundancy check, high reliability is ensured, meanwhile, the requirements for spare parts of equipment of different voltage grades are remarkably reduced, and the inventory management cost is effectively reduced.

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

The invention provides a multi-protocol configurable interface circuit. The multi-protocol configurable interface circuit comprises a plurality of channel modules, a plurality of counter modules, an input / output module and a configuration register, the channel module comprises a state machine, a shift register and a cache module. The configuration register obtains configuration information through the system bus, and the configuration information comprises which protocol is selected. The counter module generates a shift signal required by a shift register in the channel module according to the configuration information; the input and output module selects the corresponding pins according to the configuration information and determines the function of each pin; and the channel module determines the mode of each channel and the required state of the state machine according to the configuration information to complete data transmission of the selected protocol. According to the invention, a hardware design which focuses on realizing clock and data transmission by matching a state machine state transition and a shift register with a cache module is adopted, so that software intervention and CPU occupation are reduced, and the overall efficiency is improved; hardware resources are reduced, and hardware flexibility is improved.

The embodiment of the invention provides a level shifter. An input circuit receives an input signal operated in a first level. A second level supplied by a second level line coupled to a pull-up circuit is higher than the first level, and a first coupling point of the pull-up circuit and the input circuit is used as an output end of the level shifter. An acceleration circuit is coupled to the first coupling point to accelerate the low-to-high transition of the output terminal. An acceleration controller coupled to the acceleration circuit includes a plurality of pulse generating transistors having first sides connected in series. Particularly, in the pulse generation transistors connected in series at the first side, different transistors respectively receive driving signals with time differences so as to be instantly conducted, so that the acceleration circuit is enabled in a pulse mode, and the driving signals received by the different transistors are from the input signals.

The invention relates to the technical field of isolation driving chips, and provides a common-mode rejection circuit, an isolation transmission circuit and a motor driving circuit. The common-mode rejection circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a first clamping circuit and a second clamping circuit. The first clamping circuit is coupled between the power supply voltage of the receiver and a common node of the first end of the first transistor and the first end of the second transistor, and is used for clamping the voltage on the first common node; the second clamping circuit is coupled between a common node of the first end of the third transistor and the first end of the fourth transistor and the reference ground of the receiver, and is used for clamping the voltage on a second common node. According to the invention, the common-mode transient interference can be effectively suppressed in the isolation transmission circuit, and the system reliability is improved.

Circuitry is provided that includes a matching circuit, a first mixer coupled to the matching circuit and configured to receive a signal with an oscillation frequency, a second mixer coupled to the matching circuit, a first transmission line path coupled between the matching circuit and an input of the first mixer, and one or more capacitors coupled to the input of the first mixer and configured to reject signals at a harmonic frequency of the oscillation frequency. The wireless circuitry can further include a second transmission line path coupled between the matching circuit and an input of the second mixer. The transmission line path can include a first transmission line for conveying signals between the matching circuit and the first mixer, a second transmission line for conveying signals between the matching circuit and the first mixer, and a floating transmission line interposed between the first and second transmission lines.

The invention discloses a high-speed level shifter applied to a BUCK converter. The high-speed level shifter comprises a level shifting part, a control logic part and an output part, after the level shift part inputs a signal, a low-delay rising edge and a high-delay falling edge of a conversion level A, and a high-delay rising edge and a low-delay falling edge of a conversion level B are output; the input of the control logic part adopts CLK in a BUCK converter to generate a short pulse, a high-voltage domain where SW and BST are located is isolated from a low-voltage domain, when the short pulse is at a high level, an output control signal is high, and when the short pulse is at a low level, the output signal is low; the input of the output part is the output of the level shift part and the control logic, and when the control signal is high, a low-delay rising edge is selected to be output; and when the control signal is low, selecting to output a low-delay falling edge. The level shift result is output through double ports, and low delay of conversion between the rising edge and the falling edge is achieved.

The invention belongs to the field of integrated circuits, and discloses a level shifter with high dv / dt noise resistance and a self-adaptive power tube, which comprises a level shifting main body circuit and an auxiliary pull-up circuit. According to the invention, the auxiliary pull-up circuit which can be adaptively started according to the conduction time of the power tube is added, so that high dv / dt noise resistance can be realized in an application scene that different power tubes are adopted outside a chip.

A signal transmission device includes: a signal transmission circuit that transmits a pulse signal from a primary circuit system to a secondary circuit system in an isolated manner; a power supply circuit that generates an output voltage from an input voltage in an isolated manner; first and second abnormality detection circuits that detect an abnormality in the primary circuit system and secondary circuit system; a signal transmission path that transmits an output of the second abnormality detection circuit from the secondary circuit system to the primary circuit system in an isolated manner; and a self-diagnosis circuit that performs self-diagnosis on each of the first and second abnormality detection circuits and the signal transmission path. The first abnormality detection circuit includes, as a diagnostic target, a power supply abnormality detector that detects an abnormality in the power supply circuit. The self-diagnosis circuit first diagnoses on the power supply abnormality detector.

A high-noise-immunity and low-delay level shift circuit for a GaN half-bridge drive chip, relating to the technical field of power management in integrated circuits. By additionally providing a path from a floating power rail VDDH to the ground, the level shift circuit simulates the noise effect caused by a sudden change in the voltage of the floating power rail in the level shift circuit. The level shift circuit has a good noise immunity capability and a simple structure.

Mixer circuitry can include a first pair of transistors coupled to a first tail node and configured to receive a local oscillator signal, a second pair of transistors coupled to a second tail node and configured to receive the local oscillator signal, a first digital-to-analog converter, a second DAC coupled between the first DAC and of the first pair of transistors, and a third DAC coupled between the first DAC and the second pair of transistors. During a first phase, control circuitry can sweep the first DAC to trim a first and / or other odd order local oscillator feedthrough. During a second phase, the control circuitry can sweep the second DAC to trim a second and / or other even order local oscillator feedthrough. During a third phase, the control circuitry can sweep the second and third DACs to reject signals associated with a second harmonic conversion gain of the mixer circuitry.

The invention relates to a coupled inductor current-limiting type hybrid direct-current circuit breaker topology and a working method. The coupled inductor current-limiting type hybrid direct-current circuit breaker comprises a current-carrying part and a breaking part, the current-carrying part is formed by connecting an ultra-fast mechanical switch UFD and a load change-over switch LCS in series, the breaking part comprises a bridge circuit, a first branch circuit, a second branch circuit, a third branch circuit, a fourth branch circuit, a fifth branch circuit and a sixth branch circuit, the fourth branch circuit is formed by connecting a thyristor, a coupling inductor and a primary side inductor in series to form a current-limiting branch circuit, and the fifth branch circuit is formed by connecting a secondary side inductor and a secondary side inductor. The sixth branch is formed by connecting a secondary side inductor of a coupling inductor with a thyristor in series and then connecting the secondary side inductor with a capacitor in parallel; the current limiting of the fault current is realized through the fourth branch, the fault breaking of the primary side inductor of the coupling inductor of the fourth branch is completed through the coupling effect of the secondary side inductor of the coupling inductor of the sixth branch, the peak value of the fault current is obviously reduced, and the breaking time is obviously shortened; the circuit breaker can quickly respond to faults of three working modes of current limiting breaking, reclosing and small current breaking; and the breaking part of the circuit breaker adopts the thyristors instead of the IGBTs, so that the cost of the circuit breaker is reduced.

Mixer circuitry can include a first pair of transistors coupled to a first tail node and configured to receive a local oscillator signal, a second pair of transistors coupled to a second tail node and configured to receive the local oscillator signal, a first digital-to-analog converter, a second DAC coupled between the first DAC and of the first pair of transistors, and a third DAC coupled between the first DAC and the second pair of transistors. During a first phase, control circuitry can sweep the first DAC to trim a first and / or other odd order local oscillator feedthrough. During a second phase, the control circuitry can sweep the second DAC to trim a second and / or other even order local oscillator feedthrough. During a third phase, the control circuitry can sweep the second and third DACs to reject signals associated with a second harmonic conversion gain of the mixer circuitry.

To provide a semiconductor device that can realize data writing to a target device with an effective configuration.SOLUTION: A semiconductor device (1) comprises a communication unit (2) configured to perform data communication using a clock (SCL) and communication data (SDA), a register (21), an input terminal (Ti), and an output terminal (To). When an enable input signal that is input to the input terminal is at a first level, the communication unit is capable of rewriting data in the register based on a command via the data communication, and an enable output signal that is output from the output terminal is a signal that can take the first level or a second level.SELECTED DRAWING: Figure 2

A power supply circuit generates from the input voltage of a primary circuit system the output voltage of a secondary circuit system by driving a switching output stage. The power supply circuit includes: a pulse feedback signal generation circuit that generates a pulse feedback signal corresponding to the output voltage; an analog control signal generation circuit that generates an analog control signal corresponding to the pulse feedback signal; and a switching driving control circuit that drives the switching output stage according to the result of comparison of the analog control signal with a slope signal. The analog control signal generation circuit raises the maximum value (an internal supply voltage) of the analog control signal with a predetermined gradient during the start-up or renewed start-up of the output voltage.

The utility model provides a digital switching value input circuit and electronic equipment. The input circuit comprises an optocoupler receiving unit and a connector, the optocoupler receiving unit comprises a photodiode; the connector is at least provided with a first interface, a second interface, a third interface and a fourth interface; the first interface is connected with a power supply, the second interface is grounded, and the third interface and the fourth interface are connected to two ends of the photodiode; the input circuit has a first input state connected with a dry node and a second input state connected with a wet node; in a first input state, the second interface is in short circuit with the fourth interface, and the first interface and the third interface are connected to two ends of the dry node; in the second input state, the third interface is connected to the output signal end of the wet node, the second interface is connected with the grounding end of the wet node, and the fourth interface is in short circuit with the second interface; the digital switching value input circuit can be compatible with dry nodes and wet nodes, and the flexibility of the digital switching value input circuit can be improved.

The utility model relates to a communication circuit and a scooter. According to the communication circuit, a first withstand voltage boosting module comprises a withstand voltage controllable switching device and is used for being switched on or switched off under the control of a bias signal; data transmission between the first data port and the second data port is opened or closed, and the withstand voltage values of the first data port and the second data port are increased to a first voltage threshold value; the second withstand voltage boosting module comprises a withstand voltage unidirectional switching device and is used for sending a clock signal from the master device to the slave device and increasing the withstand voltage values of the first clock port and the second clock port to a second voltage threshold; the first response speed increasing module comprises a first impedance network and is used for increasing the level change rate of the first data port and the first clock port; and the second response speed increasing module comprises a second impedance network and is used for increasing the level change rate of the second data port and the second clock port. According to the I2C communication port provided by the embodiment of the invention, 100V voltage resistance can be realized, and the response speed is at a microsecond level.

The utility model relates to the technical field of die bonder detection circuits, in particular to a sensor detection circuit for a die bonder, which comprises a master control module, a sensor interface module, a display control module, a signal processing module and a power supply module. The power supply module is used for supplying power to the main control module, the sensor interface module and the display control module; the sensor interface module and the display control module are respectively connected with the main control module; the main control module comprises a main processor and an auxiliary processor, the signal processing module comprises an AD7730 chip, the input end of the AD7730 chip is connected with a low-pass filter, and the main processor is connected with the auxiliary processor through an SPI interface. According to the utility model, a plurality of sensor interface circuits are arranged and can be used for high-speed and high-precision data detection of the die bonder, so that high-speed, low-noise and rapid system response of the die bonder is met, the connection complexity of the die bonder sensor is reduced, and the requirements of high precision and high sampling rate of the die bonder sensor are met.

The utility model discloses a high voltage resistant isolation serial interface circuit, comprising a modulation signal sending circuit, a modulation signal receiving circuit, a CPU1 and a CPU2, the input end of the modulation signal sending circuit is connected to the input end of the CPU1, the output end of the modulation signal sending circuit is connected to the input end of the modulation signal receiving circuit, and the output end of the modulation signal receiving circuit is connected to the input end of the CPU2. The output end of the modulation signal receiving circuit is connected to the signal input end of the modulation signal receiving circuit, and the output end of the modulation signal receiving circuit is connected to the signal end of the CPU 2. According to the high-voltage-resistant isolation serial interface circuit provided by the utility model, the circuit is relatively simple, and the highest withstand voltage can meet 15KV high-voltage isolation application; the maximum withstand voltage value can be adjusted by adopting various schemes, the high-voltage isolation application in a larger range can be met, and the practical flexibility is high.

This application relates to an interface circuit and an electronic device. The interface circuit includes an input interface unit, an output interface unit, an input connection terminal, an output connection terminal, a device connection terminal, and a common selection terminal. The input and output connection terminals are used to connect to a controller, the device connection terminal is used to connect to an external device, and the common selection terminal is used to receive a preset voltage signal. The input interface unit is connected to the input connection terminal, the device connection terminal, and the common selection terminal, and is used to receive the signal to be transmitted received at the device connection terminal and the preset voltage received at the common selection terminal, and outputs a signal corresponding to the signal to be transmitted through the input connection terminal. The output interface unit is connected to the output connection terminal, the device connection terminal, and the common selection terminal, and is used to receive the output signal received at the output connection terminal and the preset voltage received at the common selection terminal, and outputs a signal corresponding to the output signal through the device connection terminal. This interface circuit integrates the functions of a DI circuit and a DO circuit, exhibiting high integration.

An embodiment of the present application discloses a control signal generating circuit, an automatic gain control loop, and a transimpedance amplifier (TIA), wherein the control signal generating circuit includes: a voltage-current conversion circuit, a current comparison circuit, and a voltage generating circuit; wherein the voltage-current conversion circuit is used to convert an input voltage signal to be controlled into its corresponding current signal to be controlled, and to convert an input reference voltage signal into its corresponding reference current signal; the current comparison circuit is used to compare the generated current signal to be controlled with the reference current signal to generate a difference current signal; and the voltage generating circuit is used to generate a voltage control signal based on the difference current signal.

The invention discloses a high-isolation and high-selectivity filtering power divider with an input end broadband non-reflection characteristic. Comprising an input port, two output ports, a double-L-shaped non-reflection absorption structure, two microstrip connecting lines, two parallel coupling lines, two L-shaped step resonators, two non-reflection absorption isolation resistors, a quarter-wavelength parallel coupling connecting line and two U-shaped transmission lines. The input port is a first port; the two output ports comprise a port II and a port III; the double-L-shaped non-reflection absorption structure comprises a first non-reflection absorption resistor, a second non-reflection absorption resistor, a first L-shaped non-reflection absorption connecting line and a second L-shaped non-reflection absorption connecting line. According to the invention, the broadband reflection-free absorption characteristic of the input end and the broadband high isolation between the output ports are realized at the same time, a plurality of transmission zeros are introduced through the L-shaped step resonators, and the frequency selectivity and out-of-band rejection are improved.

A programmable impedance element includes a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches. The two-port elements are arranged in a chain with a structured switch group such that a certain range of impedances can be obtained from each unit by dynamically changing the connections between the impedance elements in the unit. A common unit is constructed by connecting the nominally identical two-port impedance elements in such a way that the number of possible combinations of impedance elements is reduced to a subset of all possible combinations using the minimum possible number of connections. This structure allows the use of industry-standard devices to generate matching impedances. The connections between the impedance elements are switches, which can be "field programmable", i.e., they can be set on the chip after manufacturing and configured during the operation of the circuit or can be mask programmable.

An output circuit 1 comprises: three P-type transistors (P1, P2, P3) connected in series between a first power supply and an output terminal (OUT); three N-type transistors (N1, N2, N3) connected in series between the output terminal (OUT) and a fourth power supply; and an N-type transistor (N4) and a P-type transistor (P4) connected in series between a second power supply and a third power supply. The output circuit (1) outputs an output signal (OUT) that changes in accordance with an input signal (IN).