1260 results about "Level shifting" patented technology

The invention discloses a high-voltage level conversion circuit with a symmetric pulse current structure, which belongs to the technical field of integrated circuits and comprises a level conversion module, a symmetric pulse current auxiliary module and a latch output module. According to the level conversion module, the defect that in the prior art, when the voltage of a power supply jumps rapidly, a circuit may be triggered by mistake is overcome, and the immunity of the circuit is improved. According to the symmetrical pulse current auxiliary module, the defect that transmission delays at the rising edge and the falling edge of an input signal are asymmetric in the prior art is overcome, so that the symmetrical pulse current auxiliary module keeps high transmission delay symmetry while ensuring a high transmission speed; and the problem of possible distortion of digital signal input and output in a high-speed circuit is effectively suppressed.

The embodiment of the invention provides a signal envelope detection circuit and a chip. The circuit comprises N cascaded first limiting amplifiers, a plurality of first rectifiers and at least one first level conversion circuit, the power supply voltage of the first-stage first limiting amplifier is a first voltage; each of the first limiting amplifier and the first rectifier comprises a tail current tube, and the tail current tubes are transistors for providing bias current; the first level conversion circuit is used for reducing the voltage output by the first limiting amplifier and then outputting the reduced voltage to a post-stage first limiting amplifier and a corresponding first rectifier, so that the voltage between a collector electrode and an emitter electrode of a corresponding tail current tube is smaller than a breakdown voltage; and a first level conversion circuit is connected between at least the first-stage first limiting amplifier and the second-stage first limiting amplifier so as to at least reduce the voltage output by the first-stage first limiting amplifier. According to the embodiment of the invention, the dynamic range of the signal envelope detection circuit can be expanded.

The invention relates to the technical field of high-voltage integrated circuits, and provides an under-voltage protection high-voltage integrated circuit. Comprising an RC filter circuit, a Schmidt circuit, a filter, a level conversion circuit, a temperature protection circuit, an undervoltage protection circuit, an overcurrent protection circuit, a fault logic control circuit, a fault output circuit, a bootstrap circuit, a dead zone interlocking circuit, a time delay circuit, a pulse circuit, a first high-voltage DMOS, a second high-voltage DMOS, an RS trigger, an output circuit and an AND gate. The under-voltage protection circuit comprises a voltage stabilizing circuit, a power supply voltage detection circuit, a comparator and a first NMOS tube. The input end of the voltage stabilizing circuit serves as the input end of the under-voltage protection circuit to be connected with power supply voltage, and the output end of the voltage stabilizing circuit is connected with the input end of the power supply voltage detection circuit and the negative input end of the comparator. According to the invention, the working stability and reliability of the HIVC in an application occasion with relatively large temperature change are improved, and the market competitiveness of a product is improved.

The invention belongs to the technical field of integrated circuits, and particularly relates to a speed regulation driving and anomaly detection circuit of a cooling fan. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed, so that the speed of the fan is regulated; and the sampling detection module is connected with the logic control module and the VIN port of the LDO, samples the current of the fan through a sampling resistor, converts the current into a voltage V0, compares the voltage V0 with a reference voltage Vref, and outputs a voltage signal to the level shift circuit. The speed-adjustable fan driving circuit is integrated, detection of various abnormal states of the fan is achieved, and the speed-adjustable fan driving circuit has the outstanding advantages of being simple in PCB layout and low in cost.

The invention belongs to the technical field of integrated circuits, and particularly relates to an integrated speed regulation fan and an abnormal state detection circuit. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed, so that the speed of the fan is regulated; and the sampling detection module is connected with the logic control module and the fan, samples the current of the fan through a sampling resistor, converts the current into a voltage V0, compares the voltage V0 with a reference voltage Vref, and outputs a voltage signal to a level shift circuit. The speed-adjustable fan driving circuit is integrated, detection of various abnormal states of the fan is achieved, and the speed-adjustable fan driving circuit has the outstanding advantages of being simple in PCB layout and low in cost.

The invention discloses a high-speed level conversion circuit, and belongs to the technical field of integrated circuit design, the circuit mainly comprises an input signal processing module, a voltage boosting module, a differential signal generation module, a signal amplification module and an output module, the input signal processing module converts a low-voltage input signal into a complementary logic signal pair; the voltage boosting module raises the voltage amplitude of the complementary logic signal by using a charge pump principle; the lifted signal drives a thick gate transistor in the differential signal generation module to generate a differential signal; the signal amplification module adopts a cross coupling structure to quickly amplify the differential signal; and finally, the output module outputs a high-voltage domain signal in an inverted manner. By introducing voltage bootstrap before gate driving, the overdrive voltage of a core switch tube is remarkably increased, so that the problem of low conversion speed of a traditional level conversion circuit is effectively solved on the premise of not increasing the device size and static power consumption, and high-speed and high-efficiency level conversion is realized.

The invention provides a clock input buffer and electronic equipment. The clock input buffer comprises a multi-protocol input circuit, a level conversion circuit, a step-down circuit and a clock buffer circuit. The multi-protocol input circuit is adjusted to different working modes through a control signal transmitted by the control unit so as to be compatible with various input protocols, the multi-protocol input circuit processes an input signal based on a target working mode, and the level conversion circuit performs level shifting on an output signal of the multi-protocol input circuit so as to realize multi-protocol conversion. The voltage reduction circuit is used for converting the output signal into a low-voltage domain signal so as to meet the working voltage requirement of the clock buffer circuit, and meanwhile, the voltage reduction circuit is used for reducing the power supply voltage so as to provide low-voltage power supply voltage for the clock buffer circuit; therefore, the clock buffer circuit can buffer high-speed signals in different input protocols and voltage ranges by using a low-voltage domain device, and the application scenarios of the clock input buffer are greatly expanded.

A disclosed charge pump includes first and second stages and, optionally, additional stage(s). The first stage receives a voltage input (Vin) at a first voltage (V1), CLK1 (GND, V1), and CLK1B (V1, GND), and outputs a first stage voltage output (Vout1) at a second voltage (V2) double V1. A second stage receives Vout1, CLK2 (V1, V2), and CLK2B (V2, V1, and outputs a second stage voltage output (Vout2) at a third voltage (V3) essentially triple V1, and so on. A clock driver supplies CLK1-CLK1B to the first stage and to a clock generator. The clock generator includes: a voltage level shifter, which receives CLK1 and CLK1B and outputs multiple level-shifted voltage output pulses; and a driving circuit, which receives specific ones of the output voltage pulses and outputs CLK2 and CLK2B to the second stage and, if needed, additional voltage level-shifted clock signal-inverted clock signal pairs to any additional stages.

The invention discloses a high-precision high-power-supply-rejection-ratio band-gap reference circuit integrated with a digital trimming module. The high-precision high-power-supply-rejection-ratio band-gap reference circuit comprises a first-stage band-gap reference circuit, a second-stage band-gap reference circuit, a zero-temperature-coefficient current source circuit and the digital trimming module. The two-stage band-gap reference circuit is adopted, the power supply rejection ratio of output reference voltage is increased, zero-temperature-coefficient current is obtained through the current summing circuit, a digital trimming mode is adopted, an I2C module and a level conversion module are integrated, high-precision and repeatable trimming of the output reference voltage can be achieved, a traditional resistance trimming mode is improved, and the power supply rejection ratio of the output reference voltage is increased. And the precision of the output reference voltage is improved.

The invention discloses an automatic direction induction level conversion circuit, which comprises a first voltage domain circuit and a second voltage domain circuit which have the same structure, and can automatically input an input signal A of the first voltage domain circuit to a second level conversion module through a first voltage domain circuit driving input module. A driving signal is output to a second voltage domain circuit to drive an output module to control weak driving and control a monostable circuit to generate corresponding strong driving at the same time, and a second signal B in the same phase is output; or similarly, the input signal B of the second voltage domain circuit is automatically converted into a first signal A with the same phase. According to the level conversion circuit, the transmission direction of the switching signal can be automatically sensed without an additional signal, bidirectional level conversion is realized, and the system structure is simplified; meanwhile, strong driving output is started in a short time through the monostable circuit, the output driving capacity and transmission speed are improved, strong driving output on the other side is closed through a feedback signal, and mistaken starting of the bidirectional level conversion circuit is avoided.

A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.

The invention relates to the field of digital power supplies, and particularly provides a method for identifying CCM and DCM modes in a high-power digital power supply, which comprises the following steps: acquiring an inductive current sampling voltage signal and a reference voltage signal, and detecting the level conversion states of the two through a comparator module; if the comparison result accords with a preset error range, recording a DCM mode identifier and calculating an average sampling current value; adjusting an interrupt priority order to match a time sequence characteristic of the capture event, and generating a current state parameter of a mode switching boundary; calculating a correction factor of the average sampling current by combining the overflow times of the counter and rising edge fluctuation frequency data; a duty ratio parameter is updated based on the corrected current value, and a new PWM control signal is generated and output; when the duty ratio deviation exceeds a switching threshold value, dynamically adjusting an interrupt priority parameter and updating a reference value of a counter; and generating a real-time tracking data set of the inductive current zero point according to the final adjustment parameter.

The invention relates to a level control circuit and electric equipment. The level control circuit comprises a level shift circuit, an enable signal processing circuit and a level determination circuit. The level shift circuit is used for receiving a first control signal corresponding to the first voltage domain, converting the first control signal into a second control signal corresponding to the second voltage domain, and outputting the second control signal. The enable signal processing circuit is connected with a first positive power supply end of the first voltage domain and a second positive power supply end of the second voltage domain, and outputs an enable signal on the basis of a second power supply voltage provided by the second positive power supply end under the condition that the first power supply voltage is not connected to the first positive power supply end. And the level determining circuit is connected with the enable signal processing circuit and the output end of the level shifting circuit, and is used for controlling the level of the output end of the level shifting circuit to be in a preset state according to the received enable signal. The level shift circuit is clear in output state and high in output reliability under the condition that the second positive power supply end provides the second power supply voltage.

The invention discloses a driver chip based on a GaAs process, which comprises a level conversion unit, a first phase inverter unit, a second phase inverter unit, a third phase inverter unit, a fourth phase inverter unit, a fifth phase inverter unit, a signal input port, a first output port and a second output port, after passing through the level conversion unit, the first inverter unit and the second inverter unit in sequence, the signal is divided into two paths, and one path passes through the third inverter unit and is output from the first output port; and the other path passes through the fourth inverter unit and the fifth inverter unit and is output from the second output port. According to the circuit system, an input + 5V / 0V or + 3.3 V / 0V level signal can be converted into two 0V / -5V level signals which are opposite to each other to be output, and the problems that in an existing circuit system, level conversion is not universal, and precision and efficiency are low are solved.

A level conversion assembly (50), an overcurrent protection method and a display device, the level conversion assembly (50) comprising a level conversion module (51), the level conversion module (51) comprising a control unit (511), a current detection unit (512), a level conversion unit (513) and an overcurrent protection unit (514). When a control unit (511) is at a first falling edge of a digital clock signal (CPV), a first analog clock signal corresponding to the first falling edge in a plurality of analog clock signals (CLK1-CLK8) is determined based on the corresponding relation of the current display mode, and a current detection unit (512) is controlled to detect the current of the first analog clock signal. Since the moment of the falling edge of the digital clock signal (CPV) is located in the last row of the high level period or the low level period in the corresponding analog clock signal, the current detection unit (512) can send an overcurrent signal to the overcurrent protection unit (514) when the current of the first analog clock signal is not located in the current threshold range. The effect of improving the accuracy of over-current phenomenon detection is achieved.

A method of encoding and decoding downlink instructions based on mud flow rate includes an encoding method and a decoding method. The encoding method and the decoding method are configured to transmit and receive instructions by controlling the mud flow rate during drilling process. The method of encoding and decoding downlink instructions based on mud flow rate does not require a fixed threshold of voltage as a judgement standard for “0” and “1” symbols, but uses voltage change rate as a standard for judging the level transition, avoiding decoding failure caused by the inability of voltage sampling values to reach the fixed threshold after well depth is increased.

Provided is a traction power supply system for rail transit, specifically a power unit for rail transit, and a control method. Distinguished from the architecture of a conventional traction power supply system for rail transit, a modularization-based power unit main circuit and a control method therefor are provided. The power unit main circuit comprises a high-voltage switch module, high-voltage modules, high-frequency transformers, low-voltage modules and an intermediate direct-current module. On the basis of a modular design concept, electrical isolation between high and low voltages and level conversion are implemented, thereby effectively reducing the difficulty in insulation design of a system and also improving the degree of redundancy and maintainability of the system. Furthermore, with regard to the phenomenon of voltage unbalance of multiple cascaded modules caused by differences in device parameters, a voltage equalization start logic and a control method are provided to effectively resolve the phenomenon of voltage unbalance between the cascaded modules, thereby reducing the impact of starting currents and improving the reliability of the system.

In one embodiment, a method includes: receiving, in a level shifter, an input signal from a first voltage domain that operates according to a first supply voltage; level shifting the input signal to at least one level-shifted signal having a second voltage greater than the first supply voltage; based on the at least one level-shifted signal, generating a first pulse signal and a second pulse signal; latching the first pulse signal through a latch circuit to form an output signal; and outputting the output signal to a second voltage domain, the second voltage domain to operate according to a second supply voltage greater than the first supply voltage.

The invention relates to a power management system which comprises an awakening module, a super capacitor, an MCU module and a power supply module. The input end of the awakening module is connected to the positive electrode end of the super capacitor, and the output end of the awakening module is connected to the enabling input end of the MCU module and the enabling input end of the power supply module; the wake-up output end of the MCU module is connected to the wake-up input end of the power supply module; the super capacitor is connected in parallel with the load end; the super capacitor is used for discharging when a load is connected to the load end, and the voltage of the positive end is converted from a high level to a low level; the wake-up module is used for outputting an enable signal to wake up the MCU module and activate the power supply module when the voltage of the positive electrode end of the super capacitor is detected to be low level; and the MCU module is used for outputting a wake-up signal to the power supply module after waking up and waking up the activated power supply module. The energy consumption of the power management system can be reduced.

Embodiments of the disclosure provide a level shift circuit, a chip and a display device. By setting first and second voltage clamping modules, and by adjusting first clamping voltage by controlling bias voltage input to the first voltage clamping module and adjusting second clamping voltage by controlling bias voltage and second bias voltage input to the second voltage clamping module, respective operating and output voltages of the first and the second voltage clamping modules and the shift module are within small range. Therefore, even the level shift circuit is designed by using devices with breakdown voltage lower than the difference between the first and second power supply voltages, the devices in the level shift circuit may be avoid being breakdown. Accordingly, some process platforms that cannot produce high-breakdown voltage devices may produce chips including the level shift circuit in the embodiment, and the restrictions on the process platform are reduced.

The invention discloses a level shift circuit with a mixed structure, relates to the technical field of integrated circuits, and aims to solve the problems of long time delay and high power consumption of a level shift circuit in the prior art when the level shift circuit is converted between a low voltage domain and a high voltage domain. The circuit at least comprises a first current mirror level shift sub-circuit and a second current mirror level shift sub-circuit which are connected with a cross-coupling level shift sub-circuit; an output signal of the first current mirror level shift sub-circuit is used for reducing the pull-up strength of a first pull-up network in the cross-coupling level shift sub-circuit; the output signal of the second current mirror level shift sub-circuit is used for reducing the pull-up strength of a second pull-up network in the cross coupling level shift sub-circuit; the cross coupling level shift sub-circuit is used for cutting off quiescent current paths in the first current mirror level shift sub-circuit and the second current mirror level shift sub-circuit and realizing conversion between a low voltage domain and a high voltage domain of the circuit; therefore, level conversion between a low-voltage domain and a high-voltage domain is realized by picosecond-level delay and nanoampere-level static power consumption.

The invention provides a level shift circuit and electronic equipment, and relates to but is not limited to the technical field of integrated circuits, and the circuit comprises a level shift module which is used for outputting a first level signal according to a first input signal, and outputting a second level signal according to a second input signal; the duty ratio adjusting module is connected with the level shifting module and used for adjusting the duty ratio of the first level signal and outputting a third level signal, and adjusting the duty ratio of the second level signal and outputting a fourth level signal; and the waveform shaping module is connected with the duty ratio adjusting module, and is used for inverting the third level signal and outputting a fifth level signal, and inverting the fourth level signal and outputting a sixth level signal. The waveform duty ratios of the first level signal and the second level signal output by the level shifting module are adjusted through the duty ratio adjusting module, so that the output fifth level signal and sixth level signal can keep good duty ratios under different PVT and different working frequencies.

A multiplying digital-to-analog converter (MDAC) has two input terminals and two output terminals and includes: an analog-to-digital converter (ADC), a selection circuit, first and second sampling and amplifying circuits, an operational amplifier, and an amplification and level shifting circuit. The ADC generates a selection signal according to first and second input signals. The selection circuit selects two reference voltages from a plurality of preset voltages according to the selection signal. The first sampling and amplifying circuit samples and amplifies the first input signal according to one of the two reference voltages. The second sampling and amplifying circuit samples and amplifies the second input signal according to the other reference voltage. The operational amplifier has first and second output nodes. The amplification and level shifting circuit amplifies the first and second input signals and level shifts voltages at the first and second output nodes.

The invention relates to an anti-radiation level conversion circuit. The circuit comprises a level conversion circuit based on a DICE structure and an anti-radiation reinforcement circuit. The level conversion circuit based on the DICE structure is used for realizing level conversion by adopting redundant control nodes; comprising an input module and a DICE module, and the DICE module comprises four branches formed by connecting one PMOS transistor and one NMOS transistor in series; drain electrodes of the PMOS transistor and the NMOS transistor in each branch are connected to serve as a control node; the input module is used for controlling an MOS switch to transmit a differential input signal to the DICE module through a transmission tube; and the anti-radiation reinforcing circuit is used for performing feedback regulation on the control nodes of the second branch and the third branch through the cross coupling structure. The circuit can complete level switching from ultra-low voltage to high voltage, the radiation resistance of the level converter is improved, the level converter can resist severe environments, and meanwhile power consumption and delay are reduced.

The invention discloses a wide-level-range high-speed level conversion circuit, and relates to the technical field of electronic circuits. A level conversion module in the level conversion circuit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube; a first NMOS tube and a second NMOS tube in the input module are NMOS devices with the voltage grade lower than the device grade corresponding to the main power supply voltage of the chip; the bias voltage generation module is connected with a power supply voltage and is used for generating a bias voltage; the bias voltage is dynamically adjusted along with the change of the power supply voltage; and a signal access selection unit in the input module is respectively connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and is used for controlling the grid electrode to be connected with a bias voltage or a ground potential. The pull-down capability of the level conversion circuit can be adaptively adjusted along with the change of the pull-up capability caused by the change of the main power supply voltage, so that the level conversion circuit can realize high-speed level conversion in a wide level range.

The invention discloses a self-locking noise suppression level shift circuit with ultra-low delay, relates to the technical field of intelligent power driving, and aims to solve the problem that delay is increased when noise is filtered out through an RC filter circuit in the prior art. Comprising a high-voltage level shifting circuit, a common-mode noise elimination circuit, a differential-mode noise elimination circuit and an RS latch which are electrically connected, the common-mode noise elimination circuit is used for transmitting 1 / 2VDD voltage to the input end of the RS latch when common-mode noise exists, relatively low threshold voltage of the RS latch is designed, the 1 / 2VDD voltage is made to be high level for the RS latch, and therefore the 1 / 2VDD voltage is made to be low level for the RS latch. The state of the RS latch is kept unchanged, the differential mode noise elimination circuit is used for starting the differential mode noise elimination circuit through resistor voltage division when differential mode noise exists, and the input end of the RS latch is kept at a high level. The self-locking noise suppression level shift circuit provided by the invention is used for eliminating common-mode noise and differential-mode noise of dV / dt noise and has lower delay.

The invention discloses an LDO (Low Dropout Regulator) circuit based on a level conversion and pre-adjustment module. The LDO circuit comprises a reference source, an error amplifier, a pre-adjustment module, a level conversion module, a power switch tube P1, a power circuit tube N1 and resistance feedback networks R1 and R2. The pre-adjustment module carries out voltage reduction processing on an input high-voltage power supply, and the level conversion module generates bias voltage according to an enable signal and the high-voltage power supply, controls a power switch and a switch in the operational amplifier, and ensures that the circuit is resistant to high voltage and extremely low in drain. The error amplifier adjusts the grid voltage of the power circuit according to the feedback and reference voltage difference value, and controls the current to stably output the voltage. And the resistance feedback network realizes closed-loop regulation of the output voltage. Under the condition that the LDO is enabled to be closed, the power tube can be ensured to be completely closed no matter the LDO is under the working voltage of 3V or 5V, so that the electric leakage condition of the LDO is greatly improved, and the LDO has the characteristic of low electric leakage.

The invention provides an asynchronous motor speed sensor fault diagnosis method, which comprises the following steps of: acquiring a rotating speed signal analog quantity, analyzing the acquired rotating speed signal analog quantity, and realizing asynchronous motor speed sensor fault diagnosis according to different rotating speed signal analog quantity analysis results. Analysis of the analog quantity of the collected rotating speed signals comprises a logic sequence of level conversion, the duty ratio of signals of the same channel, the period deviation ratio of signals of different channels, edge signal time prediction of different channels and high and low level voltage values. According to the method, the fault of the speed sensor can be effectively diagnosed by comprehensively analyzing the analog quantity of the collected rotating speed signal from different angles, and the method is simple to implement, small in calculated amount and high in practicability.

The present invention provides a voltage detection method, device, system, electronic device, readable storage medium and chip. The voltage detection method is used in a voltage detection system. The voltage detection system includes a voltage sampling unit, a single-chip circuit, a temperature sensor circuit and a level conversion circuit. The voltage detection method includes: obtaining multi-channel isolated power supply voltage; determining at least one voltage parameter through a voltage sampling unit and an analog-to-digital converter; determining at least one time parameter according to a real-time clock; determining at least one temperature parameter according to a temperature sensor; determining a voltage detection result according to a time parameter, a temperature parameter and a voltage parameter; and transmitting the voltage detection result to a host computer through a level conversion circuit. Through the scheme of the present invention, the accuracy of multi-channel isolated power supply voltage detection is improved.

The invention relates to the technical field of Internet of Things, in particular to a circuit for simultaneously converting UART (Universal Asynchronous Receiver / Transmitter) to multi-path different level communication, which comprises a double-USB input module, a power supply processing module, a USB-UART core conversion module and a multi-path level conversion module, the double-USB input module comprises an MINI-USB interface J6 and a USB-B interface J8, VBUS pins of the two interfaces are connected in parallel through a Schottky diode and then output to the power supply processing module, and data differential pair pins are connected in parallel and then connected to the USB-UART core conversion module; and the power supply processing module comprises an LDO (Low Dropout Regulator) voltage stabilizing chip and a filter capacitor, and is used for converting 5V voltage output by the double-USB input module into 3.3 V stable voltage. The circuit design that the UART is connected with various different levels for communication is adopted, the tool integration technology is achieved, the design that the two USB ports are connected in parallel is adopted, the compatibility of the USB data line can be effectively improved, the demands of customers are met, and the technical difficulty that one UART bus is connected with multiple USB ports is broken through.