854 results about "Level shifting" patented technology

The invention belongs to the technical field of integrated circuits, and particularly relates to a speed regulation driving and anomaly detection circuit of a cooling fan. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed, so that the speed of the fan is regulated; and the sampling detection module is connected with the logic control module and the VIN port of the LDO, samples the current of the fan through a sampling resistor, converts the current into a voltage V0, compares the voltage V0 with a reference voltage Vref, and outputs a voltage signal to the level shift circuit. The speed-adjustable fan driving circuit is integrated, detection of various abnormal states of the fan is achieved, and the speed-adjustable fan driving circuit has the outstanding advantages of being simple in PCB layout and low in cost.

The invention belongs to the technical field of integrated circuits, and particularly relates to an integrated speed regulation fan and an abnormal state detection circuit. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed, so that the speed of the fan is regulated; and the sampling detection module is connected with the logic control module and the fan, samples the current of the fan through a sampling resistor, converts the current into a voltage V0, compares the voltage V0 with a reference voltage Vref, and outputs a voltage signal to a level shift circuit. The speed-adjustable fan driving circuit is integrated, detection of various abnormal states of the fan is achieved, and the speed-adjustable fan driving circuit has the outstanding advantages of being simple in PCB layout and low in cost.

The invention discloses a high-speed level conversion circuit, and belongs to the technical field of integrated circuit design, the circuit mainly comprises an input signal processing module, a voltage boosting module, a differential signal generation module, a signal amplification module and an output module, the input signal processing module converts a low-voltage input signal into a complementary logic signal pair; the voltage boosting module raises the voltage amplitude of the complementary logic signal by using a charge pump principle; the lifted signal drives a thick gate transistor in the differential signal generation module to generate a differential signal; the signal amplification module adopts a cross coupling structure to quickly amplify the differential signal; and finally, the output module outputs a high-voltage domain signal in an inverted manner. By introducing voltage bootstrap before gate driving, the overdrive voltage of a core switch tube is remarkably increased, so that the problem of low conversion speed of a traditional level conversion circuit is effectively solved on the premise of not increasing the device size and static power consumption, and high-speed and high-efficiency level conversion is realized.

The invention provides a clock input buffer and electronic equipment. The clock input buffer comprises a multi-protocol input circuit, a level conversion circuit, a step-down circuit and a clock buffer circuit. The multi-protocol input circuit is adjusted to different working modes through a control signal transmitted by the control unit so as to be compatible with various input protocols, the multi-protocol input circuit processes an input signal based on a target working mode, and the level conversion circuit performs level shifting on an output signal of the multi-protocol input circuit so as to realize multi-protocol conversion. The voltage reduction circuit is used for converting the output signal into a low-voltage domain signal so as to meet the working voltage requirement of the clock buffer circuit, and meanwhile, the voltage reduction circuit is used for reducing the power supply voltage so as to provide low-voltage power supply voltage for the clock buffer circuit; therefore, the clock buffer circuit can buffer high-speed signals in different input protocols and voltage ranges by using a low-voltage domain device, and the application scenarios of the clock input buffer are greatly expanded.

A disclosed charge pump includes first and second stages and, optionally, additional stage(s). The first stage receives a voltage input (Vin) at a first voltage (V1), CLK1 (GND, V1), and CLK1B (V1, GND), and outputs a first stage voltage output (Vout1) at a second voltage (V2) double V1. A second stage receives Vout1, CLK2 (V1, V2), and CLK2B (V2, V1, and outputs a second stage voltage output (Vout2) at a third voltage (V3) essentially triple V1, and so on. A clock driver supplies CLK1-CLK1B to the first stage and to a clock generator. The clock generator includes: a voltage level shifter, which receives CLK1 and CLK1B and outputs multiple level-shifted voltage output pulses; and a driving circuit, which receives specific ones of the output voltage pulses and outputs CLK2 and CLK2B to the second stage and, if needed, additional voltage level-shifted clock signal-inverted clock signal pairs to any additional stages.

The invention discloses an automatic direction induction level conversion circuit, which comprises a first voltage domain circuit and a second voltage domain circuit which have the same structure, and can automatically input an input signal A of the first voltage domain circuit to a second level conversion module through a first voltage domain circuit driving input module. A driving signal is output to a second voltage domain circuit to drive an output module to control weak driving and control a monostable circuit to generate corresponding strong driving at the same time, and a second signal B in the same phase is output; or similarly, the input signal B of the second voltage domain circuit is automatically converted into a first signal A with the same phase. According to the level conversion circuit, the transmission direction of the switching signal can be automatically sensed without an additional signal, bidirectional level conversion is realized, and the system structure is simplified; meanwhile, strong driving output is started in a short time through the monostable circuit, the output driving capacity and transmission speed are improved, strong driving output on the other side is closed through a feedback signal, and mistaken starting of the bidirectional level conversion circuit is avoided.

The invention relates to the field of digital power supplies, and particularly provides a method for identifying CCM and DCM modes in a high-power digital power supply, which comprises the following steps: acquiring an inductive current sampling voltage signal and a reference voltage signal, and detecting the level conversion states of the two through a comparator module; if the comparison result accords with a preset error range, recording a DCM mode identifier and calculating an average sampling current value; adjusting an interrupt priority order to match a time sequence characteristic of the capture event, and generating a current state parameter of a mode switching boundary; calculating a correction factor of the average sampling current by combining the overflow times of the counter and rising edge fluctuation frequency data; a duty ratio parameter is updated based on the corrected current value, and a new PWM control signal is generated and output; when the duty ratio deviation exceeds a switching threshold value, dynamically adjusting an interrupt priority parameter and updating a reference value of a counter; and generating a real-time tracking data set of the inductive current zero point according to the final adjustment parameter.

A level conversion assembly (50), an overcurrent protection method and a display device, the level conversion assembly (50) comprising a level conversion module (51), the level conversion module (51) comprising a control unit (511), a current detection unit (512), a level conversion unit (513) and an overcurrent protection unit (514). When a control unit (511) is at a first falling edge of a digital clock signal (CPV), a first analog clock signal corresponding to the first falling edge in a plurality of analog clock signals (CLK1-CLK8) is determined based on the corresponding relation of the current display mode, and a current detection unit (512) is controlled to detect the current of the first analog clock signal. Since the moment of the falling edge of the digital clock signal (CPV) is located in the last row of the high level period or the low level period in the corresponding analog clock signal, the current detection unit (512) can send an overcurrent signal to the overcurrent protection unit (514) when the current of the first analog clock signal is not located in the current threshold range. The effect of improving the accuracy of over-current phenomenon detection is achieved.

A method of encoding and decoding downlink instructions based on mud flow rate includes an encoding method and a decoding method. The encoding method and the decoding method are configured to transmit and receive instructions by controlling the mud flow rate during drilling process. The method of encoding and decoding downlink instructions based on mud flow rate does not require a fixed threshold of voltage as a judgement standard for “0” and “1” symbols, but uses voltage change rate as a standard for judging the level transition, avoiding decoding failure caused by the inability of voltage sampling values to reach the fixed threshold after well depth is increased.

Provided is a traction power supply system for rail transit, specifically a power unit for rail transit, and a control method. Distinguished from the architecture of a conventional traction power supply system for rail transit, a modularization-based power unit main circuit and a control method therefor are provided. The power unit main circuit comprises a high-voltage switch module, high-voltage modules, high-frequency transformers, low-voltage modules and an intermediate direct-current module. On the basis of a modular design concept, electrical isolation between high and low voltages and level conversion are implemented, thereby effectively reducing the difficulty in insulation design of a system and also improving the degree of redundancy and maintainability of the system. Furthermore, with regard to the phenomenon of voltage unbalance of multiple cascaded modules caused by differences in device parameters, a voltage equalization start logic and a control method are provided to effectively resolve the phenomenon of voltage unbalance between the cascaded modules, thereby reducing the impact of starting currents and improving the reliability of the system.

In one embodiment, a method includes: receiving, in a level shifter, an input signal from a first voltage domain that operates according to a first supply voltage; level shifting the input signal to at least one level-shifted signal having a second voltage greater than the first supply voltage; based on the at least one level-shifted signal, generating a first pulse signal and a second pulse signal; latching the first pulse signal through a latch circuit to form an output signal; and outputting the output signal to a second voltage domain, the second voltage domain to operate according to a second supply voltage greater than the first supply voltage.

The invention relates to a power management system which comprises an awakening module, a super capacitor, an MCU module and a power supply module. The input end of the awakening module is connected to the positive electrode end of the super capacitor, and the output end of the awakening module is connected to the enabling input end of the MCU module and the enabling input end of the power supply module; the wake-up output end of the MCU module is connected to the wake-up input end of the power supply module; the super capacitor is connected in parallel with the load end; the super capacitor is used for discharging when a load is connected to the load end, and the voltage of the positive end is converted from a high level to a low level; the wake-up module is used for outputting an enable signal to wake up the MCU module and activate the power supply module when the voltage of the positive electrode end of the super capacitor is detected to be low level; and the MCU module is used for outputting a wake-up signal to the power supply module after waking up and waking up the activated power supply module. The energy consumption of the power management system can be reduced.

A multiplying digital-to-analog converter (MDAC) has two input terminals and two output terminals and includes: an analog-to-digital converter (ADC), a selection circuit, first and second sampling and amplifying circuits, an operational amplifier, and an amplification and level shifting circuit. The ADC generates a selection signal according to first and second input signals. The selection circuit selects two reference voltages from a plurality of preset voltages according to the selection signal. The first sampling and amplifying circuit samples and amplifies the first input signal according to one of the two reference voltages. The second sampling and amplifying circuit samples and amplifies the second input signal according to the other reference voltage. The operational amplifier has first and second output nodes. The amplification and level shifting circuit amplifies the first and second input signals and level shifts voltages at the first and second output nodes.

The invention discloses a wide-level-range high-speed level conversion circuit, and relates to the technical field of electronic circuits. A level conversion module in the level conversion circuit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube; a first NMOS tube and a second NMOS tube in the input module are NMOS devices with the voltage grade lower than the device grade corresponding to the main power supply voltage of the chip; the bias voltage generation module is connected with a power supply voltage and is used for generating a bias voltage; the bias voltage is dynamically adjusted along with the change of the power supply voltage; and a signal access selection unit in the input module is respectively connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and is used for controlling the grid electrode to be connected with a bias voltage or a ground potential. The pull-down capability of the level conversion circuit can be adaptively adjusted along with the change of the pull-up capability caused by the change of the main power supply voltage, so that the level conversion circuit can realize high-speed level conversion in a wide level range.

The invention discloses an LDO (Low Dropout Regulator) circuit based on a level conversion and pre-adjustment module. The LDO circuit comprises a reference source, an error amplifier, a pre-adjustment module, a level conversion module, a power switch tube P1, a power circuit tube N1 and resistance feedback networks R1 and R2. The pre-adjustment module carries out voltage reduction processing on an input high-voltage power supply, and the level conversion module generates bias voltage according to an enable signal and the high-voltage power supply, controls a power switch and a switch in the operational amplifier, and ensures that the circuit is resistant to high voltage and extremely low in drain. The error amplifier adjusts the grid voltage of the power circuit according to the feedback and reference voltage difference value, and controls the current to stably output the voltage. And the resistance feedback network realizes closed-loop regulation of the output voltage. Under the condition that the LDO is enabled to be closed, the power tube can be ensured to be completely closed no matter the LDO is under the working voltage of 3V or 5V, so that the electric leakage condition of the LDO is greatly improved, and the LDO has the characteristic of low electric leakage.

The present invention provides a voltage detection method, device, system, electronic device, readable storage medium and chip. The voltage detection method is used in a voltage detection system. The voltage detection system includes a voltage sampling unit, a single-chip circuit, a temperature sensor circuit and a level conversion circuit. The voltage detection method includes: obtaining multi-channel isolated power supply voltage; determining at least one voltage parameter through a voltage sampling unit and an analog-to-digital converter; determining at least one time parameter according to a real-time clock; determining at least one temperature parameter according to a temperature sensor; determining a voltage detection result according to a time parameter, a temperature parameter and a voltage parameter; and transmitting the voltage detection result to a host computer through a level conversion circuit. Through the scheme of the present invention, the accuracy of multi-channel isolated power supply voltage detection is improved.

The invention relates to the technical field of Internet of Things, in particular to a circuit for simultaneously converting UART (Universal Asynchronous Receiver / Transmitter) to multi-path different level communication, which comprises a double-USB input module, a power supply processing module, a USB-UART core conversion module and a multi-path level conversion module, the double-USB input module comprises an MINI-USB interface J6 and a USB-B interface J8, VBUS pins of the two interfaces are connected in parallel through a Schottky diode and then output to the power supply processing module, and data differential pair pins are connected in parallel and then connected to the USB-UART core conversion module; and the power supply processing module comprises an LDO (Low Dropout Regulator) voltage stabilizing chip and a filter capacitor, and is used for converting 5V voltage output by the double-USB input module into 3.3 V stable voltage. The circuit design that the UART is connected with various different levels for communication is adopted, the tool integration technology is achieved, the design that the two USB ports are connected in parallel is adopted, the compatibility of the USB data line can be effectively improved, the demands of customers are met, and the technical difficulty that one UART bus is connected with multiple USB ports is broken through.

The present invention discloses a level conversion circuit and chip for converting an input signal in a first voltage domain into an output signal in a second voltage domain. The level conversion circuit includes: a switch unit including a first MOS transistor and a second MOS transistor, wherein the control end of the first MOS transistor and the control end of the second MOS transistor are both connected to a bias voltage; an input unit operating in the first voltage domain and connected to the second end of the first MOS transistor and the second end of the second MOS transistor; a conversion unit operating in the second voltage domain and connected to the first end of the first MOS transistor and the first end of the second MOS transistor; an output unit operating in the second voltage domain; and a clamping unit connected between the switch unit and a first low voltage. In a first state, the first high voltage is not powered off and the clamping unit is disconnected. In a second state, the first high voltage is powered off and the clamping unit is turned on to clamp the driving voltage to the second low voltage. The present invention reduces chip area and avoids power consumption caused by the DC current brought by the pull-down element.

A low-cost optical fiber IMU voltage acquisition circuit comprises an isolation voltage acquisition circuit and a non-isolation voltage acquisition circuit. In the isolation voltage acquisition circuit, a DC / DC isolation power supply module T1 generates an isolation power supply + 5VGIS; the divider resistor R1 and the divider resistor R2 reduce the isolation voltage to be collected to the input range of the K1. The operational amplifier T2 forms a voltage follower circuit and buffers an isolation voltage signal to be collected; the K1 converts analog voltage into digital quantity; the digital isolator K2 performs level conversion on the digital voltage signal, and the converted voltage value is output to the FPGA in the form of an I2C bus; in the non-isolated voltage acquisition circuit, divider resistors R7-R14 divide non-isolated voltage to be acquired into an input range of a four-channel analog / digital converter K3; the operational amplifiers T3-T11 form a voltage follower circuit and are used for buffering to-be-collected isolation voltage signals; and the K3 converts the analog voltage into a digital quantity and outputs the digital quantity to the FPGA in the form of an I2C bus. The method is used for accurately collecting five paths of voltage values of gyroscope and accelerometer channels in an optical fiber IMU (Inertial Measurement Unit).

The invention discloses a broadband digital phase shifter based on an inductor sharing topology and an equivalent band-pass network, relates to the technical field of microwave integrated circuits, and is suitable for being applied to a Sub-GHz frequency band. The phase shifter comprises a phase shift circuit module and a driving circuit module, and the phase shift circuit module comprises six basic phase shift units including a fine phase shift unit and a coarse phase shift unit which cooperatively realize full-range multi-state phase shift. The fine phase shift unit adopts an inductor sharing topology, so that a phase shift path and a reference path share a circuit architecture, the design is simplified, and the chip layout is optimized; the coarse tuning phase shifting unit adopts an all-pass network as a reference path, a phase shifting path is an equivalent band-pass network formed by cascading a high-pass network and a low-pass network, and the 180-degree phase shifter adopts a double-inductor all-pass network to optimize amplitude-frequency response. And the driving circuit module outputs complementary voltage pairs through the level conversion circuit to drive the switching transistor to realize path switching. The antenna has the advantages of being compact in structure, stable in amplitude, excellent in radio frequency performance and high in adaptability.

Circuits and methods are provided that more effectively and efficiently implement multi-level converter circuits, including circuits and methods that more effectively and efficiently transform a differential voltage in an upper voltage domain to a level-shifted differential voltage in a lower voltage domain. First and second signals are applied to a differential amplifier in the upper voltage domain to provide a pair of amplified voltages representing a differential amplified voltage. First and second level shifters are provided for translating each of the pair of amplified voltages to first and second output voltages, respectively, relative to a reference potential. The first and second output voltages collectively correspond to a differential level-shifted output voltage relative to the reference potential. The differential level-shifted output voltage may be applied to a fully-differential analog to digital converter.

The invention discloses a high-speed level shifter applied to a BUCK converter. The high-speed level shifter comprises a level shifting part, a control logic part and an output part, after the level shift part inputs a signal, a low-delay rising edge and a high-delay falling edge of a conversion level A, and a high-delay rising edge and a low-delay falling edge of a conversion level B are output; the input of the control logic part adopts CLK in a BUCK converter to generate a short pulse, a high-voltage domain where SW and BST are located is isolated from a low-voltage domain, when the short pulse is at a high level, an output control signal is high, and when the short pulse is at a low level, the output signal is low; the input of the output part is the output of the level shift part and the control logic, and when the control signal is high, a low-delay rising edge is selected to be output; and when the control signal is low, selecting to output a low-delay falling edge. The level shift result is output through double ports, and low delay of conversion between the rising edge and the falling edge is achieved.

The invention relates to an AB type output level shift circuit and equipment, and relates to the technical field of level shift. The AB type output level shift circuit comprises a first constant current source, a second constant current source, an input switch tube, a transconductance linear ring and an output module, a first electrode of the input switch tube is used for accessing a level signal, an input end of the output module is connected with an output end of the transconductance linear ring, and a power supply end of the output module is used for connecting a power supply. The grounding end of the output module is grounded, and the output end of the output module is connected with the second pole of the input switch tube, so that the transconductance linear ring is used for driving the output module to output AB type level shift signals based on the signals accessed from the input switch tube under the condition that the level signals are accessed to the input switch tube. By adopting the AB type output level shift circuit and the AB type output level shift equipment provided by the invention, the complexity of the circuit structure can be reduced.

The invention provides a repair circuit, a display panel and a display device. The repairing circuit comprises an input module, a first input end of which is connected with a to-be-repaired signal, a first output end of which is electrically connected with a first node, and which is used for carrying out voltage reduction processing on the to-be-repaired signal and then outputting a first input signal; and the processing module comprises a dedelay unit, a shaping unit and a level conversion unit. The control end of the de-delay unit is electrically connected to the first node, the input end is coupled with the corresponding clock signal, the output end is electrically connected to the second node, the de-delay unit is used for performing de-delay processing on the first input signal according to the corresponding clock signal and then outputting a de-delay signal, and the falling edge of the de-delay signal is consistent with the falling edge of the corresponding clock signal; the shaping unit is electrically connected to the second node and is used for shaping the waveform of the dedelayed signal and then outputting a square wave signal; and the level conversion unit is electrically connected to the output end of the shaping unit and is used for performing level adjustment on the square wave signal and then outputting a scanning repair signal.

A level shifter includes a level shifting circuit and a voltage tracking circuit. The level shifting circuit receives an input signal through an input terminal and converts the input signal from a first power domain to a second power domain to generate an output signal at an output terminal. The voltage tracking circuit is coupled to first and second voltage terminals, and tracks one with a lower level among voltages of the first and second voltage terminals to generate a control voltage. The level shifting circuit includes first and second N-type transistors. The first N-type transistor has a gate coupled to the input terminal, a drain coupled to a first node, and a source coupled to a ground. The second N-type transistor has a gate receiving the control voltage, a drain coupled to the output terminal at a second node, and a source coupled to the input terminal.

An electrical parameter measuring circuit for an output signal of an LED driver comprises an input end and an output end of the measuring circuit, a current sampling circuit, a switch circuit, a switch driving circuit, a voltage division circuit, a first voltage follower, a second voltage follower, an ADC acquisition circuit, a level conversion circuit, a multiplexing circuit and a single-chip microcomputer. The input end of the measuring circuit is connected with the input end of the voltage division circuit and the current sampling circuit, and the current sampling circuit is connected with the output end of the measuring circuit through the switching circuit. The output end of the voltage division circuit is connected with the input end of the first voltage follower, and the output end of the current sampling circuit is connected with the input end of the second voltage follower and the input end of the level conversion circuit. The input end of the ADC acquisition circuit is connected with the output ends of the first and second voltage followers, and the output end of the ADC acquisition circuit is connected with the single-chip microcomputer. The output end of the level conversion circuit is connected with the single-chip microcomputer through the multiplexing circuit. According to the utility model, various electrical parameters such as direct current and constant current output by the LED driver can be measured.

The invention discloses an automatic two-way transmission and level conversion buffer circuit applied to a Flash chip. The automatic two-way transmission and level conversion buffer circuit comprises an LDO (Low Dropout Regulator) circuit, a direction control buffer circuit and an automatic direction buffer circuit, the input end of the LDO circuit inputs a VIN signal and an EN enable signal respectively, and the LDO circuit provides voltage for other chips or internal circuits according to the VIN signal and the EN enable signal; an EN enable signal and a DIR selection signal are input into the control end of the buffer circuit for controlling the direction, and switching and switching of forward transmission and reverse transmission of signals input into the buffer circuit for controlling the direction are controlled through the EN enable signal and the DIR selection signal. An EN enable signal is input into the control end of the automatic direction buffer circuit, and level conversion of two input ports of the automatic direction buffer circuit is controlled through the EN enable signal; compatibility of the Flash chip to different SPI protocols and different voltage domains are met, interference of power supply noise to an internal chip is effectively restrained, and control over the transmission direction of transmission signals is achieved.

The invention discloses a level shift circuit, a control method thereof and electronic equipment, and relates to the technical field of integrated circuits. The circuit comprises a logic control module, an AC / DC coupling module and an inverted output module, in the logic control module, a first signal input end is connected with an input signal source, and a second signal input end is connected with an enable signal source; the AC-DC coupling module comprises a DC coupling unit and an AC coupling unit; in the direct current coupling unit, a first control input end is connected with a first control output end, and a second control input end is connected with a second control output end; in the AC coupling unit, an AC coupling input end is connected with a first control output end; the AC coupling output end is connected with the DC coupling output end; the inverted input end of the inverted output module is connected with the DC coupling output end, and the inverted output end is used for outputting a target level shift signal. And a low-delay, high-speed and good-duty-ratio level shifting function can be realized for an alternating current signal and a direct current signal.

The invention discloses a wide-input-range low-power-consumption level shift circuit, which relates to the technical field of electronic equipment and comprises a current mirror branch and a logic error diagnosis circuit. The current mirror branch is connected with the logic error diagnosis circuit; the current mirror branch at least comprises a first phase inverter and a second phase inverter; the first phase inverter and the second phase inverter are used for ensuring that the static power consumption is about zero and reducing the transient power consumption of the circuit; the logic error diagnosis circuit is used for ensuring that the input level is consistent with the output level. The level shift circuit is constructed by adopting the current mirror, so that the competitive relationship between an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor) is avoided, and a wide input voltage range can be A phase inverter is inserted into a current mirror branch to reduce power consumption. The logic error diagnosis circuit avoids a logic error caused by inconsistent input and output levels of the shifter; level conversion in a wide input voltage range is achieved, low static power consumption and dynamic power consumption are achieved, and rail-to-rail output swing can be achieved.

The invention provides a high-gain wide-output ring amplifier and a pipelined SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-gain wide-output ring amplifier comprises a ring amplification module, a level shifting capacitor, a transmission gate switch module and a cascode module, the annular amplification module is used for acquiring a residual signal output by the adjacent SAR ADC module and performing amplification processing on the residual signal to obtain a residual amplification signal; the level shift capacitor is used for performing wide-swing processing on the residual amplification signal under the control of the transmission gate switch module to form a wide-output residual amplification signal; the cascode module adopts a cascode amplification circuit to improve the voltage gain of the annular amplification module; and a high-gain wide-output ring amplifier is arranged between every two SAR ADC modules in the assembly line SAR ADC. Therefore, the gain and the response speed of the assembly line SAR ADC are improved, and the power consumption and the signal delay accumulation are reduced at the same time.