1541 results about "Level shifting" patented technology

A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.

A power factor corrected (pfc) ac-dc converter has a modified boost input and a modified buck output. Unlike the prior art boost input, the boost switch returns to the output, not to ground. Unlike the prior art buck output stage, a third switch connects to the input. This allows much of the input current to pass through the converter to the output. There is no input current measurement, but nearly ideal power factor correction is achieved through “natural modulation.” A preferred pfc ac-dc converter uses a variable dc-dc transformer on its output, as a post regulator, to provide dielectric isolation and to provide voltage level shifting. The output of the pfc ac-dc converter has the control characteristics of a buck converter, so it is a natural mate for the variable dc-dc transformer. An ac-dc buck converter is most efficient at its maximum duty cycle. It cannot regulate for a lower input voltage, but it can reduce its duty-cycle to control for higher input voltages. A variable dc-dc transformer is most efficient at its maximum ratio. It cannot regulate for a higher input voltage, but it can reduce its effective turns ratio to control for a lower input voltage. With a small overlap in their control ranges, both parts of the power system can operate at maximum efficiency. The variable dc-dc transformer controls the output voltage for nominal and low input voltage. The ac-dc buck converter limits over-voltage transients.

The invention provides a gate drive circuit and method and a display device and relates to the technical field of display. The method includes the steps that gate row drive scanning is performed on shifting register units located in a first area in the gate drive circuit; after gate row drive scanning of the shifting register units in the first area is finished, touch scanning is performed; after touch scanning is finished, the last-level shifting register unit located in the first area is scanned again so that the last-level shifting register unit located in the first area can be used for pre-charging a first-level shifting register unit located in a second area; gate row drive scanning is performed on shifting register units located in the second area in the gate drive circuit, and the last-level shifting register unit located in the first area is in cascade connection with the first-level shifting register located in the second area. The method can overcome the defect that the row pixel charging rate is insufficient and solve the problem of dark lines or poor bright lines.

In a PFC (Power Factor Correction) converter control unit, a PWM (pulse width modulated) signal is produced by comparing a PFC converter output voltage error signal, produced by a transconductance amplifier, with a ramp signal, which may be from a control unit of a resonant mode converter in cascade with the PFC converter. Level shifting is used to match the amplitude ranges of the compared signals. A current, representing an input current of the PFC converter and produced by a current mirror, is switched by the PWM signal to a parallel resistance and capacitance to produce a smoothed voltage constituting a control signal for the PFC converter.

The invention provides a shifting register unit, a grid electrode drive circuit and a display device. The shifting register unit comprises an output up-pull transistor, an up-pull node down-pull transistor, an output down-pull transistor, an output transistor, a bootstrap capacitor, an up-pull drive unit, a down-pull drive unit, a first resetting unit and a second resetting unit, wherein the first resetting unit is respectively connected with a first resetting end, an up-pull node, a local-level output end and a low-level output end; the first resetting end is connected with the output end of a next-level shifting register unit; the second resetting unit is respectively connected with a second resetting end, a local-level output end and a low-level output end; and the second resetting end is connected with the output end of a Nth-level shifting register unit after being connected with a previous-level shifting register unit, and the N is an integer which is more than one. At least two resetting units are adopted to inhibit the noise between the first unit time after the current output and the Nth unit time.

A voltage level shifting circuit (10) transitions an input signal at a first voltage to a second voltage higher than the first voltage. A cross-coupled latch provides the second voltage. Cascode configured transistors (16, 26) are connected in series with input transistors (18, 28) that receive the first voltage in complementary form. Capacitive devices (34, 40) are connected between the first voltage and gates of the cascode configured transistors for allowing independent small signal variations to occur on the gates of the cascode configured transistors for better control of duty cycle and rise and fall time matching of the level shifting circuit. Isolation devices (32, 38) permit independent modification of small signal voltages to occur on the gates of the cascode configured transistors.

The present invention relates to a device for individually driving OLED/LED elements of an OLED/LED string, comprising for each OLED/LED element of the string: a controllable shunting switch (22, 42) coupled with the respective OLED/LED element (14, 15), switch controller means (30, 44) for controlling said shunting switch (22, 42) and having a control output port coupled to said switch (22, 42), a data input port and a clock input port, level shifting means (32) assigned to said switch controller means (30, 44) and adapted to bring the control input data to a level sufficient to be accepted by the switch controller means (30, 44) during a programming mode and to allow the control of said shunting switch (22, 42). Said switch controller means (30, 44) of said OLED/LED elements (14, 15) are provided to form a serial-to-parallel converter means (31).

A level shifting circuit with a power monitor enable for mixed-voltage applications is described. The level shifter translates signals from a first power supply voltage domain to a second. The level shifter provides a known output state, rather than an undefined mid-rail state, when either of the power supplies for the voltage domains is not adequately powered. In addition, the level shifter is IDDQ (quiescent current) compliant when static, drawing negligible current from the power supply. The level shifter can be used with a power monitor circuit, which controls the level shifter during power-up with an enable signal.

The clamp circuit clamps an input voltage at prescribed higher and lower clamp voltages which are stabilized under a temperature fluctuation. Transistors Q12 and Q14 are switched on in their linear region. In a lower voltage clamp circuit 18, an Vin detecting circuit 20 outputs Va1 by level-shifting Vin by Q13 and voltage-divides by series resistance circuit 23 the level-shifted Vin, while a reference voltage generating circuit 21 outputs Vr1 by level-shifting 0 V by Q15 and voltage-divides by series resistance circuit 25 the level-shifted voltage. Q11 is switched on, when a comparator 22 determines that Va1 descends and goes across Vr1. Here, Q12 is of the same characteristics as Q14, while Q13 is of the same characteristics as Q15. Further, the resistance of the circuits 23 is the same as that of the circuit 25. The higher voltage clamp circuit 19 is similar to the circuit 18.

It is intended to obtain a high quality image which is not affected by the fluctuation of dark outputs, and pixels having a specifically large dark output, called defects, and has no lateral line etc. A solid-state image pickup apparatus including: an aperture pixel region which accumulates and outputs the electric charges generated depending on incident light; a light shielded optical black region; a black reference pixel region in which no impurity region for accumulating electric charges is formed; and level shifting means which shifts the reference level of the output signals of the black reference pixel region with respect to the reference levels of the output signals of the aperture pixel region and the optical black region, is provided.

Latch circuitry has a data input stage for sampling a first input signal responsive to a first timing signal and generating a signal on an intermediate node in the latch circuitry. The latch circuitry also has a scan input stage for sampling a second input signal responsive to a second timing signal, and generating a signal on the intermediate node. The latch circuitry also has an output stage for generating an output signal on an output node of the latch circuitry responsive to the signal on the intermediate node and a third timing signal. The data input signal has a maximum voltage level and at least one stage of the latch circuitry is operable to effectively shift the voltage level so that the output signal has a higher maximum voltage level than that of the data input signal.

A composite high voltage schottky rectifier is revealed that provides a forward voltage slightly larger than a low voltage schottky rectifier combined with a high voltage breakdown capability. The composite rectifier can be formed from the combination of a low voltage schottky rectifier, a high voltage mosfet, and a few small passive components. A quarter bridge primary switching network similar in some ways to a half bridge primary switching network is revealed. The quarter bridge network consists of four switches with voltage stress equal to half the line voltage and the network applies one quarter of the line voltage to a primary magnetic circuit element network thereby reducing the number of primary winding turns required to one quarter by comparison to a common full bridge network. A synchronously switched buck post regulator is revealed for multi-output forward converters. The synchronously switched buck post regulator accomplishes precise independent load regulation for each output and reduced magnetics volume by using a coupled inductor with a common core for all outputs plus a second smaller inductor for each output except the highest voltage output. An improved capacitor coupled floating gate drive circuit is revealed that provides an effective drive mechanism for a floating or high side switch without the use of level shifting circuits or magnetic coupling. The capacitor coupled floating gate drive circuit is an improvement over prior art capacitor coupled floating gate drive circuits in that the new circuit uses a positive current feedback mechanism to reject slowly changing voltage variations that cause unintentional switch state changes in prior art capacitor coupled floating gate drive circuits.

Disclose is a semiconductor memory device including a plurality of memory cell arrays, row and column decoders for selecting/driving each memory cell, and a plurality of bit line sensing amplifier arrays for sensing data of each memory cell, the semiconductor memory device comprising: a plurality of sub word line driver sections for driving each memory cell with a sub word line enable selection signal (SWLE) decoded by LSB address and with a global word line signal (GWLb) decoded by MSB address in the row decoder; a row decoding precharge signal generating section (RDPRi/VBFi) for applying a precharge signal to the row decoder and a voltage Vbb to the GWLb signal by means of the MSB address PXb; a level shifting section for shifting and transmitting an output signal from the column decoder to column selection lines which connects the column decoder with the bit line sensing amplifier array in series; and a data input/output controlling section for selectively applying an active signal to the bit line sensing amplifier array according to a level of the column selection line.

A driving circuit comprises an input terminal receiving an input of a PWM signal, a first output terminal connected to a main switch for outputting a low-side driving signal, a second output terminal connected to an active switch for outputting a high-side driving signal, a first branch having a voltage level shifting capacitor and a first buffer connected in series between the input terminal and the second output terminal; and a second branch having a delay circuit and a second buffer connected in series between the input terminal and the first output terminal. When the input of the PWM signal turns from a low level to a high level, the voltage level shifting capacitor transmits the input of PWM signal to the first buffer for turning off the active switch and then triggering the second buffer to turn on the main switch with a short time delay.

Embodiments of the present invention recite a level shifting circuit for high voltage protection. In embodiments of the present invention, the level shifting circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor coupled in a cascode configuration. The circuit further comprises a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor coupled in a cascode configuration. The level shifting circuit further comprises an output coupled with the source of the first transistor, the gate of the seventh transistor, and with the drain of the second transistor. A first inverter is coupled with a second inverter in series and an input signal conveyed to the first inverter dynamically controls the bias level for said second and sixth transistors.

The embodiment of the invention discloses a grid driving circuit, an array substrate, a display device and a driving method. The grid driving circuit is used for solving the problem that a large amount of power is consumed when an existing grid driving circuit works. The grid driving circuit comprises at least one sub-circuit, wherein each sub-circuit comprises M shifting register units, and M is a positive integer which is equal to or lager than 3; in any sub-circuit, the shifting register units used for driving odd grid signal lines are connected in sequence, the output end of an upper-level shifting register unit in the shifting register units used for driving the odd grid signal lines is connected with the input end of a lower-level shifting register unit, the shifting register units used for driving even grid signal lines are connected in sequence, and the output end of an upper-level shifting register unit in the shifting register units used for driving the even grid signal lines is connected with the input end of a lower-level shifting register unit. The grid driving circuit, the array substrate, the display device and the driving method have the advantages that power consumption is reduced on the premise that display quality is guaranteed.

The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance and a drain-to-gate resistance of the FET element and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element, a resistive element, a source-coupled level shifting diode, and a reverse protection diode. Therefore, the ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

An enable circuit receives an input enable signal that is referenced to a first voltage and generates a level-shifted output enable signal referenced to a second voltage. Bias control circuitry prevents shoot-through currents during ramping of the first voltage and from causing indeterminate logic levels of the level-shifted output enable signal. An enabled level-shifting circuit receives an input logic signal that is referenced to the first voltage and generates a level-shifted output logic signal referenced to the second voltage. Enable circuitry operates in response to the level-shifted output enable signal to enable normal level-shifting operation while the first and second voltages are at normal operating levels and prevents shoot-through currents in the enabled level-shifting circuit from causing indeterminate levels of the level-shifted output logic signal.