37 results about "Reference level" patented technology

The application discloses a signal interference strategy generation method and device based on deep learning, and a medium, and relates to the technical field of signal interference. The method comprises the following steps: calculating initial path rain attenuation values corresponding to reference level sampling data and real-time level sampling data; filtering a wet antenna attenuation component of the real-time level sampling data through digital filtering based on the initial path rain attenuation values, and determining pure path rain attenuation values of each communication link; inverting the pure path rain attenuation values to obtain path average rain intensities corresponding to each communication link; performing spatial interpolation optimization on a preset interference area to determine a two-dimensional rainfall intensity distribution map; calculating signal propagation time delay of an interference target ray track to obtain interference target corrected coordinates; and determining an interference strategy corresponding to the interference target through link interference parameter calculation and interference window prediction. The application solves the technical problem that the signal interference strategy in the prior art cannot meet the dynamic requirements of an interference signal link in a rainfall environment.

A pipeline analog-to-digital converter includes N pipeline conversion stages cascaded in sequence, and in the first N−1 pipeline conversion stages, at least one pipeline conversion stage includes a dither generating module and a multiplying digital-to-analog conversion module. In the present application, a flash-type analog-to-digital conversion unit in the multiplying digital-to-analog conversion module includes a quantization reference level generating circuit, and under the action of a random digital signal, the quantization reference level of a comparator in the flash-type analog-to-digital conversion unit is shifted by the quantization reference level generating circuit, thereby equivalently adding a dither signal to an input analog signal.

The invention provides a ground bounce noise suppression circuit and a circuit board, which can be applied to the technical field of circuits. The ground bounce noise suppression circuit includes a capacitor and a diode connected in series between a first ground region and a second ground region of a circuit board, in which a forward conduction path of the diode corresponds to a direction from the first ground region to the second ground region, the reference level fluctuation tolerance of the second grounding area is greater than that of the first grounding area, and the projections of the first grounding area and the second grounding area in the thickness direction of the circuit board are not overlapped.

The invention belongs to the technical field of integrated circuit design, and particularly discloses a low-delay sampler structure and method for high-speed data processing, and in a pseudo reset stage, an unlocking network module and a pre-latching network module are connected in parallel to form an equivalent low-impedance network unit; the transconductance module is used for inputting a sampling signal and a reference level signal and driving the equivalent low-impedance network unit; the pre-latch network module is used for enabling an output node of the pre-latch network module to start charging and discharging according to a sampling signal and a reference level signal and pre-sampling the sampling signal; meanwhile, in the latching stage, the transconductance module is used for driving the pre-latching network module to preliminarily amplify the sampling signal, and the strong latching network module is used for stably latching the sampling signal under the driving of the pre-latching network module. According to the invention, the sampling delay of the signal is obviously shortened, and meanwhile, the requirement of high-speed data processing on the time sequence progress is met.

A transmitter includes an analog transmission circuit, a power amplifier, a voltage detector, a comparator, and a control circuit. The analog transmission circuit is configured to provide a first gain to a first analog signal, so as to generate a second analog signal. The power amplifier is configured to provide a second gain to the second analog signal, so as to generate an output signal to an antenna. The voltage detector is configured to detect a voltage level of the second analog signal. The comparator is configured to generate an indication signal according to the voltage level and a reference level. The control circuit is configured to adjust the first gain of the analog transmission circuit according to the indication signal.

A magnetic resonance examination method comprises acquisition of a set of magnetic resonance signals from magnetic spins in an object by way of a receiver antenna, the magnetic resonance signals' signal levels are related to an independent reference level that is independent of the receiver antenna's sensitivity to form a calibrated signal level of the magnetic resonance signals, the calibrated signal levels are recorded in terms of a relative density of ordered transverse spins (DOTS). The independent reference level may be derived from the signal-to-thermal-noise ratio. The calibrated signal level in terms of DOTS in μM / T reflects predominantly a tissue property (of (a voxel of) the patient to be examined) as well as details or characteristics of the acquisition sequence used.

According to the zero-delay CT SDM excessive loop delay compensation method, the feedback coefficient of loop delay compensation can be adjusted by changing the specific value of different sampling capacitors in a switched capacitor network, the reference level of an embedded quantizer is used for adjusting the gain of the quantizer, the number of ports, connected to the reference level, of a comparator in the Flash quantizer is reduced, and meanwhile the power consumption of the Flash quantizer is reduced. The power consumption of the comparator can be effectively reduced, and the whole circuit is simple in structure and has zero delay.

The invention discloses a broadband intermediate-frequency processing circuit and a control method thereof, and relates to the technical field of electronic measurement, the broadband intermediate-frequency processing circuit comprises double intermediate-frequency channels, the broadband intermediate-frequency channel is 307.2 MHz, the narrowband intermediate-frequency channel is 288MHz, and an intermediate-frequency conditioning circuit comprises a change-over switch, a broadband filter, a narrowband filter and five amplifiers. The method can be applied to the frequency spectrograph in different working modes, and intermediate frequency signal paths corresponding to the broadband are provided; different intermediate frequency channel gains are provided for the frequency spectrograph under different reference levels, a low-power-consumption mode of the system is realized through enabling control of the amplifier, and the requirements under different applications are met.

The application relates to the technical field of integrated circuit signal detection, and provides a baud rate signal detection circuit and a CDR loop structure which are composed of two data samplers, one error sampler and a digital logic circuit, can provide better jitter performance compared with a traditional MMPD, do not need to depend on accurate reference level VRFE amplitude setting, and have relatively lower design difficulty compared with traditional designs. In addition, the signal detection circuit can also detect the frequency deviation between input data and a sampling clock, so that the baud rate CDR function with a wide frequency capture range can be realized by using only a single control loop without increasing additional clock and sampling circuits, external reference clocks are not needed, the difficulty of the performance and cost compromise mentioned above can be greatly reduced, and the overall design cost is greatly reduced.

The application discloses a kind of digital quantity output control's fault identification system and method, the first control unit in the digital quantity output control device in the system, output pin reference level and periodic communication data are sent to the second control unit in the digital quantity output control device, the second control unit, the output pin actual level of first control unit is acquired, whether the pin output fault of first control unit exists according to output pin reference level and output pin actual level judges, realize the detection of pin damage, and, whether the running fault of first control unit exists according to the periodic communication data received judges, realizes the fault detection of the control unit in the digital quantity output control device.The system realizes the fault identification of digital quantity output control, improves the security of digital quantity output control, guarantees the normal operation of the controlled external equipment.

The application discloses a double residual quantization method and application for a multi-stage analog-to-digital converter, the multi-stage analog-to-digital converter comprising a front-stage quantizer, an inter-stage amplifier and a back-stage quantizer; the front-stage quantizer performs preliminary quantization on an input signal and generates a quantization result; two residual signals are generated at the output end of the front-stage quantizer based on the quantization result; the two residual signals contain quantization error information of the front-stage quantizer and reference level information of the front-stage quantizer; the two residual signals are transmitted to the back-stage quantizer after being amplified by the inter-stage amplifier; the back-stage quantizer is designed as a delta-sigma modulator; the back-stage quantizer directly quantizes the quantization error of the front-stage quantizer through the two residual signals; and the reference level information of the front-stage quantizer is introduced into a converted signal according to the conversion result of the back-stage quantization, and is used for updating a back-stage loop filter. The application maintains the robustness of the inter-stage gain error, and realizes high-precision, high-speed and high-energy-efficiency analog-to-digital conversion performance.

A switching power converter includes: a power stage circuit for converting an input voltage to an output voltage by switching an inductor with a synchronous or an asynchronous mode; an error amplifier to generate an error amplified signal; a modulation comparator for generating a primary modulation signal by comparing the error amplified signal and a ramp signal; a pulse skipping comparator for generating a pulse skipping control signal by comparing the error amplified signal and a skipping reference signal; and a switching control unit for masking the primary modulation signal by the pulse skipping control signal. During the synchronous mode, the skipping reference signal has a predetermined reference level. At the beginning after the synchronous mode is changed to the asynchronous mode, the skipping reference signal turns to the predetermined reference level superposing a compensation reference level, and subsequently the skipping reference signal gradually returns to the predetermined reference level.

The utility model discloses an electrocardio analog signal acquisition circuit for a teaching experiment, which comprises an instrument amplification circuit, a first-stage amplifier, a second-stage amplifier, a first-stage amplifier, a second-stage amplifier, a second-stage amplifier, a first-stage amplifier, a second-stage amplifier and a third-stage amplifier, the band-pass filter circuit comprises an operational amplifier and a resistance-capacitance combination formed by a plurality of capacitors and resistors, and the resistance-capacitance combination formed by the plurality of capacitors and resistors is connected with the operational amplifier; the low-pass filter circuit comprises an operational amplifier and a resistance-capacitance combination formed by a plurality of resistors and capacitors, and the different resistance-capacitance combinations formed by the plurality of resistors and capacitors are connected with the operational amplifier; the level raising circuit comprises a multi-way switch and different resistor combinations, the bias level of an input signal is adjusted through a voltage dividing network, the reference level of a preceding-stage signal is raised to a direct-current level range suitable for subsequent processing, and by arranging an adjustable resistor and capacitor network, collection and conditioning of an electrocardio analog signal are achieved.

A successive approximation analog-to-digital conversion circuit and a method of operating the same are disclosed. The successive approximation analog-to-digital conversion circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The plurality of latch circuits are coupled to the comparator circuit and are serially connected to each other. The plurality of latch circuits are sequentially triggered to store comparator outputs of the comparator circuit in response to a plurality of trigger signals, respectively, and to generate a digital signal accordingly. A first latch circuit and a second latch circuit of the plurality of latch circuits are triggered in response to a first trigger signal and a second trigger signal of the plurality of trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal based on the comparator output stored in the first latch circuit. The successive approximation analog-to-digital conversion circuit is capable of providing more time margin for a settling time of a digital-to-analog converter.

A wearable device comprises at least one processor, memory storing instructions, a plurality of microphones, and a speaker. The instructions that, when executed by the at least one processor individually or collectively, cause the wearable device to: execute an ambient sound function, perform a measurement with respect to a sound of an ambient environment of a user using a first outer microphone, refrain from performing a measurement with respect to the sound of the ambient environment of the user using a second outer microphone, obtain sound data according to the measurement performed using the first outer microphone, in accordance with a level of the sound data less than or equal to a reference level, output a sound of the ambient environment based on the sound data, and in accordance with the level of the sound data greater than the reference level, perform the measurement using the second outer microphone.

The invention relates to the technical field of radar signal processing, in particular to a self-adaptive distributed radar intermittent sampling and forwarding interference resisting method, which is used for accurately and stably detecting a real target when encountering intermittent sampling and forwarding interference and comprises the following steps of: performing signal-level interference alignment processing through echoes of a plurality of receiving stations; and realizing intra-pulse coherent-level intermittent sampling forwarding interference cancellation fusion processing and optimization under the optimal site combination by adopting a simulated annealing-particle swarm search sequence optimization algorithm. According to the method provided by the invention, by virtue of the characteristics of high power gain of intermittent sampling and forwarding interference and high correlation of homologous interference radiation, the adaptive distributed radar intermittent sampling and forwarding interference resisting method provided by the invention has relatively good robustness in the environment of resisting different types of intermittent sampling and forwarding interference and different interference-to-signal ratios; and the target accurate detection capability in an information battlefield confrontation environment is improved.

The invention relates to the technical field of microwaves and millimeter waves, in particular to an over-temperature self-protection circuit for a high-power assembly. The over-temperature self-protection circuit for the high-power component comprises a temperature sensing circuit, a reference circuit and a comparison circuit, wherein the temperature sensing circuit is used for converting a temperature signal into a voltage signal VSIG; the reference circuit is used for providing a reference level signal VREF to determine a judgment threshold; the comparison circuit is used for comparing the voltage signal VSIG with the reference level signal VREF; the logic circuit is used for performing AND logic operation on the high and low levels and an original control signal of the high-power device; the comparison circuit is electrically connected with the temperature sensing circuit, the reference circuit and the logic circuit. When it is detected that the temperature in the high-power assembly exceeds a threshold value, a control signal can be generated to rapidly turn off a high-power device without intervention of a high-power system, and self-protection of the high-power assembly during overtemperature is achieved.

A computer-implemented method of processing an audio signal. The method comprises: receiving from two or more microphones, respective audio signals; deriving a plurality of time-frequency signals from the received audio signals, indexed by frequency, and for each of the time-frequency signals: determining in-beam components of the audio signals; and performing post-processing of the received audio signals, the post-processing comprising: computing a reference level based on the audio signals; computing an in-beam level based on the determined in-beam components of the audio-signals; computing a post-processing gain to be applied to the in-beam components from the reference level and in-beam level; and applying the post-processing gain to the in-beam components.

A switching power converter includes: a power stage circuit for converting an input voltage to an output voltage by switching an inductor with a synchronous or an asynchronous mode; an error amplifier to generate an error amplified signal; a modulation comparator for generating a primary modulation signal by comparing the error amplified signal and a ramp signal; a pulse skipping comparator for generating a pulse skipping control signal by comparing the error amplified signal and a skipping reference signal; and a switching control unit for masking the primary modulation signal by the pulse skipping control signal. During the synchronous mode, the skipping reference signal has a predetermined reference level. When the synchronous mode is changed to the asynchronous mode, the skipping reference signal turns to the predetermined reference level superposing a compensation reference level, and subsequently the skipping reference signal gradually returns to the predetermined reference level.

The present disclosure relates to an analog-to-digital converter, comprising: one or more comparators, each signal with a variable configured to compare an analog reference level specific to the comparator; a controller coupled to an output of the one or more comparators and configured to generate a control signal indicating the reference level of each comparator as a function of an output signal from each of the one or more comparators and configured to generate a digital output signal based on the output signal from each of the one or more comparators.

The application provides a ground bounce noise suppression circuit and a circuit board, which can be applied to the technical field of circuits. The ground bounce noise suppression circuit comprises a capacitor and a diode, which are connected in series between a first grounding area and a second grounding area of a circuit board, wherein a forward conduction path of the diode corresponds to a direction from the first grounding area to the second grounding area, wherein a reference level fluctuation tolerance of the second grounding area is greater than a reference level fluctuation tolerance of the first grounding area, and projections of the first grounding area and the second grounding area along a thickness direction of the circuit board do not overlap.

The invention discloses a signal demodulation method, circuit and device, a storage medium and electronic equipment. Relates to the field of signal processing, and the method comprises the steps: obtaining a to-be-demodulated input signal, the input signal employing pulse position modulation; performing comparison processing on the input signal and the delay signal of the input signal through a first comparator to obtain a pulse position modulation signal; comparing the input signal with a reference level through a second comparator to obtain a signal triggering moment level; and under the condition that the level meets the triggering condition at the signal triggering moment, the pulse position modulation signal is demodulated through the single chip microcomputer. According to the invention, the problem that the signal demodulation cost is high when preprocessing of signal demodulation is carried out based on an FPGA chip in the prior art is solved.

The invention provides a comparator offset background calibration method and circuit for a delta-sigma type ADC, and the method comprises the steps: carrying out the shuffling of a reference level, inputting the shuffled reference level into a comparator array and a serial-to-parallel converter, and outputting a plurality of periods of digital codes; a moving average value determination step: determining a moving average value corresponding to each comparator of the plurality of periods by using an EWMA algorithm according to the digital codes of the plurality of periods; calculating the average value of the moving average values of the plurality of periods of all the comparators; determining relative imbalance information according to the moving average value and the average value of each comparator; and the control codes in the to-be-calibrated comparators are trimmed in parallel according to the relative imbalance information, the moving average value determination step is returned until the moving average values and the average values corresponding to the comparators meet preset conditions, the reset signals and the enable signals are made to become low levels, iteration is stopped, and calibration is completed. The calibration complexity, the power consumption and the area are reduced, and the linearity and the quantization precision of the delta-sigma type ADC are improved.

This application provides an automatic on-chip clock frequency calibration method and related apparatus. The automatic on-chip clock frequency calibration method includes: a calibration module acquiring a reference clock containing N... ref The reference level for each cycle; the calibration module uses the current clock of the oscillator to calculate the reference level, which contains N values ​​within its width. o One cycle; if the theoretical number of cycles N os With N o If the absolute value of the difference is greater than the set error DN, the calibration module adjusts the frequency control parameter through the parameter adjustment module. The frequency control parameter is used to change the current frequency of the oscillator; N os Based on the reference clock's reference frequency, the oscillator's target frequency, and N... ref Determined; if N os With N o If the absolute value of the difference is less than the set error DN, the calibration module determines that the oscillator calibration is successful. This embodiment of the application can shorten the calibration time for the on-chip clock frequency.

The application relates to a kind of ultra-high shielding effectiveness measurement methods, comprising: step S1, shielding effectiveness measurement system is built;Step S2, the frequency deviation of signal source transmitting signal frequency and signal analyzer corresponding received signal frequency is measured, and the frequency of all test frequency points corresponding to the frequency set when shielding effectiveness measurement is carried out is compensated;Step S3, after completing frequency offset compensation, 1dB compression point test is carried out to signal analyzer, the 1dB compression point power of signal analyzer under all test frequency points is acquired, and the dynamic matching power of signal source under all test frequency points is calculated;Step S4, reference level measurement system is built, and the reference level of signal analyzer under all test frequency points is measured;Step S5, the power value corresponding to all test frequency points after shielding is measured in shielding effectiveness measurement system, and the shielding effectiveness of the shielding room to be measured is acquired according to the reference level.The application realizes the requirement of ultra-high performance shielding effectiveness measurement.

A method comprising: obtaining (601) input video data in an input dynamic range and interoperability metadata; converting (602) the input video data in output video data in an output dynamic range using the interoperability metadata; wherein, the interoperability metadata comprise at least an information representing an HDR reference level value, an information representing an SDR reference level value.

The present description relates to an analog-to-digital converter (300), comprising: - one or more comparators (304), each configured to compare an analog signal (VIN) with a variable reference level (REF) specific to the comparator; - a controller (306) connected to an output of the one or more comparators (304) and configured to generate a control signal (CTRL) indicating the reference level (REF) of each comparator (304) as a function of an output signal of each of the one or more comparators and configured to generate a digital output signal (NUM) based on the output signal of each of the one or more comparators.

The invention relates to the technical field of circuits, in particular to a current detection circuit and a robot, and the current detection circuit comprises a differential input unit which is used for carrying out the differential detection of a current output by a current source, and obtaining a first differential signal and a second differential signal; the differential filtering unit is connected to the differential input unit and is used for filtering the first differential signal to obtain a signal to be detected and filtering the second differential signal to obtain a reference signal corresponding to the signal to be detected; the comparison unit is connected with the differential filtering unit and is used for performing voltage comparison on the signal to be detected and a reference signal to obtain a comparison result signal; and the output unit is connected with the comparison unit and is used for outputting a current detection signal to the controller based on the comparison result signal. According to the current detection circuit, the reference level input by the comparison unit can be dynamically adjusted according to the differentially input second differential signal, so that the influence caused by the level shift of the ground wire is reduced, and the over-current detection accuracy is improved.

For receiver circuits, Sampler offset calibration techniques are provided. In some embodiments, an output of an analog front end circuit may be tuned to a reference level that is used for an input of the sampler, and the sampler may then be calibrated to reduce an offset between its inputs.

The present disclosure relates to an analog-to-digital converter (300) comprising:-one or more comparators (304), each configured to compare an analog signal (VIN) with a comparator-specific variable reference level (REF); a controller (306) coupled to an output of the one or more comparators (304) and configured to generate a control signal (CTRL) indicative of a reference level (REF) of each comparator (304) in dependence on an output signal of each of the one or more comparators (304), and configured to generate a digital output signal (NUM) based on an output signal of each of the one or more comparators.