56 results about "Reference level" patented technology

The invention provides a self-adaptive equalization circuit and a self-adaptive equalization method, and relates to the technical field of data communication. The adaptive equalization circuit comprises an equalizer, a gain amplifier, a signal acquisition unit and a digital control unit, the signal acquisition unit comprises a low-pass filter, a first power detection module and a first comparator, and the output end of the equalizer is connected with the gain amplifier to form a signal path. The output end of the equalizer, the low-pass filter, the first power detection module and the first input end of the first comparator are sequentially connected, the second input end of the first comparator is used for inputting a reference level, and the digital control unit is respectively connected with the output end of the first comparator and the gain amplifier; the digital control unit is used for adjusting the reference level according to the first comparison result until the first comparison result output by the first comparator conforms to a preset signal mode; and the gain of the gain amplifier is adjusted according to the corresponding reference level in the preset signal mode. The method has the effect of reducing power consumption.

The invention relates to a high-speed data transceiving circuit supporting multiple modulation modes. The high-speed data transceiving circuit comprises a multi-mode modulation unit, a multi-mode demodulation unit, a clock signal generation unit and a control unit, wherein the multi-mode modulation unit responds to a control signal generated by the control unit to determine a modulation type of a signal to be modulated, responds to a first clock signal CK1 sent by the clock signal generation unit to determine a corresponding modulation period so as to modulate the signal to be modulated to obtain a modulation signal, and responds to the first control signal to modulate the signal to be modulated to obtain the modulation signal. Transmitting the modulation signal; and the multi-mode demodulation unit obtains the modulation signal, selects a corresponding reference level signal in response to the control signal, compares the reference level signal with the modulation signal to obtain a comparison result, and determines a corresponding demodulation period in response to a second clock signal CK2 sent by the clock signal generation unit to demodulate the comparison result to obtain a required demodulation signal. The circuit can be integrated on a chip to support data transceiving of multiple modulation types.

The present disclosure provides a multipath signal decomposition method enabling to estimate paths and path parameters. The method includes: (a) acquiring observation data including a plurality of multipath signal components; (b) for each multipath signal component, determining one or more basis vectors maximizing a projection; (c) calculating a residual using basis vectors having an orthogonality higher than a predetermined reference level with a new basis vector and performing a sub-optimization by updating a basis vector maximizing a projection of the residual among the basis vectors having the orthogonality lower than the reference level; (d) unless a termination condition is satisfied, repeating the operations (b) and (c) to determine an additional basis vector and determine basis vectors of a minimum number expressing a corresponding multipath signal component while avoiding a redundancy of the basis vectors; and (e) when the termination condition is satisfied, determining coefficients of basis vectors and parameters.

The application discloses a signal interference strategy generation method and device based on deep learning, and a medium, and relates to the technical field of signal interference. The method comprises the following steps: calculating initial path rain attenuation values corresponding to reference level sampling data and real-time level sampling data; filtering a wet antenna attenuation component of the real-time level sampling data through digital filtering based on the initial path rain attenuation values, and determining pure path rain attenuation values of each communication link; inverting the pure path rain attenuation values to obtain path average rain intensities corresponding to each communication link; performing spatial interpolation optimization on a preset interference area to determine a two-dimensional rainfall intensity distribution map; calculating signal propagation time delay of an interference target ray track to obtain interference target corrected coordinates; and determining an interference strategy corresponding to the interference target through link interference parameter calculation and interference window prediction. The application solves the technical problem that the signal interference strategy in the prior art cannot meet the dynamic requirements of an interference signal link in a rainfall environment.

A pipeline analog-to-digital converter includes N pipeline conversion stages cascaded in sequence, and in the first N−1 pipeline conversion stages, at least one pipeline conversion stage includes a dither generating module and a multiplying digital-to-analog conversion module. In the present application, a flash-type analog-to-digital conversion unit in the multiplying digital-to-analog conversion module includes a quantization reference level generating circuit, and under the action of a random digital signal, the quantization reference level of a comparator in the flash-type analog-to-digital conversion unit is shifted by the quantization reference level generating circuit, thereby equivalently adding a dither signal to an input analog signal.

The invention provides a ground bounce noise suppression circuit and a circuit board, which can be applied to the technical field of circuits. The ground bounce noise suppression circuit includes a capacitor and a diode connected in series between a first ground region and a second ground region of a circuit board, in which a forward conduction path of the diode corresponds to a direction from the first ground region to the second ground region, the reference level fluctuation tolerance of the second grounding area is greater than that of the first grounding area, and the projections of the first grounding area and the second grounding area in the thickness direction of the circuit board are not overlapped.

An optical distance measuring apparatus comprises a laser diode emitting a light pulse, light receiver including a photon-counting light receiver, distance measurement unit including a signal discriminator and propagation estimator, and threshold determiner. The signal discriminator discriminates the signal component, exceeding a threshold, of the signal as a reflected signal resulting from reflection of the light pulse at a measurement object. The propagation estimator estimates a round-trip propagation time of the light pulse to the measurement object using the signal. The threshold determiner sets a boundary level as the threshold, corresponding to a reference level obtained from the signal when the signal discriminator determines the reflected signal, using the relationship between the reference and the boundary level. The reference level is obtained from the average value of a noise probability distribution in the signal. The boundary level represents a predetermined cumulative probability in the noise probability distribution.

The invention belongs to the technical field of integrated circuit design, and particularly discloses a low-delay sampler structure and method for high-speed data processing, and in a pseudo reset stage, an unlocking network module and a pre-latching network module are connected in parallel to form an equivalent low-impedance network unit; the transconductance module is used for inputting a sampling signal and a reference level signal and driving the equivalent low-impedance network unit; the pre-latch network module is used for enabling an output node of the pre-latch network module to start charging and discharging according to a sampling signal and a reference level signal and pre-sampling the sampling signal; meanwhile, in the latching stage, the transconductance module is used for driving the pre-latching network module to preliminarily amplify the sampling signal, and the strong latching network module is used for stably latching the sampling signal under the driving of the pre-latching network module. According to the invention, the sampling delay of the signal is obviously shortened, and meanwhile, the requirement of high-speed data processing on the time sequence progress is met.

A transmitter includes an analog transmission circuit, a power amplifier, a voltage detector, a comparator, and a control circuit. The analog transmission circuit is configured to provide a first gain to a first analog signal, so as to generate a second analog signal. The power amplifier is configured to provide a second gain to the second analog signal, so as to generate an output signal to an antenna. The voltage detector is configured to detect a voltage level of the second analog signal. The comparator is configured to generate an indication signal according to the voltage level and a reference level. The control circuit is configured to adjust the first gain of the analog transmission circuit according to the indication signal.

The present invention discloses a terminal impedance matching adjustment system. The impedance matching network inputs an impedance matching target value and an impedance matching control signal, and adjusts the magnitude of the parallel resistor in the impedance matching network according to the impedance matching control signal to match the target value, thereby realizing the impedance adjustment function. The high-speed comparator compares the impedance matching state level with the reference level generated by the voltage division module, and outputs the comparison result to the impedance matching control signal generation module. The impedance matching control signal generation module generates a comparator control signal to the high-speed comparator, generates an impedance matching control signal to the impedance matching network and the port driver circuit, and generates a latch signal to output to the port driver circuit. The port driver circuit adjusts its own impedance according to the impedance matching control signal and the latch signal to achieve the expected impedance matching effect. The present invention can realize two impedance matching adjustment modes, namely manual and automatic, has high flexibility and applicability, and can be widely applied to various transmission line terminal devices.

A magnetic resonance examination method comprises acquisition of a set of magnetic resonance signals from magnetic spins in an object by way of a receiver antenna, the magnetic resonance signals' signal levels are related to an independent reference level that is independent of the receiver antenna's sensitivity to form a calibrated signal level of the magnetic resonance signals, the calibrated signal levels are recorded in terms of a relative density of ordered transverse spins (DOTS). The independent reference level may be derived from the signal-to-thermal-noise ratio. The calibrated signal level in terms of DOTS in μM / T reflects predominantly a tissue property (of (a voxel of) the patient to be examined) as well as details or characteristics of the acquisition sequence used.

The present invention provides a bidirectional level converter and electronic equipment, relating to the technical field of analog integrated circuits. The bidirectional level converter includes: a first port, a second port, and a conversion circuit arranged between the first port and the second port; the first port includes a first input / output port and a first reference level port; the second port includes a second input / output port and a second reference level port; the conversion circuit includes: a first Schmitt comparator, a clamping circuit, a pull-up module, a pull-down module, and a second Schmitt comparator. The present invention provides a bidirectional level converter and electronic equipment, which can achieve that when the input signal is converted from high to low, the input stage does not require a particularly strong driving capability, the input and output are in an isolated state, and the load size of the output stage has no effect on the driving capability of the input stage, which is conducive to maintaining signal integrity, is more flexible in system design, and can adapt to more application scenarios.

According to the zero-delay CT SDM excessive loop delay compensation method, the feedback coefficient of loop delay compensation can be adjusted by changing the specific value of different sampling capacitors in a switched capacitor network, the reference level of an embedded quantizer is used for adjusting the gain of the quantizer, the number of ports, connected to the reference level, of a comparator in the Flash quantizer is reduced, and meanwhile the power consumption of the Flash quantizer is reduced. The power consumption of the comparator can be effectively reduced, and the whole circuit is simple in structure and has zero delay.

The invention relates to the technical field of AC power supply controller detection, and discloses a detection system and method for an AC power supply controller, and the system comprises a signal conditioning module which is used for reducing a high-voltage AC signal to a level suitable for a detection circuit through resistor voltage division or optocoupler isolation when the AC power supply controller is in an operation state, a filter circuit is adopted to eliminate high-frequency noise so as to obtain a comparison signal; and the jump setting module is used for connecting the comparison signal to the positive end of the high-speed comparator and setting the reference level to be connected to the negative end, so that the output state of the high-speed comparator jumps when the comparison signal input into the high-speed comparator reaches or passes through the reference level. The high-speed comparator and the microcontroller are used for timing each zero crossing moment, the periodic delay problem can be recognized through two-stage judgment in a single period or a small number of periods, fault hidden dangers can be found in advance without long monitoring time, and the response time from problem occurrence to abnormal judgment and repair reporting is shortened.

The invention discloses a broadband intermediate-frequency processing circuit and a control method thereof, and relates to the technical field of electronic measurement, the broadband intermediate-frequency processing circuit comprises double intermediate-frequency channels, the broadband intermediate-frequency channel is 307.2 MHz, the narrowband intermediate-frequency channel is 288MHz, and an intermediate-frequency conditioning circuit comprises a change-over switch, a broadband filter, a narrowband filter and five amplifiers. The method can be applied to the frequency spectrograph in different working modes, and intermediate frequency signal paths corresponding to the broadband are provided; different intermediate frequency channel gains are provided for the frequency spectrograph under different reference levels, a low-power-consumption mode of the system is realized through enabling control of the amplifier, and the requirements under different applications are met.

The present invention provides a power adaptive link allocation front-end receiving component, which mainly includes a front-end radio frequency circuit module, a detection signal operation circuit module, a radio frequency signal amplification circuit module, and an output power adjustment circuit module. A large-dynamic detector is used to detect the signal of the radio frequency receiving front-end to obtain a power-related level signal, and then the level signal is amplified by an operational amplifier. Then, according to the reference level set for radio frequency signals with different powers, the control level of the single-pole triple-throw switch in the subsequent circuit is automatically converted, and then different back-end signal processing links are selected to complete the signal processing function of the front-end receiving component, and finally the adaptive allocation feature of the receiving front-end is realized. The present invention can realize adaptive link allocation according to the magnitude of the radio frequency input power, and has the advantages of adaptive implementation, large dynamic range, high detection sensitivity, etc.

The application relates to the technical field of integrated circuit signal detection, and provides a baud rate signal detection circuit and a CDR loop structure which are composed of two data samplers, one error sampler and a digital logic circuit, can provide better jitter performance compared with a traditional MMPD, do not need to depend on accurate reference level VRFE amplitude setting, and have relatively lower design difficulty compared with traditional designs. In addition, the signal detection circuit can also detect the frequency deviation between input data and a sampling clock, so that the baud rate CDR function with a wide frequency capture range can be realized by using only a single control loop without increasing additional clock and sampling circuits, external reference clocks are not needed, the difficulty of the performance and cost compromise mentioned above can be greatly reduced, and the overall design cost is greatly reduced.

The application discloses a kind of digital quantity output control's fault identification system and method, the first control unit in the digital quantity output control device in the system, output pin reference level and periodic communication data are sent to the second control unit in the digital quantity output control device, the second control unit, the output pin actual level of first control unit is acquired, whether the pin output fault of first control unit exists according to output pin reference level and output pin actual level judges, realize the detection of pin damage, and, whether the running fault of first control unit exists according to the periodic communication data received judges, realizes the fault detection of the control unit in the digital quantity output control device.The system realizes the fault identification of digital quantity output control, improves the security of digital quantity output control, guarantees the normal operation of the controlled external equipment.

The application discloses a double residual quantization method and application for a multi-stage analog-to-digital converter, the multi-stage analog-to-digital converter comprising a front-stage quantizer, an inter-stage amplifier and a back-stage quantizer; the front-stage quantizer performs preliminary quantization on an input signal and generates a quantization result; two residual signals are generated at the output end of the front-stage quantizer based on the quantization result; the two residual signals contain quantization error information of the front-stage quantizer and reference level information of the front-stage quantizer; the two residual signals are transmitted to the back-stage quantizer after being amplified by the inter-stage amplifier; the back-stage quantizer is designed as a delta-sigma modulator; the back-stage quantizer directly quantizes the quantization error of the front-stage quantizer through the two residual signals; and the reference level information of the front-stage quantizer is introduced into a converted signal according to the conversion result of the back-stage quantization, and is used for updating a back-stage loop filter. The application maintains the robustness of the inter-stage gain error, and realizes high-precision, high-speed and high-energy-efficiency analog-to-digital conversion performance.

A switching power converter includes: a power stage circuit for converting an input voltage to an output voltage by switching an inductor with a synchronous or an asynchronous mode; an error amplifier to generate an error amplified signal; a modulation comparator for generating a primary modulation signal by comparing the error amplified signal and a ramp signal; a pulse skipping comparator for generating a pulse skipping control signal by comparing the error amplified signal and a skipping reference signal; and a switching control unit for masking the primary modulation signal by the pulse skipping control signal. During the synchronous mode, the skipping reference signal has a predetermined reference level. At the beginning after the synchronous mode is changed to the asynchronous mode, the skipping reference signal turns to the predetermined reference level superposing a compensation reference level, and subsequently the skipping reference signal gradually returns to the predetermined reference level.

The utility model discloses an electrocardio analog signal acquisition circuit for a teaching experiment, which comprises an instrument amplification circuit, a first-stage amplifier, a second-stage amplifier, a first-stage amplifier, a second-stage amplifier, a second-stage amplifier, a first-stage amplifier, a second-stage amplifier and a third-stage amplifier, the band-pass filter circuit comprises an operational amplifier and a resistance-capacitance combination formed by a plurality of capacitors and resistors, and the resistance-capacitance combination formed by the plurality of capacitors and resistors is connected with the operational amplifier; the low-pass filter circuit comprises an operational amplifier and a resistance-capacitance combination formed by a plurality of resistors and capacitors, and the different resistance-capacitance combinations formed by the plurality of resistors and capacitors are connected with the operational amplifier; the level raising circuit comprises a multi-way switch and different resistor combinations, the bias level of an input signal is adjusted through a voltage dividing network, the reference level of a preceding-stage signal is raised to a direct-current level range suitable for subsequent processing, and by arranging an adjustable resistor and capacitor network, collection and conditioning of an electrocardio analog signal are achieved.

A successive approximation analog-to-digital conversion circuit and a method of operating the same are disclosed. The successive approximation analog-to-digital conversion circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The plurality of latch circuits are coupled to the comparator circuit and are serially connected to each other. The plurality of latch circuits are sequentially triggered to store comparator outputs of the comparator circuit in response to a plurality of trigger signals, respectively, and to generate a digital signal accordingly. A first latch circuit and a second latch circuit of the plurality of latch circuits are triggered in response to a first trigger signal and a second trigger signal of the plurality of trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal based on the comparator output stored in the first latch circuit. The successive approximation analog-to-digital conversion circuit is capable of providing more time margin for a settling time of a digital-to-analog converter.

The invention provides a configurable oscillator circuit. The consistency of the output frequency precision of the oscillator is mainly improved. The scheme of the invention comprises a reference level generation circuit, a triangular wave generation circuit, a frequency selection circuit, a frequency calibration circuit, a comparator circuit and a logic circuit. The reference level generation circuit provides a reference level for the comparator and the frequency calibration circuit; the triangular wave generating circuit charges and discharges a capacitor by adopting a charging branch and a discharging branch to generate a triangular wave, and compares the triangular wave with a reference level of a comparator to generate a square wave clock; the frequency selection circuit can configure charging and discharging branch current through a control signal to realize selection of one-time frequency and two-time frequency output by the oscillator; and the frequency calibration circuit can realize fine adjustment of charging and discharging current through a control signal, so that oscillator frequency drift caused by process processing errors is eliminated. The configurable oscillator circuit designed by the invention has the advantages of high output precision, flexible configuration and the like.

The present invention relates to the field of modular integrated circuits, and particularly to an aviation ARINC429 bus receiving and decoding circuit system. It includes: an input overvoltage protection unit, a common-mode rejection unit, a linear difference and attenuation unit, an anti-self-excitation unit, a reference level unit, and a comparison decoding and output unit. The input overvoltage protection unit is used to eliminate interference signals such as bus overshoot interference and electrostatic shock; the common-mode rejection unit can provide a reference zero potential in case of transmission line ground fault, reduce common-mode interference, and provide a signal loop; the linear difference and attenuation unit converts the bus bipolar differential-ended zeroed signal into a single-ended signal. This circuit adopts an overvoltage protection unit, a common-mode rejection unit, and a comparison decoding and output unit, eliminates bus overshoot interference and electrostatic shock interference signals, reduces common-mode interference, and the comparison decoding and output unit realizes hysteresis comparison, reduces the interference caused by signal glitches, and improves the reliability of aviation bus signal transmission.

The invention belongs to the field of visual inspection, and provides a high-precision phase unwrapping method based on stripe level correction, which is used for solving the problems of the existing time phase unwrapping method and space phase unwrapping method. The method comprises the following steps: firstly, processing an image acquired by a camera to obtain single-frequency and high-frequency wrapped phases, and simultaneously completing defect area identification; a high-frequency wrapped phase is unwrapped by adopting a space phase unwrapping method, and the fringe order is inversely calculated; carrying out single-frequency wrapped phase expansion to calculate a reference level, and carrying out symbol correction on a stripe level in a defect area; and finally, the order difference of the unwrapping result of the reference phase and the space phase is calculated, the stripe order after superposition correction is used as the real order of the defect area, the stripe order is used as the real order of the non-defect area, and the phase unwrapping result is calculated according to the real order. According to the method, the robustness of phase unwrapping to a defect area is improved through stripe level correction, and high-frequency stripes are unwrapped with high precision under the condition that the number of projection frames is not increased.

A wearable device comprises at least one processor, memory storing instructions, a plurality of microphones, and a speaker. The instructions that, when executed by the at least one processor individually or collectively, cause the wearable device to: execute an ambient sound function, perform a measurement with respect to a sound of an ambient environment of a user using a first outer microphone, refrain from performing a measurement with respect to the sound of the ambient environment of the user using a second outer microphone, obtain sound data according to the measurement performed using the first outer microphone, in accordance with a level of the sound data less than or equal to a reference level, output a sound of the ambient environment based on the sound data, and in accordance with the level of the sound data greater than the reference level, perform the measurement using the second outer microphone.

The invention relates to the technical field of radar signal processing, in particular to a self-adaptive distributed radar intermittent sampling and forwarding interference resisting method, which is used for accurately and stably detecting a real target when encountering intermittent sampling and forwarding interference and comprises the following steps of: performing signal-level interference alignment processing through echoes of a plurality of receiving stations; and realizing intra-pulse coherent-level intermittent sampling forwarding interference cancellation fusion processing and optimization under the optimal site combination by adopting a simulated annealing-particle swarm search sequence optimization algorithm. According to the method provided by the invention, by virtue of the characteristics of high power gain of intermittent sampling and forwarding interference and high correlation of homologous interference radiation, the adaptive distributed radar intermittent sampling and forwarding interference resisting method provided by the invention has relatively good robustness in the environment of resisting different types of intermittent sampling and forwarding interference and different interference-to-signal ratios; and the target accurate detection capability in an information battlefield confrontation environment is improved.

The invention relates to the technical field of microwaves and millimeter waves, in particular to an over-temperature self-protection circuit for a high-power assembly. The over-temperature self-protection circuit for the high-power component comprises a temperature sensing circuit, a reference circuit and a comparison circuit, wherein the temperature sensing circuit is used for converting a temperature signal into a voltage signal VSIG; the reference circuit is used for providing a reference level signal VREF to determine a judgment threshold; the comparison circuit is used for comparing the voltage signal VSIG with the reference level signal VREF; the logic circuit is used for performing AND logic operation on the high and low levels and an original control signal of the high-power device; the comparison circuit is electrically connected with the temperature sensing circuit, the reference circuit and the logic circuit. When it is detected that the temperature in the high-power assembly exceeds a threshold value, a control signal can be generated to rapidly turn off a high-power device without intervention of a high-power system, and self-protection of the high-power assembly during overtemperature is achieved.

A computer-implemented method of processing an audio signal. The method comprises: receiving from two or more microphones, respective audio signals; deriving a plurality of time-frequency signals from the received audio signals, indexed by frequency, and for each of the time-frequency signals: determining in-beam components of the audio signals; and performing post-processing of the received audio signals, the post-processing comprising: computing a reference level based on the audio signals; computing an in-beam level based on the determined in-beam components of the audio-signals; computing a post-processing gain to be applied to the in-beam components from the reference level and in-beam level; and applying the post-processing gain to the in-beam components.

A switching power converter includes: a power stage circuit for converting an input voltage to an output voltage by switching an inductor with a synchronous or an asynchronous mode; an error amplifier to generate an error amplified signal; a modulation comparator for generating a primary modulation signal by comparing the error amplified signal and a ramp signal; a pulse skipping comparator for generating a pulse skipping control signal by comparing the error amplified signal and a skipping reference signal; and a switching control unit for masking the primary modulation signal by the pulse skipping control signal. During the synchronous mode, the skipping reference signal has a predetermined reference level. When the synchronous mode is changed to the asynchronous mode, the skipping reference signal turns to the predetermined reference level superposing a compensation reference level, and subsequently the skipping reference signal gradually returns to the predetermined reference level.