132results about "Voltage/current interference elimination" patented technology

To provide a new shift register.SOLUTION: One aspect of the invention comprises a transistor 101, a transistor 102, a transistor 103 and a transistor 104. A first terminal of the transistor 101 is connected to a wire 111, and a second terminal of the transistor 101 is connected to a wire 112. A first terminal of the transistor 102 is connected to a wire 113, and a second terminal of the transistor 102 is connected to the wire 112. A first terminal of the transistor 103 is connected to the wire 113, and a gate of the transistor 103 is connected to the wire 111 or the wire 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103 and a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.SELECTED DRAWING: Figure 10

The application provides an inhibitor circuit, a signal sending device and a communication system, and relates to the field of digital information transmission.The inhibitor circuit provided by the application comprises a first transistor and a second transistor, a first switch, a second switch and a first voltage generation module.When communication ends, the first switch and the second switch are closed, and the first transistor and the second transistor are turned on.When the signals on the first communication bus and the second communication bus reach a common mode state, the first switch and the second switch are turned off.The application further provides an inhibitor circuit which adds an additional path on the basis of the above inhibitor circuit.The application further provides a signal sending device which comprises the above inhibitor circuit.The application further provides a communication system which comprises the above signal sending device.The inhibitor circuit, the signal sending device and the communication system provided by the application can reduce the amplitude of tailing overshoot and ensure accurate decoding at the receiving end.

The application relates to the technical field of integrated circuit design, in particular to an inverter chain circuit shielding SET pulse signals and a module packaged based on the inverter chain circuit shielding SET pulse signals. The inverter chain is constructed based on a three-stage inverter structure, which not only has the basic function of an inverter, but also has the outstanding ability of shielding SET pulse signals through reasonable circuit design, can shield voltage jump in any direction, and ensures that the output node o3 can still output with correct logic state.

A level shifter having: an input configured to receive an input signal, an output configured to provide an output signal, a voltage rail configured to provide a rail voltage, at least two diodes including a first and second diode connected in series between the voltage rail and the input, at least three switches, and a capacitor. The at least three switches include a first switch coupled between the voltage rail and the output of the first diode, a second switch coupled between the voltage rail and the output of the second diode, and a third switch coupled between the voltage rail and the input. The capacitor is coupled between the output of the second diode and ground.

A signal generator circuit is provided. The gate of a first transistor and the drain of a second transistor are coupled to a first output terminal. The sources of the first and second transistors are coupled to a first power terminal. The drains of the first and third transistors, and the gate of the second transistor are coupled to a second output terminal. The gate of the third transistor is coupled to a second power terminal. The source of the third transistor is coupled to a third power terminal. A fourth transistor is coupled to the second power terminal and the first output terminal. When the third transistor is turned off, a first bias circuit turns on the fourth transistor. A second bias circuit provides a first predetermined voltage to the second transistor. A third bias circuit provides a second predetermined voltage to the first transistor.

The invention provides a high-voltage level shift circuit with high dVdt suppression capability, which is used for converting a signal in a low-voltage domain into a signal in a high-voltage domain and comprises an encyclopedia level shift module, a PMOS (P-channel Metal Oxide Semiconductor) coupling module, a noise current elimination module, a current compensation module, a transmission gate module and an RS (Reed-Solomon) latch module, the level shift module is used for transmitting signals from a low-voltage domain to a high-voltage domain, the PMOS coupling module is used for converting voltage signals transmitted by the level shift module into current signals, accelerating signal transmission and preventing common-mode signals from passing through, and the noise current elimination module is used for mirroring current, accelerating signal transmission and counteracting common-mode noise induction current. The current compensation module is used for compensating the current of a node, the transmission gate is used for transmitting a signal output by the noise elimination module to the RS latch, the RS latch module is used for recovering an edge narrow pulse signal into a square signal, and according to the scheme, the dV / dt noise suppression capability of the circuit is enhanced while low power consumption and low delay are achieved.

[0006] It is an object to provide a quantum computing system and arrangement. According to one embodiment, a qubit has a ground state and a plurality of excited states, the plurality of excited states including a lowest excited state, an energy difference between the ground state and the lowest excited state corresponds to a first frequency, an energy difference between the lowest excited state of the plurality of excited states and another excited state corresponds to a second frequency, an energy dissipation structure is configured to dissipate energy transferred to the energy dissipation structure, and a filter has a stopband and a passband, the filter is coupled to the qubit and the energy dissipation structure, the stopband includes the first frequency and the passband includes the second frequency. [0007] An arrangement, quantum computing system, and method are provided.

A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.

This invention discloses a highly reliable protection and locking circuit capable of withstanding single-particle transients, belonging to the field of satellite power technology. Its key feature is that it includes at least: a trigger module that receives a signal Pro. SET Amplitude and time signals, Pro SET Amplitude and time signals with reference V REF The system compares data and outputs a trigger signal; a locking module receives the trigger signal and outputs an instruction on whether to execute the locking signal based on the trigger signal; a reset module sends a reset instruction to the locking module. This system is suitable for protection circuit design in medium and high orbit space power controllers or in high-radiation ground environments, and has the advantages of good radiation resistance, high reliability, and stable operation.

Disclosed is a spike neural network circuit according to an embodiment of the present disclosure, which includes a self-correcting control circuit that generates an input signal and a first control code, a bias voltage generation circuit that generates a first bias voltage based on the first control code, a synaptic circuit including a first synaptic column that performs an operation of the input signal and a first weight signal and generates a first operation signal, a neuron circuit including a first neuron that generates a first output signal based on a comparison of the first operation signal and a threshold voltage, and a spike comparison circuit that generates a first comparison signal corresponding to a difference between the first output signal and a reference number, and the self-correcting control circuit further generates a second control code for correcting the first bias voltage.

The present disclosure provides a digital display control buffer circuit and a digital display control buffer apparatus. The digital display control buffer circuit at least includes a glitch removal circuit, a first comparison unit, a second comparison unit and a first switch device; a first end of the first switch device and a first input end of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit, a first input end of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit; the glitch removal circuit is used to output a control signal to the control end of the first switch device when a first signal outputted by the output end of the second comparison unit is a falling edge, such that the first switch device is turned off.

The application discloses a digital processing circuit, comprising a logic unit, at least one combinational logic device, the combinational logic device comprising at least one input terminal; a filter unit is used to divide the waveform of the received initial input signal into at least two segments of waveforms within a cycle of the clock signal of the combinational logic device, and to prevent the back propagation of glitches contained in at least one segment of waveforms, so as to provide a filtered input signal to the input terminal of the combinational logic device. By preventing the back propagation of the glitches contained in at least one segment of waveforms in the initial input signal through the filter unit, the application can eliminate the influence of the glitches in the signal on the power consumption of the entire circuit in time, so as to effectively reduce the additional power consumption caused by the glitches.

A circuit includes a first transistor having a control terminal and includes a predriver having an input and an output. The output is coupled to the control terminal of the first transistor. A second transistor of a first polarity has a control terminal coupled to the output of the predriver. A third transistor of a second polarity has first and second terminals. The first terminal of the third transistor is coupled to the control terminal of the second transistor. A fourth transistor having the second polarity has first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the third transistor. The second terminal of the fourth transistor is coupled to a supply terminal.

The application provides a level shift circuit based on current compensation, a low-voltage pulse signal is connected to a first level input end and a second level output end respectively, so that the two low-voltage pulse signals are converted into two high-voltage pulse signals, and the high-voltage pulse signals are output to a current compensation circuit and a common mode noise elimination circuit through a first level output end and a second level output end; the output of the current compensation circuit and the common mode noise elimination circuit jointly influences the signal state of R end and S end in a latch, and the latch is used for restoring the high-voltage pulse signal into a floating square wave signal with the same phase as the input signal. The application not only can resist high common mode noise, but also has a good inhibitory effect on differential mode noise, and effectively improves the stability and reliability of the level shift circuit.

Embodiments of the present disclosure relate to reverse body biasing of a transistor using a photovoltaic source. A metal-oxide-semiconductor (MOS) transistor has a source terminal, a drain terminal, a gate terminal, and a body terminal. The source terminal is connected to receive a supply voltage, and the body terminal is connected to receive a reverse body bias voltage. A photovoltaic circuit has a first terminal connected to the source terminal of the MOS transistor and a second terminal connected to the body terminal of the MOS transistor. The photovoltaic circuit converts photons received from the environment to generate the reverse body bias voltage.

A transfer circuit includes a high voltage level transfer circuit and a latch circuit. The high voltage level transfer circuit has a first input terminal and a second input terminal, and a first output terminal and a second output terminal. The latch circuit receives the first output terminal and the second output terminal of the high voltage level transfer circuit, and outputs a signal. When the first input terminal receives a first pulse signal, the high voltage level transfer circuit outputs a low pulse signal at the first output terminal to the latch circuit, so that the latch circuit outputs a signal latched as high. When the second input terminal receives a second pulse signal, the high voltage level transfer circuit outputs a low pulse signal at the second output terminal to the latch circuit, so that the latch circuit outputs a signal latched as low.

An exemplary setup includes: a rectifier circuit arrangement comprising: a first resistor with one terminal; a second resistor with one terminal; a first transistor with a first terminal, a second terminal, and a control terminal; and a second transistor with a first terminal, a second terminal, and a control terminal;a reference circuit arrangement comprising a first input, a second input, a third input, a fourth input and an output, wherein the first input of the reference circuit arrangement is coupled to the control terminal of the first transistor, wherein the second input of the reference circuit arrangement is coupled to the terminal of the second resistor and the first terminal of the second transistor, wherein the third input of the reference circuit arrangement is coupled to the control terminal of the second transistor, and wherein the fourth input of the reference circuit arrangement is coupled to the terminal of the first resistor and the first terminal of the first transistor.

A digital frequency divider for a voltage supply circuit of a controller is disclosed. The digital frequency divider has a counting unit which has a clock input for a clock signal, a reset input for a reset signal, and a plurality of outputs for division signals. The counting unit is designed to generate the division signals as a division of the clock signal by a power of 2. The digital frequency divider further has a first coupling circuit for coupling the division signals to form a coupling signal, wherein the coupling signal has a logical HIGH only if all coupled division signals have a logical HIGH; and a second coupling circuit which is designed to enter the coupling signal into the reset input of the counting unit.

The present invention provides a common-mode transient suppression protection circuit for a digital isolator, including a modulation circuit, a demodulation circuit and an isolation capacitor connected between the modulation circuit and the demodulation circuit. The modulation circuit includes a modulation circuit front-end and a drive circuit, which are connected in sequence, and a clamping module is arranged in the drive circuit. The protection circuit further includes a linear voltage regulator structure connected with the drive circuit, and a power supply clamp is arranged in the linear voltage regulator structure. By providing the linear voltage regulator structure having the power supply clamp and the drive circuit having the clamping module in the protection circuit, low-voltage devices in the drive circuit can be protected from being damaged by high-voltage signals generated by common-mode transient interference.

The present disclosure relates to a circuit comprising: —a first timing guard circuit (200) configured to detect when a slack time of a first data signal arriving at a first synchronous device (202) falls below a first threshold (SLG DELAY); and —a second timing guard circuit (200) configured to detect when a slack time of a second data signal arriving at a second synchronous device (202) falls below a second threshold (SLG DELAY), the first and second thresholds being different from each other.

Integrated circuit (IC) including domino logic circuit blocks with nFETs that are implemented in a first device layer and pFET keeper transistors that are implemented in a second device layer. The multiple device layers may be integrated within an IC die through layer transfer. Very low temperature operation (e.g., −25° C., or less) may greatly reduce electrical leakage current from dynamic nodes of the domino logic circuit blocks so that output capacitance of the keeper transistors is sufficient to maintain dynamic node charge levels for good noise margin.

An electronic circuit comprising a latch comprising a first inverter and a second inverter, wherein an output of the first inverter is coupled to an input of the second inverter and an output of the second inverter is coupled to an input of the first inverter; and an output stage comprising a first transistor coupled between a first supply voltage and a first output node, a second transistor coupled between the first output node and ground, a third transistor coupled between a second supply voltage and a second output node, and a fourth transistor coupled between the second output node and ground. The output of the first inverter is coupled to the gate terminals of the first transistor and the fourth transistor. The output of the second inverter is coupled to the gate terminals of the second transistor and the third transistor.

This invention discloses a high-speed digital output circuit and device based on an isolated power supply, comprising an isolated power supply, a high-speed isolation device, a MOS driver, and a MOS transistor. The first port of the isolated power supply is connected to the power supply terminal, the third port of the isolated power supply is connected to the power supply terminal, and the fourth port of the isolated power supply is connected to the second power supply terminal (COM). The third and fourth ports of the isolated power supply are respectively connected to the power distribution terminals of the high-speed isolation device. The first input terminal of the high-speed isolation device is connected to the power supply terminal, the second input terminal of the high-speed isolation device is connected to a current-limiting resistor, and the power distribution terminals of the high-speed isolation device are connected to the third and fourth ports of the isolated power supply. The output terminal of the high-speed isolation device is sequentially connected to the input terminal of the MOS driver and the gate of the MOS transistor. The power supply terminal of the MOS driver is connected to the third port of the isolated power supply, and the output terminal of the MOS driver is connected to the gate of the MOS transistor. The drain of the MOS transistor is connected to the equivalent load and the third power supply terminal. This improves the anti-interference capability of the high-speed digital output device.

A method and system for reducing radiation at predetermined frequencies using delay elements and related devices is disclosed. The device includes an input terminal (102) for receiving a signal (104), a delay element (108) electrically connected to the input terminal, an output terminal (112) for providing a slew rate reduced signal (114), and a combining circuit (116) electrically connected to the delay element and the output terminal. The delay elements provide delayed signals (110) responsive to the received signal. Each of the delayed signals includes a delayed version of the received signal. The combining circuit combines the delayed signals to generate the slew rate reduced signal. The delays associated with the delay elements are selected to reduce radiation at one or more predetermined frequencies of the slew rate reduced signal compared to the received signal.

This disclosure describes pulse width determination in a single-wire bus device. Here, a pulse width determination circuit is configured to determine the pulse width based on a sampling clock. More specifically, the sampling clock may be a half-rate clock with reduced sampling power. Alternatively, the sampling clock may be a full-rate clock with improved sampling accuracy. Given that the pulse and the sampling clock may be asynchronous, the pulse width determination circuit is further configured to mitigate possible sampling errors associated with the rising and / or falling edges of the pulse, thereby improving sampling accuracy. In embodiments, the pulse width determination circuit may be located in one or more slave circuits in the single-wire bus device to determine a synchronization pulse transmitted by the master circuit via the single-wire bus, thereby establishing a timing basis for subsequent communication with the master circuit.

A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.

A digital frequency divider, a voltage supply and a method for operating a monitoring circuit disclose a digital frequency divider (10) for a controller (600) voltage supply circuit (500). The digital frequency divider (10) comprises a counting unit (100) having a clock input (110) for a clock signal (50), a reset input (120) for a reset signal, and a plurality of outputs (130) for a frequency divider signal (Qn). The counter unit (100) is designed to generate a frequency divider signal (Qn) which is divided by power of 2 as a clock signal (50). The digital frequency divider (10) further comprises a first coupling circuit (200) for coupling the frequency divider signal (Qn) into a coupling signal (250), and a second coupling circuit (300) designed to input the coupling signal (250) to the reset input (120) of the counting unit (100), in which only when all the coupled frequency divider signals (Qn) have a logic high, the first coupling circuit (200) and the second coupling circuit (300) are coupled into the reset input (120) of the counting unit (100). The coupling signal (250) has a logic high.

Certain aspects of the present disclosure provide apparatus and techniques for generating a signal for clock spurious attenuation. An example apparatus generally includes one or more circuits coupled between a voltage rail and a reference potential node, where the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delayed signal; and a signal generation circuit coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delayed signal.

The invention relates to an industrial standard digital quantity input device. The device comprises an input circuit, a protection and clamping circuit, a current limiting circuit, a power supply circuit, a hysteresis comparator circuit and a micro-control unit, wherein the input circuit is used for transmitting a digital quantity input (DI) signal to the protection and clamping circuit; the protection and clamping circuit is used for clamping the voltage of the input DI signal within a preset safety range; the current limiting circuit is used for limiting the current of the DI signal passing through the protection and clamping circuit below a preset threshold value; the hysteresis comparator circuit is used for comparing the voltage of the DI signal passing through the current limiting circuit with a reference voltage; the micro-control unit is used for receiving the voltage signal transmitted by the hysteresis comparator circuit and sending the voltage signal to the upper-layer controller; the power supply circuit is used for providing preset voltage for the current limiting circuit, the hysteresis comparator circuit and the micro-control unit. The device has a DI input current control function and a DI signal clamping function, and the stability and the anti-interference performance of the circuit can be improved.

This driver circuit comprises: a differential output circuit (1); a capacitor (C1) that is inserted between the output terminal of the positive phase side of the differential output circuit (1) and the output terminal of the positive phase side of the driver circuit; a capacitor (C2) that is inserted between the output terminal of the negative phase side of the differential output circuit (1) and the output terminal of the negative phase side of the driver circuit; and an offset circuit (2) that applies offset voltages to output signals (Voutp, Voutn) of the driver circuit in such a manner that the difference between the midpoint of the output signal (Voutp) of the positive phase side of the driver circuit and the midpoint of the output signal (Voutn) of the negative phase side thereof is equivalent to or greater than the amplitudes of the output signals (Vp, Vn) of the differential output circuit (1).