419results about "Voltage/current interference elimination" patented technology

A circuit includes a high-side driver having a high-side slew control input, a high-side drive input and a high-side drive output. A low-side driver has a low-side slew control input, a low-side drive input and a low-side drive output. Drive control circuitry has a high-side drive control output, a low-side drive control output, and a slew control output. The high-side drive control output is coupled to the high-side drive input, the low-side drive control output is coupled to the low-side drive input. The slew control output is coupled to at least one of the high-side slew control input and the low-side slew control input, and the drive control circuitry is configured to provide a slew control signal at the slew control output. The high-side and / or low-side driver is configured to modulate a slew rate of a drive signal at a respective drive output thereof based on the slew control signal.

The embodiment of the present application discloses a level shift circuit and a high-voltage half-bridge driver chip. The level shift circuit includes a first and a second high-voltage switch tube, a cross-coupling module and a conversion module; a controlled end of the first high-voltage switch tube; a controlled end of the second high-voltage switch tube; the cross-coupling module includes a first current mirror and a second current mirror; the first and second nodes of the conversion module are respectively connected to the first and second current mirrors through the first and second nodes, to output an output signal.

The present disclosure provides a semiconductor device, which includes a process monitor circuit, a controller, and an output buffer. The process monitor circuit is configured to measure process information of the semiconductor device. The controller is electrically connected to the process monitor circuit, and configured to generate a trimming code based on the measured process information. The output buffer is electrically connected to the controller, and configured to adjust a first bias current and a second bias current based on the trimming code.

The present invention provides a common-mode transient suppression protection circuit for a digital isolator, including a modulation circuit, a demodulation circuit and an isolation capacitor connected between the modulation circuit and the demodulation circuit. The modulation circuit includes a modulation circuit front-end and a drive circuit, which are connected in sequence, and a clamping module is arranged in the drive circuit. The protection circuit further includes a linear voltage regulator structure connected with the drive circuit, and a power supply clamp is arranged in the linear voltage regulator structure. By providing the linear voltage regulator structure having the power supply clamp and the drive circuit having the clamping module in the protection circuit, low-voltage devices in the drive circuit can be protected from being damaged by high-voltage signals generated by common-mode transient interference.

A reconfigurable driver in an I / O circuit has a first transistor provided in a first pullup structure, a second transistor provided in a second pullup structure, and a control circuit that generates a control signal provided to a gate of the second transistor. A gate of the first transistor receives a data signal. The control signal is an inverted, delayed version of the data signal in a first mode. The control signal turns off the second transistor in a second mode. The control circuit generates the control signal using a version of the data signal when operated in a third mode. The second pullup structure may be used to provide one-shot equalization to an output of the reconfigurable driver when the second pullup structure is operated in the first mode. The second transistor may be a thin-oxide PMOS transistor. The first transistor may be a thin-oxide NMOS transistor.

A buffer circuit configured to generate an output voltage according to an input voltage includes: an input stage configured to provide first and second differential currents to a load stage or receive third and fourth differential currents from the load stage based on a difference between the input voltage and the output voltage; a load stage configured to apply gate voltages to first and second output transistors of an output stage based on the first through fourth differential currents; the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors; and a slew rate compensator configured to regulate the gate voltages of the first and second output transistors by providing a source current to the load stage or receiving a sink current from the load stage.

The invention relates to a high-voltage level shift circuit and a layout structure thereof, and the high-voltage level shift circuit comprises a pulse generation module which is used for receiving an input signal and generating a double-path low-voltage domain narrow pulse signal; the level shift module is used for receiving the low-voltage domain narrow pulse signal and converting the low-voltage domain narrow pulse signal into a corresponding double-path high-voltage domain narrow pulse signal; the voltage transient noise detection module is used for detecting voltage transient noise and generating a transient noise intensity signal; the voltage transient noise filtering module is used for filtering voltage transient noise based on the received transient noise intensity signal to generate a double-path high-voltage domain filtering signal; and the RS trigger is used for converting the received high-voltage domain filtering signal into a high-side power device driving signal. The common-mode noise filtering capability and the VS negative bias resisting capability of the voltage transient noise filtering module can be enhanced, the transmission delay of a chip is effectively reduced, and the width of a narrow pulse signal is free of loss in the transmission process, so that the dynamic power consumption is reduced.

The invention provides a control method and device of a radio frequency power supply, the radio frequency power supply and semiconductor process equipment, and is applied to the technical field of semiconductor process equipment, the method is applied to the radio frequency power supply which provides at least one pulse signal in each work period, and in the at least one pulse signal in each work period of the radio frequency power supply, the pulse signal is transmitted to the radio frequency power supply. Wherein one pulse signal is controlled according to a first control mode, and the first control mode is as follows: according to a forward power feedback value, a reflection power feedback value, a dissipation power feedback value and a bus voltage threshold value of a current radio frequency power supply, a bus voltage output to the radio frequency power supply is adjusted, and a bias voltage output to the radio frequency power supply is kept unchanged; compared with a protection circuit built according to electronic components in the prior art, the invention provides a software protection mechanism, the execution process is not easily influenced by factors such as environment temperature and electromagnetic interference, the protection mechanism is more reliable, and the safety of the radio frequency power supply in the operation process can be ensured.

The invention discloses a multi-tube parallel power device phase shift type current sharing and crosstalk suppression drive circuit which is composed of a crosstalk suppression unit, a current balancing unit, a control response unit and a function switching unit. Wherein the crosstalk suppression unit generates a control signal for suppressing the crosstalk voltage of the parallel power device and shields the interference of the current balancing unit; the current balancing unit generates a control signal for balancing the dynamic current of the parallel power device and shields the interference of the crosstalk suppression unit; the control response unit is used for realizing crosstalk active clamping or current active equalization; and the mode switching unit realizes automatic switching of a crosstalk suppression function or a current equalization function according to configuration. Parallel device grid driving signal feedback is introduced, crosstalk voltage active clamping and dynamic current active balancing are achieved through a logic circuit, and the parallel expansibility is high; an exclusive-OR gate is adopted to accurately identify synchronous or asynchronous information of driving signals of the parallel devices, and various different gate sequential modes in parallel application of the hybrid devices can be compatible.

The invention discloses a wide-level-range high-speed level conversion circuit, and relates to the technical field of electronic circuits. A level conversion module in the level conversion circuit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube; a first NMOS tube and a second NMOS tube in the input module are NMOS devices with the voltage grade lower than the device grade corresponding to the main power supply voltage of the chip; the bias voltage generation module is connected with a power supply voltage and is used for generating a bias voltage; the bias voltage is dynamically adjusted along with the change of the power supply voltage; and a signal access selection unit in the input module is respectively connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and is used for controlling the grid electrode to be connected with a bias voltage or a ground potential. The pull-down capability of the level conversion circuit can be adaptively adjusted along with the change of the pull-up capability caused by the change of the main power supply voltage, so that the level conversion circuit can realize high-speed level conversion in a wide level range.

In the present disclosure, a buffer outputs a gate drive signal indicating the same logic level as an element control signal, and an inverting buffer outputs a base drive signal indicating the opposite logic level to the element control signal. The resistance is interposed between the output of the buffer and the gate of an IGBT. A PNP bipolar transistor has its emitter connected to the gate of the IGBT and its collector connected to reference potential. A diode is interposed between the output of the buffer and a base of the PNP bipolar transistor. An output of the inverting buffer is connected to the base of the PNP bipolar transistor through a resistance.

According to the current compensation-based level shift circuit provided by the invention, one path of low-voltage pulse signal is accessed through the first level input end and the second level output end respectively, so that the two paths of low-voltage pulse signals are converted into two paths of high-voltage pulse signals; the signals are output to the current compensation circuit and the common-mode noise elimination circuit through the first level output end and the second level output end, and the output of the current compensation circuit and the output of the common-mode noise elimination circuit jointly influence the signal states of the R end and the S end in the latch. And the latch is used for restoring the high-voltage pulse signal into a floating square wave signal with the same phase as the input signal. The level shift circuit not only can resist high common-mode noise, but also has a good inhibition effect on differential-mode noise, and the stability and reliability of the level shift circuit are effectively improved.

A bidirectional crosstalk suppression driving circuit suitable for a wide bandgap power semiconductor device comprises a push-pull circuit and a crosstalk suppression auxiliary circuit, the push-pull circuit is connected with the crosstalk suppression auxiliary circuit, and the crosstalk suppression auxiliary circuit is connected with a grid electrode and a source electrode of the power semiconductor device. The push-pull circuit is used for generating a driving voltage signal to drive a power semiconductor device. When the power semiconductor device is subjected to positive crosstalk, positive voltage is generated through a negative voltage capacitor in the crosstalk suppression auxiliary circuit, and the influence of negative overvoltage generated on a driving resistor when the positive crosstalk occurs is reduced; when the power semiconductor device is subjected to negative crosstalk, gate equivalent driving impedance is reduced through an RD auxiliary branch in the crosstalk suppression auxiliary circuit, and reverse overvoltage caused by negative crosstalk is reduced. The circuit has compatibility and economical efficiency, and is simple in structure and easy to operate. The method is of great significance in improving the turn-on and turn-off reliability of a power semiconductor device and guaranteeing stable operation of a system.

The embodiment of the invention discloses a level shift circuit and a high-voltage half-bridge driving chip. The level shift circuit comprises a first high-voltage switch tube, a second high-voltage switch tube, a cross coupling module and a conversion module; the controlled end of the first high-voltage switch tube is connected with a setting signal; a reset signal is accessed to the controlled end of the second high-voltage switch tube; the cross coupling module comprises a first current mirror and a second current mirror, first current is connected to the first end of the first current mirror, second current is connected to the first end of the second current mirror, and the first current is larger than or equal to N times of the second current; the first and second of the conversion module are respectively connected with the first and second current mirrors through the first and second nodes, and output signals are output. The level shift circuit can filter common-mode noise so as to ensure the stability of an output signal, a large resistor or capacitor does not need to be arranged, delay is reduced, and the signal transmission speed is increased.

To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.

Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.

The present invention relates to the field of power integrated circuits, and disclosed is a level shift circuit for improving the anti-noise capability of a high-voltage gate driver chip. When a high-voltage domain power rail rises rapidly, a feedback control module detects that common-mode noise is present in a signal transmission path, and outputs a feedback signal to control the load impedance of a level shift branch to be reduced, thereby reducing the amplitude and time of impact of the noise, and filtering out residual noise by a rear-stage filter circuit can ensure that the noise would not cause logic function disorder of a high-voltage domain circuit. Moreover, the time of impact of the noise can be greatly shortened due to the action of a dynamic load structure and the feedback control module, and the noise can be thoroughly filtered out by the rear-stage filter circuit. Therefore, the allowed minimum pulse width of an input signal can be effectively reduced, and a signal transmission delay can be greatly reduced.

A voltage selector includes a first input terminal for receiving a first input voltage, a second input terminal for receiving a second input voltage, an output terminal, a main select circuit and a reference circuit. The main select circuit includes a select unit for outputting a higher input voltage as an output voltage to the output terminal, and an auxiliary unit for pulling up the output voltage to the first input voltage according to a reference voltage when the first input voltage equals to the second input voltage. The reference circuit pulls up the reference voltage according to a higher one of the first input voltage and the second input voltage, and pulls down the reference voltage when the first input voltage equals to the second input voltage and the output voltage is lower than the first input voltage by a threshold voltage.

The present disclosure provides a semiconductor device, which includes a process monitor circuit, a controller, and an output buffer. The process monitor circuit is configured to measure process information of the semiconductor device. The controller is electrically connected to the process monitor circuit, and configured to generate a trimming code based on the measured process information. The output buffer is electrically connected to the controller, and configured to adjust a first bias current and a second bias current based on the trimming code.

The invention discloses an amplitude-adjustable attenuation circuit network for differential signal transmission. The amplitude-adjustable attenuation circuit network is composed of an attenuator I and an attenuator II. Wherein a common-mode feedback circuit is arranged between the attenuator I and the attenuator II. The attenuator I is introduced into an anti-ESD impact module which is composed of an input end back-to-back diode and used for resisting ESD impact. Differential signals at the input end of the attenuator I are subjected to voltage division through fixed resistors RS1 and RS1 < n > and binary weight adjustable resistors RS2 and RS2 < n >, the attenuator II is connected to a transmission channel in parallel, and the differential signals are subjected to further differential mode attenuation through binary weight adjustable capacitors CSp and CSn. The attenuation circuit network dynamically switches attenuation paths through an MOS tube switch matrix, respectively supports attenuation amounts from-1dB to-6dB and from-0.3 dB to-7dB, realizes high stepping precision, finally realizes synchronous attenuation for common-mode and differential-mode voltages, retains differential-mode attenuation of common-mode levels, and optimizes low-frequency amplitude attenuation and high-frequency signal integrity at the same time.

A semiconductor device includes a first conductivity-type substrate, and a cell region including: a second conductivity type deep well; first and second non-deep wells having the second conductivity-type, the first and second non-deep wells being in corresponding first and second portions of the substrate, the first and second portions of the substrate being in the deep well; and first, second, third and fourth transistor-regions. The first and second transistor-regions are correspondingly in the first and second non-deep wells and include first conductivity-type first transistors. The third and fourth transistor-regions are in the third and fourth portions of the substrate which are in the deep well, and include second transistors having the second conductivity-type. The first transistor-region is configured for a first power domain. The second, third and fourth transistor-regions are configured for a second power domain that is different than the first power domain.

To provide a new shift register.SOLUTION: One aspect of the invention comprises a transistor 101, a transistor 102, a transistor 103 and a transistor 104. A first terminal of the transistor 101 is connected to a wire 111, and a second terminal of the transistor 101 is connected to a wire 112. A first terminal of the transistor 102 is connected to a wire 113, and a second terminal of the transistor 102 is connected to the wire 112. A first terminal of the transistor 103 is connected to the wire 113, and a gate of the transistor 103 is connected to the wire 111 or the wire 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103 and a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.SELECTED DRAWING: Figure 10

The present application discloses a digital isolator including a signal transmitting circuit, a signal receiving circuit, and an isolation circuit. The isolation circuit is coupled between the signal transmitting circuit and the signal receiving circuit. The isolation circuit includes a first isolation unit for converting a received input modulation signal into a differential signal and a second isolation unit for providing an output modulation signal in response to receiving the differential signal. The first isolation unit and the second isolation unit have symmetrical circuit structures. By using a fully differential structure and a fully symmetrical structure, the circuit has improved immunity capability, and can suppress common mode transient interference greater than 200 kv / us.

The invention discloses a level shift circuit for subnanosecond transmission delay of a GaN gate driving chip, and relates to the technical field of gallium nitride half-bridge gate driving chips. Based on a traditional level shifting circuit, two auxiliary capacitors are additionally arranged in two pulse control branch nodes of a level shifting main circuit, charge and discharge logic control is achieved through a capacitor control circuit, and the capacitors are actively charged in the signal transmission stage to accelerate node voltage establishment by means of the time sequence characteristic of narrow pulse signals; and in the noise interference stage, rapid discharge is carried out to compensate the voltage drop caused by common-mode noise, and collaborative optimization of the anti-noise capability and the signal transmission efficiency is realized. And efficient and stable operation of the GaN power device under a high-frequency working condition is ensured.

The invention discloses a common-mode noise reduction level shift circuit in the technical field of power supply circuits. The common-mode noise reduction level shift circuit comprises a common-mode circuit module, a voltage stabilization module, an RC delay module, a gate circuit module, a trigger and a phase inverter module, the common-mode circuit module is used for filtering common-mode signals, and electromagnetic interference of the level shift circuit can be reduced by filtering the common-mode signals; the input end of the common-mode circuit module is electrically connected with the output end of the voltage stabilizing module, and the voltage stabilizing module is used for stabilizing the voltage of the input end of the common-mode circuit module, so that the stability of the voltage input into the common-mode circuit module is improved. The common-mode level shift circuit under high transient voltage is arranged to effectively suppress dv / dt noise, so that the noise can be effectively reduced, and the problem of logic errors caused by noise coupling when the high-side ground VS jumps quickly from low voltage to high voltage is effectively solved.

The application provides an inhibitor circuit, a signal sending device and a communication system, and relates to the field of digital information transmission.The inhibitor circuit provided by the application comprises a first transistor and a second transistor, a first switch, a second switch and a first voltage generation module.When communication ends, the first switch and the second switch are closed, and the first transistor and the second transistor are turned on.When the signals on the first communication bus and the second communication bus reach a common mode state, the first switch and the second switch are turned off.The application further provides an inhibitor circuit which adds an additional path on the basis of the above inhibitor circuit.The application further provides a signal sending device which comprises the above inhibitor circuit.The application further provides a communication system which comprises the above signal sending device.The inhibitor circuit, the signal sending device and the communication system provided by the application can reduce the amplitude of tailing overshoot and ensure accurate decoding at the receiving end.

The application relates to the technical field of integrated circuit design, in particular to an inverter chain circuit shielding SET pulse signals and a module packaged based on the inverter chain circuit shielding SET pulse signals. The inverter chain is constructed based on a three-stage inverter structure, which not only has the basic function of an inverter, but also has the outstanding ability of shielding SET pulse signals through reasonable circuit design, can shield voltage jump in any direction, and ensures that the output node o3 can still output with correct logic state.

A level shifter having: an input configured to receive an input signal, an output configured to provide an output signal, a voltage rail configured to provide a rail voltage, at least two diodes including a first and second diode connected in series between the voltage rail and the input, at least three switches, and a capacitor. The at least three switches include a first switch coupled between the voltage rail and the output of the first diode, a second switch coupled between the voltage rail and the output of the second diode, and a third switch coupled between the voltage rail and the input. The capacitor is coupled between the output of the second diode and ground.

Crossbar arrays with reduced disturbance and methods for programming the same are disclosed. In some implementations, an apparatus comprises: a plurality of rows; a plurality of first columns; a plurality of second columns; a plurality of devices. Each of the plurality of devices is connected among one of the plurality of rows, one of the plurality of first columns, and one of the plurality of second columns. The device further comprises a shared end on the plurality of first columns or the plurality of the second columns connecting to the plurality of the devices in the same row or column; the shared end is grounding or holds a stable voltage potential. In some implementations, one of the devices is: a RRAM, a floating date, a phase change device, an SRAM, a memristor, or a device with tunable resistance. In some implementations the stable voltage potential is a constant DC voltage.

The present invention discloses a high-end power control circuit based on digital logic and an anti-interference method. The high-end power control circuit includes a digital trigger module, the output end of the digital trigger module is simultaneously connected to the gates of a first PMOS transistor and a second PMOS transistor, and the control end is connected to the output end of the output driving circuit. At this time, the digital trigger module will use the output signal of the output driving circuit as a clock control signal, so that the digital trigger module is triggered during the rising edge period of the output signal, and thus the output end of the digital trigger module is always in a low level state. The anti-interference method is based on the high-end power control circuit to raise the drain potential of the first LDMOS transistor when the output signal is in the rising edge stage, reducing the noise pulse width. The high-end power control circuit has the advantages of simple structure and small chip volume, and the high-end power control circuit and the anti-interference method more effectively eliminate noise interference.