231results about "Voltage/current interference elimination" patented technology

The embodiment of the present application discloses a level shift circuit and a high-voltage half-bridge driver chip. The level shift circuit includes a first and a second high-voltage switch tube, a cross-coupling module and a conversion module; a controlled end of the first high-voltage switch tube; a controlled end of the second high-voltage switch tube; the cross-coupling module includes a first current mirror and a second current mirror; the first and second nodes of the conversion module are respectively connected to the first and second current mirrors through the first and second nodes, to output an output signal.

A buffer circuit configured to generate an output voltage according to an input voltage includes: an input stage configured to provide first and second differential currents to a load stage or receive third and fourth differential currents from the load stage based on a difference between the input voltage and the output voltage; a load stage configured to apply gate voltages to first and second output transistors of an output stage based on the first through fourth differential currents; the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors; and a slew rate compensator configured to regulate the gate voltages of the first and second output transistors by providing a source current to the load stage or receiving a sink current from the load stage.

The invention discloses a multi-tube parallel power device phase shift type current sharing and crosstalk suppression drive circuit which is composed of a crosstalk suppression unit, a current balancing unit, a control response unit and a function switching unit. Wherein the crosstalk suppression unit generates a control signal for suppressing the crosstalk voltage of the parallel power device and shields the interference of the current balancing unit; the current balancing unit generates a control signal for balancing the dynamic current of the parallel power device and shields the interference of the crosstalk suppression unit; the control response unit is used for realizing crosstalk active clamping or current active equalization; and the mode switching unit realizes automatic switching of a crosstalk suppression function or a current equalization function according to configuration. Parallel device grid driving signal feedback is introduced, crosstalk voltage active clamping and dynamic current active balancing are achieved through a logic circuit, and the parallel expansibility is high; an exclusive-OR gate is adopted to accurately identify synchronous or asynchronous information of driving signals of the parallel devices, and various different gate sequential modes in parallel application of the hybrid devices can be compatible.

The invention discloses a wide-level-range high-speed level conversion circuit, and relates to the technical field of electronic circuits. A level conversion module in the level conversion circuit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube; a first NMOS tube and a second NMOS tube in the input module are NMOS devices with the voltage grade lower than the device grade corresponding to the main power supply voltage of the chip; the bias voltage generation module is connected with a power supply voltage and is used for generating a bias voltage; the bias voltage is dynamically adjusted along with the change of the power supply voltage; and a signal access selection unit in the input module is respectively connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and is used for controlling the grid electrode to be connected with a bias voltage or a ground potential. The pull-down capability of the level conversion circuit can be adaptively adjusted along with the change of the pull-up capability caused by the change of the main power supply voltage, so that the level conversion circuit can realize high-speed level conversion in a wide level range.

In the present disclosure, a buffer outputs a gate drive signal indicating the same logic level as an element control signal, and an inverting buffer outputs a base drive signal indicating the opposite logic level to the element control signal. The resistance is interposed between the output of the buffer and the gate of an IGBT. A PNP bipolar transistor has its emitter connected to the gate of the IGBT and its collector connected to reference potential. A diode is interposed between the output of the buffer and a base of the PNP bipolar transistor. An output of the inverting buffer is connected to the base of the PNP bipolar transistor through a resistance.

A bidirectional crosstalk suppression driving circuit suitable for a wide bandgap power semiconductor device comprises a push-pull circuit and a crosstalk suppression auxiliary circuit, the push-pull circuit is connected with the crosstalk suppression auxiliary circuit, and the crosstalk suppression auxiliary circuit is connected with a grid electrode and a source electrode of the power semiconductor device. The push-pull circuit is used for generating a driving voltage signal to drive a power semiconductor device. When the power semiconductor device is subjected to positive crosstalk, positive voltage is generated through a negative voltage capacitor in the crosstalk suppression auxiliary circuit, and the influence of negative overvoltage generated on a driving resistor when the positive crosstalk occurs is reduced; when the power semiconductor device is subjected to negative crosstalk, gate equivalent driving impedance is reduced through an RD auxiliary branch in the crosstalk suppression auxiliary circuit, and reverse overvoltage caused by negative crosstalk is reduced. The circuit has compatibility and economical efficiency, and is simple in structure and easy to operate. The method is of great significance in improving the turn-on and turn-off reliability of a power semiconductor device and guaranteeing stable operation of a system.

The embodiment of the invention discloses a level shift circuit and a high-voltage half-bridge driving chip. The level shift circuit comprises a first high-voltage switch tube, a second high-voltage switch tube, a cross coupling module and a conversion module; the controlled end of the first high-voltage switch tube is connected with a setting signal; a reset signal is accessed to the controlled end of the second high-voltage switch tube; the cross coupling module comprises a first current mirror and a second current mirror, first current is connected to the first end of the first current mirror, second current is connected to the first end of the second current mirror, and the first current is larger than or equal to N times of the second current; the first and second of the conversion module are respectively connected with the first and second current mirrors through the first and second nodes, and output signals are output. The level shift circuit can filter common-mode noise so as to ensure the stability of an output signal, a large resistor or capacitor does not need to be arranged, delay is reduced, and the signal transmission speed is increased.

The present invention relates to the field of power integrated circuits, and disclosed is a level shift circuit for improving the anti-noise capability of a high-voltage gate driver chip. When a high-voltage domain power rail rises rapidly, a feedback control module detects that common-mode noise is present in a signal transmission path, and outputs a feedback signal to control the load impedance of a level shift branch to be reduced, thereby reducing the amplitude and time of impact of the noise, and filtering out residual noise by a rear-stage filter circuit can ensure that the noise would not cause logic function disorder of a high-voltage domain circuit. Moreover, the time of impact of the noise can be greatly shortened due to the action of a dynamic load structure and the feedback control module, and the noise can be thoroughly filtered out by the rear-stage filter circuit. Therefore, the allowed minimum pulse width of an input signal can be effectively reduced, and a signal transmission delay can be greatly reduced.

A voltage selector includes a first input terminal for receiving a first input voltage, a second input terminal for receiving a second input voltage, an output terminal, a main select circuit and a reference circuit. The main select circuit includes a select unit for outputting a higher input voltage as an output voltage to the output terminal, and an auxiliary unit for pulling up the output voltage to the first input voltage according to a reference voltage when the first input voltage equals to the second input voltage. The reference circuit pulls up the reference voltage according to a higher one of the first input voltage and the second input voltage, and pulls down the reference voltage when the first input voltage equals to the second input voltage and the output voltage is lower than the first input voltage by a threshold voltage.

The present disclosure provides a semiconductor device, which includes a process monitor circuit, a controller, and an output buffer. The process monitor circuit is configured to measure process information of the semiconductor device. The controller is electrically connected to the process monitor circuit, and configured to generate a trimming code based on the measured process information. The output buffer is electrically connected to the controller, and configured to adjust a first bias current and a second bias current based on the trimming code.

The invention discloses an amplitude-adjustable attenuation circuit network for differential signal transmission. The amplitude-adjustable attenuation circuit network is composed of an attenuator I and an attenuator II. Wherein a common-mode feedback circuit is arranged between the attenuator I and the attenuator II. The attenuator I is introduced into an anti-ESD impact module which is composed of an input end back-to-back diode and used for resisting ESD impact. Differential signals at the input end of the attenuator I are subjected to voltage division through fixed resistors RS1 and RS1 < n > and binary weight adjustable resistors RS2 and RS2 < n >, the attenuator II is connected to a transmission channel in parallel, and the differential signals are subjected to further differential mode attenuation through binary weight adjustable capacitors CSp and CSn. The attenuation circuit network dynamically switches attenuation paths through an MOS tube switch matrix, respectively supports attenuation amounts from-1dB to-6dB and from-0.3 dB to-7dB, realizes high stepping precision, finally realizes synchronous attenuation for common-mode and differential-mode voltages, retains differential-mode attenuation of common-mode levels, and optimizes low-frequency amplitude attenuation and high-frequency signal integrity at the same time.

A semiconductor device includes a first conductivity-type substrate, and a cell region including: a second conductivity type deep well; first and second non-deep wells having the second conductivity-type, the first and second non-deep wells being in corresponding first and second portions of the substrate, the first and second portions of the substrate being in the deep well; and first, second, third and fourth transistor-regions. The first and second transistor-regions are correspondingly in the first and second non-deep wells and include first conductivity-type first transistors. The third and fourth transistor-regions are in the third and fourth portions of the substrate which are in the deep well, and include second transistors having the second conductivity-type. The first transistor-region is configured for a first power domain. The second, third and fourth transistor-regions are configured for a second power domain that is different than the first power domain.

To provide a new shift register.SOLUTION: One aspect of the invention comprises a transistor 101, a transistor 102, a transistor 103 and a transistor 104. A first terminal of the transistor 101 is connected to a wire 111, and a second terminal of the transistor 101 is connected to a wire 112. A first terminal of the transistor 102 is connected to a wire 113, and a second terminal of the transistor 102 is connected to the wire 112. A first terminal of the transistor 103 is connected to the wire 113, and a gate of the transistor 103 is connected to the wire 111 or the wire 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103 and a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.SELECTED DRAWING: Figure 10

The present application discloses a digital isolator including a signal transmitting circuit, a signal receiving circuit, and an isolation circuit. The isolation circuit is coupled between the signal transmitting circuit and the signal receiving circuit. The isolation circuit includes a first isolation unit for converting a received input modulation signal into a differential signal and a second isolation unit for providing an output modulation signal in response to receiving the differential signal. The first isolation unit and the second isolation unit have symmetrical circuit structures. By using a fully differential structure and a fully symmetrical structure, the circuit has improved immunity capability, and can suppress common mode transient interference greater than 200 kv / us.

The invention discloses a level shift circuit for subnanosecond transmission delay of a GaN gate driving chip, and relates to the technical field of gallium nitride half-bridge gate driving chips. Based on a traditional level shifting circuit, two auxiliary capacitors are additionally arranged in two pulse control branch nodes of a level shifting main circuit, charge and discharge logic control is achieved through a capacitor control circuit, and the capacitors are actively charged in the signal transmission stage to accelerate node voltage establishment by means of the time sequence characteristic of narrow pulse signals; and in the noise interference stage, rapid discharge is carried out to compensate the voltage drop caused by common-mode noise, and collaborative optimization of the anti-noise capability and the signal transmission efficiency is realized. And efficient and stable operation of the GaN power device under a high-frequency working condition is ensured.

The application provides an inhibitor circuit, a signal sending device and a communication system, and relates to the field of digital information transmission.The inhibitor circuit provided by the application comprises a first transistor and a second transistor, a first switch, a second switch and a first voltage generation module.When communication ends, the first switch and the second switch are closed, and the first transistor and the second transistor are turned on.When the signals on the first communication bus and the second communication bus reach a common mode state, the first switch and the second switch are turned off.The application further provides an inhibitor circuit which adds an additional path on the basis of the above inhibitor circuit.The application further provides a signal sending device which comprises the above inhibitor circuit.The application further provides a communication system which comprises the above signal sending device.The inhibitor circuit, the signal sending device and the communication system provided by the application can reduce the amplitude of tailing overshoot and ensure accurate decoding at the receiving end.

The application relates to the technical field of integrated circuit design, in particular to an inverter chain circuit shielding SET pulse signals and a module packaged based on the inverter chain circuit shielding SET pulse signals. The inverter chain is constructed based on a three-stage inverter structure, which not only has the basic function of an inverter, but also has the outstanding ability of shielding SET pulse signals through reasonable circuit design, can shield voltage jump in any direction, and ensures that the output node o3 can still output with correct logic state.

A level shifter having: an input configured to receive an input signal, an output configured to provide an output signal, a voltage rail configured to provide a rail voltage, at least two diodes including a first and second diode connected in series between the voltage rail and the input, at least three switches, and a capacitor. The at least three switches include a first switch coupled between the voltage rail and the output of the first diode, a second switch coupled between the voltage rail and the output of the second diode, and a third switch coupled between the voltage rail and the input. The capacitor is coupled between the output of the second diode and ground.

The invention discloses a signal state detection circuit based on square wave frequency difference and a detection method thereof.The circuit comprises an XOR gate circuit and a band-pass filter, the first input end of the XOR gate circuit is used for inputting a first square wave signal A, and the second input end of the XOR gate circuit is used for inputting a second square wave signal B; the first square wave signal A and the second square wave signal B are square wave signals with different frequencies, and the output end of the XOR gate circuit is connected with the input end of the band-pass filter. The AND gate circuit not only inherits the advantages of simple structure and easy implementation of a traditional AND gate, but also remarkably enhances the anti-interference capability and safety in the logical operation process by introducing a frequency difference detection mechanism, and effectively avoids logical errors caused by interference. In addition, the invention also has good integration and compatibility, and can be easily integrated into a chip design and expanded into the existing electronic system.

The invention provides a ground bounce noise suppression circuit and a circuit board, which can be applied to the technical field of circuits. The ground bounce noise suppression circuit includes a capacitor and a diode connected in series between a first ground region and a second ground region of a circuit board, in which a forward conduction path of the diode corresponds to a direction from the first ground region to the second ground region, the reference level fluctuation tolerance of the second grounding area is greater than that of the first grounding area, and the projections of the first grounding area and the second grounding area in the thickness direction of the circuit board are not overlapped.

The invention relates to the technical field of transistor driving, in particular to an adaptive variable resistance transistor driving system, which comprises a data acquisition module; the driving analysis module is used for determining whether grid resistance driving needs to be carried out on the current opening process according to the abnormal reference value, and carrying out staged driving or overall driving on the grid resistance according to the Miller plateau time and the change rate fluctuation value when the grid resistance driving is carried out on the current opening process; the stage division module is used for determining whether to perform secondary division on each stage according to the stage comparison value corresponding to each stage; the stage driving module is used for determining grid resistance adjustment aiming at the characteristic pre-adjustment sections or all the pre-adjustment sections according to the number of the pre-adjustment sections and adjusting the grid resistance according to the abnormal degree of section change; and the integral driving module is used for adjusting the grid resistance according to the turn-on stage characterization value. According to the invention, the conduction loss of the transistor can be reduced.

A signal generator circuit is provided. The gate of a first transistor and the drain of a second transistor are coupled to a first output terminal. The sources of the first and second transistors are coupled to a first power terminal. The drains of the first and third transistors, and the gate of the second transistor are coupled to a second output terminal. The gate of the third transistor is coupled to a second power terminal. The source of the third transistor is coupled to a third power terminal. A fourth transistor is coupled to the second power terminal and the first output terminal. When the third transistor is turned off, a first bias circuit turns on the fourth transistor. A second bias circuit provides a first predetermined voltage to the second transistor. A third bias circuit provides a second predetermined voltage to the first transistor.

The invention provides a high-voltage level shift circuit with high dVdt suppression capability, which is used for converting a signal in a low-voltage domain into a signal in a high-voltage domain and comprises an encyclopedia level shift module, a PMOS (P-channel Metal Oxide Semiconductor) coupling module, a noise current elimination module, a current compensation module, a transmission gate module and an RS (Reed-Solomon) latch module, the level shift module is used for transmitting signals from a low-voltage domain to a high-voltage domain, the PMOS coupling module is used for converting voltage signals transmitted by the level shift module into current signals, accelerating signal transmission and preventing common-mode signals from passing through, and the noise current elimination module is used for mirroring current, accelerating signal transmission and counteracting common-mode noise induction current. The current compensation module is used for compensating the current of a node, the transmission gate is used for transmitting a signal output by the noise elimination module to the RS latch, the RS latch module is used for recovering an edge narrow pulse signal into a square signal, and according to the scheme, the dV / dt noise suppression capability of the circuit is enhanced while low power consumption and low delay are achieved.

[0006] It is an object to provide a quantum computing system and arrangement. According to one embodiment, a qubit has a ground state and a plurality of excited states, the plurality of excited states including a lowest excited state, an energy difference between the ground state and the lowest excited state corresponds to a first frequency, an energy difference between the lowest excited state of the plurality of excited states and another excited state corresponds to a second frequency, an energy dissipation structure is configured to dissipate energy transferred to the energy dissipation structure, and a filter has a stopband and a passband, the filter is coupled to the qubit and the energy dissipation structure, the stopband includes the first frequency and the passband includes the second frequency. [0007] An arrangement, quantum computing system, and method are provided.

A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.

This invention discloses a highly reliable protection and locking circuit capable of withstanding single-particle transients, belonging to the field of satellite power technology. Its key feature is that it includes at least: a trigger module that receives a signal Pro. SET Amplitude and time signals, Pro SET Amplitude and time signals with reference V REF The system compares data and outputs a trigger signal; a locking module receives the trigger signal and outputs an instruction on whether to execute the locking signal based on the trigger signal; a reset module sends a reset instruction to the locking module. This system is suitable for protection circuit design in medium and high orbit space power controllers or in high-radiation ground environments, and has the advantages of good radiation resistance, high reliability, and stable operation.

Disclosed is a spike neural network circuit according to an embodiment of the present disclosure, which includes a self-correcting control circuit that generates an input signal and a first control code, a bias voltage generation circuit that generates a first bias voltage based on the first control code, a synaptic circuit including a first synaptic column that performs an operation of the input signal and a first weight signal and generates a first operation signal, a neuron circuit including a first neuron that generates a first output signal based on a comparison of the first operation signal and a threshold voltage, and a spike comparison circuit that generates a first comparison signal corresponding to a difference between the first output signal and a reference number, and the self-correcting control circuit further generates a second control code for correcting the first bias voltage.

The present disclosure provides a digital display control buffer circuit and a digital display control buffer apparatus. The digital display control buffer circuit at least includes a glitch removal circuit, a first comparison unit, a second comparison unit and a first switch device; a first end of the first switch device and a first input end of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit, a first input end of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit; the glitch removal circuit is used to output a control signal to the control end of the first switch device when a first signal outputted by the output end of the second comparison unit is a falling edge, such that the first switch device is turned off.

The application discloses a digital processing circuit, comprising a logic unit, at least one combinational logic device, the combinational logic device comprising at least one input terminal; a filter unit is used to divide the waveform of the received initial input signal into at least two segments of waveforms within a cycle of the clock signal of the combinational logic device, and to prevent the back propagation of glitches contained in at least one segment of waveforms, so as to provide a filtered input signal to the input terminal of the combinational logic device. By preventing the back propagation of the glitches contained in at least one segment of waveforms in the initial input signal through the filter unit, the application can eliminate the influence of the glitches in the signal on the power consumption of the entire circuit in time, so as to effectively reduce the additional power consumption caused by the glitches.

A circuit includes a first transistor having a control terminal and includes a predriver having an input and an output. The output is coupled to the control terminal of the first transistor. A second transistor of a first polarity has a control terminal coupled to the output of the predriver. A third transistor of a second polarity has first and second terminals. The first terminal of the third transistor is coupled to the control terminal of the second transistor. A fourth transistor having the second polarity has first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the third transistor. The second terminal of the fourth transistor is coupled to a supply terminal.