17results about "Voltage/current interference elimination" patented technology

A level shifter having: an input configured to receive an input signal, an output configured to provide an output signal, a voltage rail configured to provide a rail voltage, at least two diodes including a first and second diode connected in series between the voltage rail and the input, at least three switches, and a capacitor. The at least three switches include a first switch coupled between the voltage rail and the output of the first diode, a second switch coupled between the voltage rail and the output of the second diode, and a third switch coupled between the voltage rail and the input. The capacitor is coupled between the output of the second diode and ground.

A circuit includes a first transistor having a control terminal and includes a predriver having an input and an output. The output is coupled to the control terminal of the first transistor. A second transistor of a first polarity has a control terminal coupled to the output of the predriver. A third transistor of a second polarity has first and second terminals. The first terminal of the third transistor is coupled to the control terminal of the second transistor. A fourth transistor having the second polarity has first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the third transistor. The second terminal of the fourth transistor is coupled to a supply terminal.

This disclosure describes pulse width determination in a single-wire bus device. Here, a pulse width determination circuit is configured to determine the pulse width based on a sampling clock. More specifically, the sampling clock may be a half-rate clock with reduced sampling power. Alternatively, the sampling clock may be a full-rate clock with improved sampling accuracy. Given that the pulse and the sampling clock may be asynchronous, the pulse width determination circuit is further configured to mitigate possible sampling errors associated with the rising and / or falling edges of the pulse, thereby improving sampling accuracy. In embodiments, the pulse width determination circuit may be located in one or more slave circuits in the single-wire bus device to determine a synchronization pulse transmitted by the master circuit via the single-wire bus, thereby establishing a timing basis for subsequent communication with the master circuit.

An integrated circuit is provided with a signal node / IO pad in an output buffer that is protected by a current injection protection circuit which includes first and second comparators connected between a first voltage supply and a second voltage supply to generate first and second control signals in response to, respectively, a positive or negative injected current at the signal node, and which also includes a pre-driver stack of transistors which generate, respectively, a positive gate control signal and negative gate control signal, and which also includes a multiplex selection circuit connected to output the positive gate control signal and negative gate control signal to the output buffer to clamp signal node to a first clamped voltage if a voltage on the signal node exceeds the first supply voltage or to a second clamped voltage if a voltage on the signal node falls below the second supply voltage.

A novel shift register is provided. A transistor 101, a transistor 102, a transistor 103, and a transistor A first terminal of the transistor 101 is connected to a wiring 111. The second terminal of the transistor 101 is connected to the wiring 112. The first terminal of the transistor 102 is connected to the wiring 112. The first terminal of the transistor 102 is connected to a wiring 113, and the second terminal of the transistor 102 is connected to a wiring 112. The first terminal of the transistor 103 is connected to the wiring 113, and the gate of the transistor 103 is connected to the wiring 113. The first terminal of the transistor 104 is connected to the wiring 111 or the wiring 119. The second terminal of the transistor 104 is connected to the second terminal of the transistor 103. The gate of transistor 104 is connected to the gate of transistor 102. and is connected.

To form a driving circuit with high withstanding voltage using an element with low withstanding voltage.SOLUTION: A driving circuit 10 is a circuit that drives a high withstanding voltage element Q1 with higher withstanding voltage than a first withstanding voltage, and includes inverters (INVs) 1 to 5 each formed of an element with the withstanding voltage performance with respect to a second withstanding voltage lower than the first withstanding voltage, and first to sixth transistors (FETs) M1 to M6 with higher withstanding voltage than the first withstanding voltage. The FET M1 has a first end to which a first voltage V1 is applied and a second end connected to a driving terminal of the high withstanding voltage element. To the INV I1, a driving signal is input. The FET M2 is connected to the FET M1. The INV I2 is connected to driving terminals of the INV I1 and the FET M1. The INV I3 is connected to the INV I1. The FET M3 is connected to the INV I2. The FET M4 is connected to the FET M3. The FET M5 is connected to the INV I3. The FET M6 is connected to the FET M5. The INV I4 is connected to the FET M6 and the FET M2. The INV I5 is connected to the FET M4 and the INV M4.SELECTED DRAWING: Figure 1

A circuit for transmitting signals in an integrated circuit device is described. The circuit comprises a first die (501), a second die (502) stacked on the first die (501), and a buffer (513) for transmitting data between the first die (501) and the second die (502), wherein a first inverter (512) of the buffer (513) is on the first die (501) and a second inverter (514) of the buffer (513) is on the second die (513). A method for transmitting signals in an integrated circuit device is also described.

An integrated circuit is provided with a signal node / IO pad in an output buffer that is protected by a current injection protection circuit which includes first and second comparators connected between a first voltage supply and a second voltage supply to generate first and second control signals in response to, respectively, a positive or negative injected current at the signal node, and which also includes a pre-driver stack of transistors which generate, respectively, a positive gate control signal and negative gate control signal, and which also includes a multiplex selection circuit connected to output the positive gate control signal and negative gate control signal to the output buffer to clamp signal node to a first clamped voltage if a voltage on the signal node exceeds the first supply voltage or to a second clamped voltage if a voltage on the signal node falls below the second supply voltage.

A driver circuit includes: a differential output circuit; a capacitor inserted between an output terminal on the positive phase side of the differential output circuit and an output terminal on the positive phase side of the driver circuit; a capacitor inserted between an output terminal on the negative phase side of the differential output circuit and an output terminal on the negative phase side of the driver circuit; and an offset circuit for applying offset voltages to output signals of the driver circuit in such a manner that the difference between a midpoint of the output signal on the positive phase side of the driver circuit and a midpoint of the output signal on the negative phase side of the driver circuit becomes equal to or greater than amplitudes of output signals of the differential output circuit.

The present disclosure provides a digital display control buffer circuit and a digital display control buffer apparatus. The digital display control buffer circuit at least includes a glitch removal circuit, a first comparison unit, a second comparison unit and a first switch device; a first end of the first switch device and a first input end of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit, a first input end of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit; the glitch removal circuit is used to output a control signal to the control end of the first switch device when a first signal outputted by the output end of the second comparison unit is a falling edge, such that the first switch device is turned off.

According to one embodiment, a semiconductor device includes a first terminal which is coupled to a first node and to which a control signal is externally input, a first circuit coupled to the first node, configured to switch based on a logic level of the first node between a first state where a first voltage is not output to a second node and a second state where the first voltage is output to the second node, and configured to control a slew rate of an output voltage at a time of switching from the first state to the second state, and a second circuit including a switch circuit which includes one end coupled to the first node and another end applied with a second voltage, and configured to control the switch circuit based on a voltage at the second node.

The application provides a digital display control buffer circuit and a digital display control buffer device. The digital display control buffer circuit comprises at least a deburring circuit, a first comparison unit, a second comparison unit and a first switching device. A first end of the first switching device and a first input end of the second comparison unit are used for inputting an upstream signal of the digital display control buffer circuit. A first input end of the first comparison unit is used for inputting a downstream signal of the digital display control buffer circuit. The deburring circuit is used for outputting a control signal to a control end of the first switching device to make the first switching device off in the case that a first signal output at an output end of the second comparison unit is a falling edge. The circuit solves the problem of long delay of the switching device on the upstream in the process of transmitting the signal from the upstream to the downstream of the digital display control buffer and the generation of glitches.

Embodiments of the present disclosure relate to glitch suppression apparatus and methods. The apparatus includes a primary core processor configured to receive a first signal through a first primary buffer, a second signal through a second primary buffer, a third signal through a third primary buffer, and a fourth signal through a fourth primary buffer; a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer, and the fourth signal through a fourth shadow buffer; and a first glitch suppression buffer coupled to a common node of an input of the first primary buffer and an input of the first shadow buffer.

Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.