20results about "Power consumption reduction" patented technology

Disclosed are a clock divider and a control method thereof, which enable retention work to be smoothly performed by ensuring that an output clock of the clock divider is in a low-level state in a retention signal conversion section. A clock divider according to an embodiment of the present invention comprises: a counter that counts clocks of an input clock and generates a counter output for dividing the input clock; an output clock generator that generates a generated clock edge according to the counter output, thereby generating an output clock divided from an input clock; and the state machine controls the counter according to a clock low level request of the power management unit, so that the output clock is in a low level state in a retention signal conversion interval.

This invention discloses a digital isolator circuit with additional delay, including a transmitter circuit that receives a data input signal and generates first and second transmitter output signals, wherein the second transmitter output signal is a delayed version of the first transmitter output signal. Subsequently, an isolation barrier generates the first and second isolation output signals, causing a receiver circuit to generate a data output signal in response to these isolation output signals. By further incorporating a delay circuit in the transmitter circuit to delay the first transmitter output signal and generate the second transmitter output signal, this invention effectively enhances the received signal at the receiver circuit, maintaining the stability of the common-mode signal and the robustness of data transmission. A pulse carrier modulation mechanism is also employed to effectively reduce power consumption, electromagnetic interference, and signal jitter.

A communication device includes a first device and a second device. The first device includes a transmitting circuit configured to output and transmit a differential signal including a first signal and a second signal to the second device using an input signal and an enable signal. The second device includes a first amplifier configured to receive the differential signal from the first device, a gate circuit configured to gate an output signal of the first amplifier based on a deactivated reset signal, and a count circuit configured to: (1) count a section in which a value of the differential signal is constant based on a clock signal and an output signal of the gate circuit and (2) generate an activated reset signal when the count of the section exceeds a threshold value.

The invention relates to an industrial standard digital quantity input device. The device comprises an input circuit, a protection and clamping circuit, a current limiting circuit, a power supply circuit, a hysteresis comparator circuit and a micro-control unit, wherein the input circuit is used for transmitting a digital quantity input (DI) signal to the protection and clamping circuit; the protection and clamping circuit is used for clamping the voltage of the input DI signal within a preset safety range; the current limiting circuit is used for limiting the current of the DI signal passing through the protection and clamping circuit below a preset threshold value; the hysteresis comparator circuit is used for comparing the voltage of the DI signal passing through the current limiting circuit with a reference voltage; the micro-control unit is used for receiving the voltage signal transmitted by the hysteresis comparator circuit and sending the voltage signal to the upper-layer controller; the power supply circuit is used for providing preset voltage for the current limiting circuit, the hysteresis comparator circuit and the micro-control unit. The device has a DI input current control function and a DI signal clamping function, and the stability and the anti-interference performance of the circuit can be improved.

According to the trimming circuit and the trimming method thereof, the electrical device and the vehicle, through the technical scheme, the fusing state of an internal trimming fuse is controlled according to the trimming input signal based on the trimming module, the trimming control signal is generated according to the fusing state, and the trimming output signal is generated according to the trimming control signal through the output module; according to the trimming circuit, the trimming module is electrically connected to the first enabling line, so that the trimming module is turned on or turned off according to the first enabling signal output by the first enabling line, the trimming module is controlled to be turned off through the first enabling signal when the trimming function is not needed, and the power consumption of the trimming circuit is reduced.

A communication device includes a first device and a second device. The first device includes a transmitting circuit configured to output and transmit a differential signal including a first signal and a second signal to the second device using an input signal and an enable signal. The second device includes a first amplifier configured to receive the differential signal from the first device, a gate circuit configured to gate an output signal of the first amplifier based on a deactivated reset signal, and a count circuit configured to: (1) count a section in which a value of the differential signal is constant based on a clock signal and an output signal of the gate circuit and (2) generate an activated reset signal when the count of the section exceeds a threshold value.

The embodiment of the invention relates to a preset control loop for a PPG LED driver. According to an embodiment, a driver circuit for a light emitter in a photoplethysmography (PPG) system includes a main control loop having an operational amplifier and a transistor configured as a source follower. During the preset control stage, the preset circuit sets the output voltage of the operational amplifier to be a preset level. The switching circuit activates the preset circuit in a preset phase and activates the main control loop in a main control phase. Before the main control loop is activated, the preset circuit pre-regulates the gate voltage of the source follower transistor to be close to its threshold voltage. This improves startup performance by reducing delay and uncontrolled initial current while avoiding the need for amplifier trimming. The circuit can realize fast stabilization time and accurate control of short current pulse at a very low duty ratio, and is beneficial to PPG measurement accuracy and power efficiency in wearable health care monitoring equipment.

The invention provides a selectable boost circuit applied to an intelligent low-side switch chip, the intelligent low-side switch chip comprises a pin IN, a power tube and a voltage change rate control module respectively connected with the pin IN and the power tube, and the selectable boost circuit comprises a selectable voltage multiplication module which is provided with an input end and an output end, the input end is connected to a pin IN of the intelligent low-side switch chip, and the output end is connected to the voltage change rate control module; and the selectable voltage multiplication module is used for detecting an input voltage value of the pin IN, performing boost control based on the input voltage value to obtain a target voltage, and outputting the target voltage to the power tube so as to enable the internal resistance of the power tube to be smaller than a preset threshold value, thereby remarkably reducing the switching loss and improving the efficiency and reliability of the intelligent low-side switching chip.

A digital isolator module having additional delay path is provided, comprising a transmitter circuit receiving a data input signal and generating a first and second transmitter output signal. The second transmitter output signal is a delay signal of the first transmitter output signal. An isolation barrier is then configured, accordingly developing a first and second isolated output signal. And a receiver circuit accordingly generates a data output signal in response to the first and second isolated output signals. By employing a delay circuit in the disclosed transmitter circuit for delaying the first transmitter output signal and generating the second transmitter output signal, receiving signals at the receiver input terminal can be enhanced, robustness of data transmission is greatly improved and common mode voltage instability is suppressed. A pulse carrier modulation technique is further developed in the disclosed digital isolator module for reducing power consumption, electromagnetic interferences and jitter disturbance.

The application relates to the chip technical field, in particular to a low-power-consumption asynchronous handshake circuit and an asynchronous circuit, the asynchronous handshake circuit comprising a first flip-flop, a second flip-flop and a third flip-flop; a clock port of the first flip-flop is used for receiving a single pulse signal generated based on a first clock, a data port of the first flip-flop is connected with vdd, and an output port of the first flip-flop is connected with a data port of the second flip-flop; an output port of the second flip-flop is connected with a data port of the third flip-flop, and a clock port of the second flip-flop and an output port of the third flip-flop are both connected with a second clock; if the first flip-flop is an asynchronous low-level effective reset port, the asynchronous handshake circuit further comprises an inverter, an output port of the third flip-flop is connected with a data port of the inverter, and an output port of the inverter is connected with a reset port of the first flip-flop. The application reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit.

An apparatus and method of generating an output transmit signal, comprising generating a first portion of an output transmit signal (TXo) based on an input transmit signal (TXi), where the first portion (TXo1) of the output transmit signal comprises a first set of pulses each spanning a unit interval (UI); generating a second portion (TXo2) of the output transmit signal based on the input transmit signal, wherein the second portion of the output signal comprises a second set of pulses each spanning an intermediate sub-interval of the UI; and combining the first portion with the second portion to generate an output transmit signal.

A leakage compensation circuit (1101), a crystal oscillator circuit, and a microprocessor chip (1100). The leakage compensation circuit (1101) comprises: an IO module (100); a leakage compensation module (200), which comprises a source follower transistor (210) and a leakage current mirror transistor (220), wherein the source follower transistor (210) is electrically connected to an output end of the IO module (100) and is used for receiving and outputting a leakage current of the IO module (100), and the leakage current mirror transistor (220) is electrically connected to an output end of the source follower transistor (210) and is used for outputting a leakage compensation current on the basis of the leakage current of the IO module (100); and a crystal oscillator driving module (300), which is electrically connected to the output end of the IO module (100) and an output end of the leakage compensation module (200), and is used for receiving the leakage current and the leakage compensation current, and outputting a leakage compensation result on the basis of the leakage current and the leakage compensation current. The leakage compensation circuit can perform leakage compensation on an IO circuit, thereby ensuring the normal operation of the IO circuit.

To provide a programmable logic device capable of achieving low power consumption while suppressing reduction in operation speed.SOLUTION: A first circuit, a second circuit, a first transistor which controls electrical connection between the first circuit and the second circuit in accordance with a potential of a gate of the first transistor, a first switch which controls supply of a signal to a first node, and a second switch which controls supply of the signal to a second node, wherein one of a source and a drain and a gate of the first transistor are electrically connected to the first node; A second transistor in which the other of the source and the drain is electrically connected to the second node; and a capacitor configured to hold a potential of the signal supplied to the first node.SELECTED DRAWING: Figure 1

An embodiment relates to a method for manufacturing a metal nanosheet, including: providing a template having a two-dimensional layered structure with a limited interlayer height; and electroplating metal in an interlayer space of the template, wherein nucleation occurs in the interlayer space of the template, and the interlayer height is fixed.

By incorporating a holding circuit into the logic circuit, power gating becomes possible. [Solution] The holding circuit comprises a first terminal, a node, a capacitive element, and first to third transistors It has a terminal. The first transistor controls the conduction state between the first terminal and the input terminal of the logic circuit. The second transistor controls the conduction state between the output terminal of the logic circuit and the node. The 3 transistors control the conduction state between the node and the input terminal of the logic circuit. Transistor 1 The gate of the zista and the gate of the second transistor are electrically connected. Data retention period During this time, the node is electrically floating. The voltage at the node is maintained by the capacitive element.

To provide a programmable logic device capable of achieving low power consumption while suppressing reduction in operation speed.SOLUTION: A first circuit, a second circuit, a first transistor which controls electrical connection between the first circuit and the second circuit in accordance with a potential of a gate of the first transistor, a first switch which controls supply of a signal to a first node, and a second switch which controls supply of the signal to a second node, wherein one of a source and a drain and a gate of the first transistor are electrically connected to the first node; A second transistor in which the other of the source and the drain is electrically connected to the second node; and a capacitor configured to hold a potential of the signal supplied to the first node.SELECTED DRAWING: Figure 1

Aspects of the disclosure are directed to dc power consumption optimization in an extended reality (XR) device with thermal constraints. In accordance with one aspect, the disclosure includes performing a two-input logical AND operation using a first comparison state and a second comparison state as inputs to generate a first conjunctive output; performing a three-input logical AND operation using a third comparison state, a fourth comparison state and a fifth comparison state as inputs to generate a second conjunctive output; performing a two-input logical OR operation using the first conjunctive output and the second conjunctive output to generate a disjunctive output; and setting the disjunctive output to a select line for a two-input multiplexer to select either a processor voltage or a memory voltage as a voltage rail for an electrical load.

The application relates to the chip technical field, in particular to a low-power-consumption asynchronous handshake circuit with a test circuit, which comprises a clock control circuit, a third selector, a first flip-flop, a second flip-flop, a third flip-flop, an AND gate and an OR gate; the function of the low-power-consumption asynchronous handshake circuit is realized in a function mode, and the low-power-consumption asynchronous handshake circuit is tested in a test mode. The application reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit under the premise of meeting the asynchronous handshake circuit test.

To enable power gating by providing a holding circuit on a logic circuit.SOLUTION: A holding circuit has a first terminal, a node, a capacitive element, and first to third transistors. The first transistor controls a conduction state between the first terminal and an input terminal of a logic circuit. The second transistor controls a conduction state between an output terminal of the logic circuit and the node. The third transistor controls a conduction state between the node and the input terminal of the logic circuit. A gate of the first transistor and a gate of the second transistor are electrically connected with each other. During a data retention time period, the node becomes in an electrically floating state. A voltage of the node is held by the capacitive element.SELECTED DRAWING: Figure 4

To provide a semiconductor integrated circuit in which the consumption power can be reduced and the delay of the operation can be reduced.SOLUTION: In each of a plurality of sequential circuits 21_1 to 21_n included in a storage circuit 11, which is a semiconductor integrated circuit, a transistor 31 whose channel formation region is formed of an oxide semiconductor and a capacitative element 32 in which a node with one electrode electrically connected becomes floating when the transistor is turned off are provided. When the channel formation region of the transistor is formed of the oxide semiconductor, the transistor whose off current (leak current) is extremely low can be achieved. Therefore, in a period for which a power supply voltage is not supplied to the storage circuit, the transistor is turned off, so that the potential of the node to which one electrode of the capacitative element is electrically connected in this period can be kept constant or substantially constant.SELECTED DRAWING: Figure 1