98results about "Power consumption reduction" patented technology

The invention discloses a memristor-based signal detection circuit and method, a receiver and equipment, and relates to the field of wireless communication, a voltage source module of the circuit is connected with a voltage input end of a memristor array module, and a current source module is connected with a current input end of the memristor array module; the current output end of the memristor array module is connected with the reverse input end of the operational amplifier module and one end of the feedback resistor module, the other end of the feedback resistor module and the output end of the operational amplifier module are connected with the input end of the multiplier module, and the output end of the multiplier module is connected with one end of the resistor module. The voltage of the voltage source module is set according to the emission vector set; the current of the current source module is set according to the received radio frequency signal, and the conductance value of the memristor is set according to the channel matrix, so that a relatively low bit error rate of signal detection can be realized on the basis of greatly reducing calculation time and power consumption, and meanwhile, the requirement on programmable bit precision of the memristor is also reduced.

A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks disposed about the first axis. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the central portion and indicates a first value when skyrmion is present.

The invention discloses a clock control device and method, a controller and a system-on-chip, and the device comprises the steps: delaying a first preset clock to stop inputting a digital clock signal to a digital logic device based on an analog clock signal inputted by an analog clock generation device when a low-power-consumption request signal issued by the digital logic device is received; delaying the second preset clock to close the analog clock signal output by the analog clock generation device; when a wake-up input signal input by an external wake-up source is received, after a first preset clock is delayed to input a high-level digital clock gating signal to a digital clock gating unit in the clock control device, a third preset clock is delayed to control the analog clock generation device to output an analog clock signal; the digital clock gating unit inputs a digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal. The device can completely avoid burrs generated when clock signals are turned on and turned off.

The invention relates to the technical field of integrated circuits, and discloses a field programmable gate array (FPGA) lookup table circuit and an implementation method, the lookup table circuit comprises a first decoder used for acquiring a first address input signal of a lookup table and decoding the first address input signal to obtain first decoded data; the first selector is used for acquiring RAM multi-bit data, and performing selection processing on the RAM multi-bit data by utilizing the first decoding data to obtain output multi-bit data; the second decoder is used for acquiring a second address input signal of the lookup table and decoding the second address input signal to obtain second decoded data; and the second selector is used for performing selection processing on the output multi-bit data by using the second decoding data to obtain single-bit output data of the lookup table. According to the method, the number of consumed devices is smaller, logic resources and area occupied by the LUT in the FPGA are saved, and the effect of universality enhancement is achieved.

The invention provides a chip pin multiplexing control circuit and a control method thereof, and a chip, the circuit comprises a multiplexing terminal, a chip power supply terminal, a power-on reset controller, a pin signal detector, a voltage detector and a debugging controller, the multiplexing terminal is used for receiving a general function signal and a debugging function signal; the power-on reset controller is used for sending a first enabling control signal to the pin signal detector during power-on; the pin signal detector is used for obtaining an input signal of the multiplexing terminal when enabling is confirmed according to the first enabling control signal, and sending the first control signal to the debugging controller; the voltage detector is used for detecting a voltage signal of a chip power supply terminal and sending a second control signal to the debugging controller; the debugging controller is used for confirming whether to enter a debugging mode according to the first control signal and the second control signal. By applying the chip pin multiplexing control circuit provided by the invention, the waste of chip pin resources can be reduced, and accurate identification of the debugging request signal is ensured.

Disclosed are a clock divider and a control method thereof, which enable retention work to be smoothly performed by ensuring that an output clock of the clock divider is in a low-level state in a retention signal conversion section. A clock divider according to an embodiment of the present invention comprises: a counter that counts clocks of an input clock and generates a counter output for dividing the input clock; an output clock generator that generates a generated clock edge according to the counter output, thereby generating an output clock divided from an input clock; and the state machine controls the counter according to a clock low level request of the power management unit, so that the output clock is in a low level state in a retention signal conversion interval.

The invention relates to the technical field of transistor driving, in particular to an adaptive variable resistance transistor driving system, which comprises a data acquisition module; the driving analysis module is used for determining whether grid resistance driving needs to be carried out on the current opening process according to the abnormal reference value, and carrying out staged driving or overall driving on the grid resistance according to the Miller plateau time and the change rate fluctuation value when the grid resistance driving is carried out on the current opening process; the stage division module is used for determining whether to perform secondary division on each stage according to the stage comparison value corresponding to each stage; the stage driving module is used for determining grid resistance adjustment aiming at the characteristic pre-adjustment sections or all the pre-adjustment sections according to the number of the pre-adjustment sections and adjusting the grid resistance according to the abnormal degree of section change; and the integral driving module is used for adjusting the grid resistance according to the turn-on stage characterization value. According to the invention, the conduction loss of the transistor can be reduced.

The invention provides a combinational logic circuit for outputting a high-voltage signal, and the circuit comprises a power circuit which is provided with a high-voltage source connected to a high voltage PH and a low-voltage source grounded, and is used for outputting a first low voltage PL1 and a second low voltage PL2; a high-voltage source of the low-voltage output signal generation circuit is connected to the first low voltage PL1, a low-voltage source of the low-voltage output signal generation circuit is grounded, and the low-voltage output signal generation circuit is used for outputting a plurality of low-voltage output signals with the same frequency and different phases according to the first low-voltage input signal SL1 and the second low-voltage input signal SL2; each high-voltage signal output circuit is provided with a first high-voltage source, a second high-voltage source, a first low-voltage source and a second low-voltage source, the first high-voltage source is connected to the high voltage PH, the second high-voltage source is connected to the first low voltage PL1, the first low-voltage source is connected to the second low voltage PL2, and the second low-voltage source is grounded; and each high-voltage signal output circuit accesses a corresponding low-voltage output signal and outputs a high-voltage signal according to the corresponding low-voltage output signal, and the high-voltage signals output by the plurality of high-voltage signal output circuits are signals with the same frequency but different phases.

The invention provides an H-bridge power tube driving circuit and a control method. According to the invention, the high-side driving voltage and the low-side driving voltage are additionally arranged, and a plurality of current sources are adopted as current input, so that the technical effects that the power tube quickly enters a linear region to reduce the on-resistance, the starting speed is improved and the loss is correspondingly reduced are achieved by increasing the current input of the input end of the power tube; each current source is provided with an independent switch, so that the current input of the input end of a power tube can be reduced by disconnecting the switches corresponding to part of the current sources after the gate-source voltage stably reaches a set value, and the technical effects of effectively preventing overshoot and reducing noise are achieved; and the corresponding fourth switch and the seventh switch are directly switched off, so that the whole driving circuit can be quickly switched off, the switching-off speed is greatly improved, and the technical effect of reducing circuit loss is achieved. The technical problems that loss is increased and efficiency is reduced due to the fact that the opening and closing speed is low in the prior art are solved.

The application discloses a noise reduction circuit, a power supply circuit, a readout circuit and a detection circuit, and relates to the field of MEMS interface circuits, which is used to reduce the low-frequency noise of a MEMS sensor interface circuit. The power supply circuit comprises a charge pump circuit and a noise reduction circuit, and the noise reduction circuit comprises a reference noise suppression circuit and a charge pump noise suppression circuit. The input end of the reference noise suppression circuit is used for connecting a clock signal, a power supply, a reference voltage and a feedback voltage, the output end is connected to the ground through a capacitor C1, and the output end outputs a second voltage. The power supply voltage of the charge pump noise suppression circuit is used for connecting a first voltage to be reduced, the input end is connected to the second voltage, and the output end respectively outputs a third voltage and the feedback voltage. The application reduces the low-frequency noise transmitted by the high-voltage feedback driving circuit and the charge pump circuit in the MEMS sensor interface circuit, and improves the measurement accuracy of the MEMS sensor.

An apparatus and method of generating an output transmit signal including generating a first portion of an output transmit signal based on an input transmit signal, wherein the first portion of the output transmit signal includes a first set of pulses each spanning a unit interval (UI); generating a second portion of the output transmit signal based on the input transmit signal, wherein the second portion of the output signal includes a second set of pulses each spanning a middle sub-interval of the UI; and combining the first portion with the second portion to generate the output transmit signal.

The invention discloses a power-controllable switch Hall chip, which comprises a magnetic induction unit, the magnetic induction unit is sequentially connected with a signal processing unit and a signal output unit, the magnetic induction unit is also connected with an enabling logic unit, and the enabling logic unit is respectively connected with the signal processing unit and the signal output unit; the enabling logic unit is connected with an external signal, and the switch Hall chip further comprises a power supply pin VCC and a grounding pin GND. The invention further discloses a power control method of the switch Hall chip with the controllable power, and the switch Hall chip with the controllable power is used by the switch Hall chip with the controllable power. The problem that in the prior art, the power and power consumption of a switch Hall chip cannot be dynamically controlled through an external signal is solved.

The invention relates to a capacitive element driver and a method for driving a capacitive element. A circuit for driving an output of a capacitive element between two voltage levels has at least one driver unit having a first pair of switches connected in series between a first voltage source terminal and the capacitive element and a second pair of switches connected in series between a second voltage source terminal and the capacitive element. One or more non-dissipative elements may be connected between a first common node of the first switch pair and a second common node of the second switch pair. A combination of driver cell switches is sequentially activated and deactivated to provide a stepwise transfer of energy to the capacitive element, subtracted from, bypassed to the input voltage, and added to the input voltage. The switching stages that achieve the high voltage output may be the same as the switching stages that achieve the low voltage output, but are organized in an opposite order.

The application discloses a signal detection circuit and method based on a memristor, a receiver and equipment, and relates to the field of wireless communication. A voltage source module of the circuit is connected with a voltage input end of a memristor array module, a current source module is connected with a current input end of the memristor array module, a current output end of the memristor array module is connected with an inverting input end of an operational amplifier module and one end of a feedback resistance module respectively, the other end of the feedback resistance module and an output end of the operational amplifier module are connected with an input end of a multiplier module, and an output end of the multiplier module is connected with one end of a resistance module. The voltage of the voltage source module is set according to a set of transmission vectors, the current of the current source module is set according to a received radio frequency signal, and the conductance value of the memristor is set according to a channel matrix. The application can realize a lower bit error rate of signal detection on the basis of greatly reducing the calculation time and power consumption, and also reduces the requirement for the programmable bit precision of the memristor.

The application discloses a digital processing circuit, comprising a logic unit, at least one combinational logic device, the combinational logic device comprising at least one input terminal; a filter unit is used to divide the waveform of the received initial input signal into at least two segments of waveforms within a cycle of the clock signal of the combinational logic device, and to prevent the back propagation of glitches contained in at least one segment of waveforms, so as to provide a filtered input signal to the input terminal of the combinational logic device. By preventing the back propagation of the glitches contained in at least one segment of waveforms in the initial input signal through the filter unit, the application can eliminate the influence of the glitches in the signal on the power consumption of the entire circuit in time, so as to effectively reduce the additional power consumption caused by the glitches.

The invention discloses a high-power radio frequency switch circuit and a control method thereof, and belongs to the technical field of radio frequency switch circuits, the high-power radio frequency switch circuit comprises a blocking capacitor C2, a matching inductor L12, a diode D1, a capacitor C9, a blocking capacitor C4, a matching inductor L6, a diode D2, a capacitor C12, a blocking capacitor C7 and a matching inductor L7, one end of the blocking capacitor C2 is connected with an input end channel Term1, the other end of the blocking capacitor C2 is connected with one end of the matching inductor L12, and the other end of the matching inductor L12 is connected with the other end of the matching inductor L12. And the other end of the matching inductor L12 is connected to two paths of the switch, namely a first path and a second path, a grounded diode D3 and a grounded diode D4 are respectively connected between the capacitor C9 and the blocking capacitor C4 in the first path and the second path and between the capacitor C12 and the blocking capacitor C7 in the first path and the second path, and the diode D3 and the diode D4 are both connected with a feed circuit. After the two output channels are connected with the grounding diode D3 and the grounding diode D4, the isolation between the channels can be improved, the working frequency range is wider, and the high-frequency insertion loss is smaller.

The low power sequential circuit (e.g., a latch) uses nonlinear polarized capacitors to hold charge with fewer transistors than conventional CMOS sequential circuits. The sequential circuit includes a three-input majority gate having first, second and third inputs and a first output. The sequential circuit includes a driver coupled to the first output, the driver generating a second output. The sequential circuit further includes an exclusive-or (XOR) gate for receiving a clock and the second output, the XOR gate generating a third output coupled to the second input, the first input receiving the data and the third input receiving the second output.

Superconducting circuits-based devices and methods, including reciprocal quantum logic, RQL, based devices and methods are provided. A circuit for an A-and-not-B gate including an output terminal (no), a first input terminal (ai) for receiving a first set of single flux quantum, SFQ, pulses, and a second input terminal (bi) for receiving a second set of SFQ pulses is provided. The circuit further includes a first Josephson junction (104), JJ, coupled to receive the first set of SFQ pulses. The circuit further includes a second JJ (114), where the second JJ when positively biased is configured to negatively bias the first JJ such that the circuit is configured to not pass the first set of SFQ pulses to the output terminal only when the second set of SFQ pulses have arrived at the second input terminal prior to an arrival of the first set of SFQ pulses at the first input terminal.

A battery management device according to an embodiment disclosed in the present document comprises: an intermediate signal generation unit for generating intermediate signals related to controlling the operation of contactors respectively corresponding to a first battery pack and a second battery pack connected in parallel to the first battery pack; and a final signal generation unit for generating a final signal for controlling an electrical connection of a positive contactor corresponding to the second battery pack, the final signal being generated on the basis of the intermediate signal and a comparison result between a link voltage, which is a voltage applied by the first battery pack to nodes to which the first battery pack and the second battery pack are connected, and a pack voltage applied to the contactor corresponding to the second battery pack.

The invention discloses a driving circuit and a signal transmitting chip, and relates to the technical field of communication chips, the driving circuit comprises an amplitude amplification circuit and an impedance matching circuit, the amplitude amplification circuit is used for carrying out amplitude amplification on an external differential input signal and then outputting the signal to the impedance matching circuit, and the impedance matching circuit is used for carrying out impedance matching on the signal; and the impedance matching circuit is connected with the amplitude amplification circuit and is used for performing impedance matching on the differential output signal of the amplitude amplification circuit and then outputting the signal to a post-stage circuit. The driving circuit in the embodiment of the invention is realized through two stages of circuits, namely the amplitude amplification circuit and the impedance matching circuit, and each stage of circuit can realize corresponding functions and reasonably configure power consumption at the same time, so that the power consumption of the whole driving circuit can be smaller than that of a traditional current mode logic driving circuit when the amplitude of an output signal is relatively large; and the power consumption of the signal transmitting chip is reduced.

Data path elements implemented using a plurality of logic primitives are provided. The plurality of logic primitives are connected in one or more topologies to perform an atomic operation on at least two atomic input data of a pre-defined bit-size. The atomic operation is split into a plurality of sub-atomic operations and the at least two atomic input data is split into a plurality of sub-atomic data fragments. Each of the plurality of logic primitives perform a sub-atomic operation from the plurality of sub-atomic operations on at least two sub-atomic data fragments from the plurality of sub-atomic data fragments to generate at least one partial sub-atomic output data. The at least one partial sub-atomic output data is generated based on a partial arithmetic operation, a shift operation, or a logical operation performed by each of the plurality of logic primitives in each clock-cycle. The architectures of a plurality of data-path elements comprised of a plurality of logic primitives in a plurality of connection topologies are provided.

This invention discloses a digital isolator circuit with additional delay, including a transmitter circuit that receives a data input signal and generates first and second transmitter output signals, wherein the second transmitter output signal is a delayed version of the first transmitter output signal. Subsequently, an isolation barrier generates the first and second isolation output signals, causing a receiver circuit to generate a data output signal in response to these isolation output signals. By further incorporating a delay circuit in the transmitter circuit to delay the first transmitter output signal and generate the second transmitter output signal, this invention effectively enhances the received signal at the receiver circuit, maintaining the stability of the common-mode signal and the robustness of data transmission. A pulse carrier modulation mechanism is also employed to effectively reduce power consumption, electromagnetic interference, and signal jitter.

The invention discloses a high-performance low-power-consumption single-ended to differential conditioning signal circuit which comprises an input signal isolation conditioning circuit, a common-mode input conditioning isolation circuit, an in-phase amplification conditioning circuit and a reverse amplification conditioning circuit. The input signal isolation conditioning circuit receives a single-ended signal, prepares for a post-stage, and is connected with the in-phase and reverse amplification conditioning circuit. The common-mode input conditioning isolation circuit receives a common-mode conditioning signal, and after the stability of the common-mode conditioning signal is enhanced, the common-mode input conditioning isolation circuit accesses the reverse amplification conditioning circuit. The in-phase and reverse amplification conditioning circuit converts a single-ended signal into a differential signal and then is connected with the digital-to-analog converter. The circuit only uses a single positive power supply rail, can adapt to more AD modules without damaging signal quality, has a wide adjustable common-mode level range, and meets more AD input requirements. A negative power supply is omitted, the power supply structure is simplified, and power consumption is reduced. And moreover, a single-ended to differential chip is not needed, so that the hardware type selection cost is reduced and more device type selection schemes are provided when the design volume of the PCB is not changed.

A communication device includes a first device and a second device. The first device includes a transmitting circuit configured to output and transmit a differential signal including a first signal and a second signal to the second device using an input signal and an enable signal. The second device includes a first amplifier configured to receive the differential signal from the first device, a gate circuit configured to gate an output signal of the first amplifier based on a deactivated reset signal, and a count circuit configured to: (1) count a section in which a value of the differential signal is constant based on a clock signal and an output signal of the gate circuit and (2) generate an activated reset signal when the count of the section exceeds a threshold value.

The invention relates to an industrial standard digital quantity input device. The device comprises an input circuit, a protection and clamping circuit, a current limiting circuit, a power supply circuit, a hysteresis comparator circuit and a micro-control unit, wherein the input circuit is used for transmitting a digital quantity input (DI) signal to the protection and clamping circuit; the protection and clamping circuit is used for clamping the voltage of the input DI signal within a preset safety range; the current limiting circuit is used for limiting the current of the DI signal passing through the protection and clamping circuit below a preset threshold value; the hysteresis comparator circuit is used for comparing the voltage of the DI signal passing through the current limiting circuit with a reference voltage; the micro-control unit is used for receiving the voltage signal transmitted by the hysteresis comparator circuit and sending the voltage signal to the upper-layer controller; the power supply circuit is used for providing preset voltage for the current limiting circuit, the hysteresis comparator circuit and the micro-control unit. The device has a DI input current control function and a DI signal clamping function, and the stability and the anti-interference performance of the circuit can be improved.

The invention relates to the technical field of latches, and discloses a high-performance low-overhead four-point reinforced latch based on dual modular redundancy, which comprises an input module, a storage module L1 and a storage module L2, the storage module L1 and the storage module L2 are connected with the input module, and the storage module L1 and the storage module L2 are connected with an output module; and the input module comprises a transmission gate TG1-a transmission gate TG10 which are connected with the storage module L1 and the storage module L2. According to the method, internal four-node overturning can be completely tolerated, and meanwhile, the method has a relatively high four-node overturning self-recovery rate and relatively high reinforcing performance and reliability; a double-input C unit stacking structure is adopted, the leakage power consumption is greatly reduced, and the clock control double-input C unit is utilized, so that the dynamic power consumption is reduced; only one transmission gate is arranged from the input end to the output end in a transparent mode, so that the latch has low time delay and can be widely applied to the fields of aerospace and the like with high requirements on reliability and low power consumption of the latch.

The invention discloses a phase interpolator circuit, and belongs to the field of phase interpolator circuits. The phase interpolator circuit comprises a current source module, a control word decoding module, a phase interpolation module and a buffer output module, the current source module provides different currents for different units of the phase interpolation module, the control word decoding module converts an input control word into a corresponding control signal, the phase interpolation module allocates weight to an input four-phase clock according to the input control word to carry out phase interpolation and output, and the buffer output module recovers a voltage signal to a full swing. The digital resource overhead and the circuit area are remarkably reduced, and high linearity can be achieved through the designed control word decoding scheme and the current source proportion. The method is applied to a multi-channel high-speed sampling application scene with harsh area and resource overhead requirements.

According to the trimming circuit and the trimming method thereof, the electrical device and the vehicle, through the technical scheme, the fusing state of an internal trimming fuse is controlled according to the trimming input signal based on the trimming module, the trimming control signal is generated according to the fusing state, and the trimming output signal is generated according to the trimming control signal through the output module; according to the trimming circuit, the trimming module is electrically connected to the first enabling line, so that the trimming module is turned on or turned off according to the first enabling signal output by the first enabling line, the trimming module is controlled to be turned off through the first enabling signal when the trimming function is not needed, and the power consumption of the trimming circuit is reduced.

The invention aims to provide a digital-analog hybrid LDO (Low Dropout Regulator) suitable for a high-speed signal interface circuit and a FinFet process. The circuit comprises an analog LDO module, a digital LDO module and a control module, the analog LDO module is connected with the digital LDO module and the control module and is used for outputting stable voltage; the digital LDO module is connected with the control module and is used for adjusting the output voltage until the output voltage is stable when the output voltage changes; the control module is used for detecting the output voltage and controlling the digital LDO module to adjust the output voltage. Compared with a traditional analog LDO, the LDO has the advantages of being suitable for low-voltage work and low in power consumption, the transient response is faster, the requirement of a high-speed interface circuit for transient large current in the high-speed read-write process can be met, and compared with a digital LDO, the LDO has the advantages of being good in power supply rejection and capable of meeting the requirement of PLL and other high-speed circuit modules for power supply ripples.

A communication device includes a first device and a second device. The first device includes a transmitting circuit configured to output and transmit a differential signal including a first signal and a second signal to the second device using an input signal and an enable signal. The second device includes a first amplifier configured to receive the differential signal from the first device, a gate circuit configured to gate an output signal of the first amplifier based on a deactivated reset signal, and a count circuit configured to: (1) count a section in which a value of the differential signal is constant based on a clock signal and an output signal of the gate circuit and (2) generate an activated reset signal when the count of the section exceeds a threshold value.