13 results about "Differential signaling" patented technology

Modem datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and / or PCIe domains, addressing interoperability challenges.

Modern datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and / or PCIe domains, addressing interoperability challenges.

Disclosed in the present invention are a low-voltage differential signaling device and a low-voltage differential signaling driver. An output circuit of the low-voltage differential signaling driver comprises a first current source and a differential push-pull output circuit, wherein the first current source is connected between a power source end and the differential push-pull output circuit, and the differential push-pull output circuit is connected to a differential output end of the low-voltage differential signaling driver, and is used for generating a first output voltage and a second output voltage on the basis of a first input signal and a second input signal. A turn-off circuit of the low-voltage differential signaling driver is connected to the differential output end of the low-voltage differential signaling driver and is used for turning off the first current source by using a short-circuited power source on the differential output end when the low-voltage differential signaling driver is in a leakage protection state. A first end of a substrate clamping circuit of the low-voltage differential signaling driver is connected to the power source end, and a second end thereof provides a substrate potential to a MOS transistor in the first current source. When the low-voltage differential signaling driver is in the leakage protection state, the substrate clamping circuit is in an off-state in the direction from the second end to the first end, such that effective leakage protection can still be performed on the low-voltage differential signaling driver when the low-voltage differential signaling driver is in a power-off state.

An example device for processing video data includes a memory configured to store video data; and a processing system implemented in circuitry, the processing system being configured to: receive data representing a plurality of neural networks associated with a video bitstream, each of the plurality of neural networks having a different type; receive data representing an update to at least one of the neural networks, the data including a type corresponding to the at least one of the neural networks and a neural network structure for the update; update the neural network according to the data representing the update to generate an updated neural network; and provide video data from the video bitstream to the updated neural network to cause the updated neural network to process the video data.

A CMS includes a camera mounted to a commercial vehicle. The camera is configured to provide a video feed of an external environment of the commercial vehicle. The CMS includes an electronic control unit (ECU) that includes processing circuitry operatively connected to memory. The processing circuitry is configured to receive the video feed from the camera over a wired interface, and the video feed is serialized. The processing circuitry is configured to deserialize the video feed according to a first low-voltage differential signaling (LVDS) standard based on the video feed being serialized according to the first LVDS standard, and deserialize the video feed according to a second LVDS standard based on the video feed being serialized according to the second LVDS standard. A method for a camera monitor system (CMS) is also disclosed.

Device comprising: an interface logic for differential signaling on a plurality of paths, where the interface logic is configured to transmit a plurality of flits, wherein the plurality of flits has a plurality of nibbles, and wherein a first of the plurality of flits is transmitted with a clean flit boundary such that each of the plurality of paths is used to transmit initial nibbles of the first flit in a first unit interval (UI), and wherein initial nibbles of a second flit of the plurality of flits, together with final nibbles of the first flit, are transmitted on the plurality of paths during a subsequent UI.

A differential signaling circuit is provided. The differential signaling circuit includes: a differential amplifier configured to generate differential signals; a first signal path circuit; a second signal path circuit; a phase control circuit configured to receive the differential signals having a common phase, output DC signals having a common level in a first operating period, and transmit the differential signals to the first signal path circuit and the second signal path circuit, respectively, in a second operating period; and a duty ratio correction circuit connected between the first signal path circuit and the second signal path circuit, and configured to control duty ratios of the differential signals to be equal to each other in the second operating period.

A connector that provides a solderless mating interface and includes ground shields with terminal pairs, a tail aligner with apertures, and a gasket with apertures. The connector has compression signal contacts coupled to the terminal pairs and compressible compliant pins integral with the ground shield. The compression signal contacts and compliant pins extend through the tail aligner and gasket apertures. The compliant pins may be eye-of-the-needle type and extend below the gasket and tail aligner. The ground shields may be nested within a connector housing. The connector provides a solderless, mechanically robust connection suitable for high-speed differential signaling applications.

A differential signal receiver is provided. The differential signal receiver includes a first differential difference amplifier, a second differential difference amplifier, a latch and a first inverter. The first differential difference amplifier and the second differential difference amplifier compare a voltage value of an input signal with a first threshold value and a second threshold value, respectively, so as to output a first difference signal and a second difference signal, respectively. The second threshold value is an opposite value of the first threshold value. The latch has a set terminal for receiving the first difference signal and a reset terminal for receiving the second difference signal. The first inverter is configured to receive the first latch signal and output the first output signal. The first output signal has a duty cycle being the same as a duty cycle of the input signal.

An apparatus and method for reducing differential cross-talk in a pin arrangement of a socket are described. Socket pins within a differential pair use a modified shape to tighten the intra-pair pin coupling to reduce the crosstalk without changing the pin map. The middle vertical segment of one pin of a diagonally adjacent differential pin pair is modified to be closer to the other pin than other corresponding locations of the pins. The spring beam that extends from the middle vertical segment of the one pin is modified to accommodate the package landing pad that the spring beam contacts to maintain a uniform pitch.

A digital tape measure device is configured with an optical encoder that facilitates improved measurement capabilities. The optical encoder may be configured in one of several different optical configurations to process differential signaling generated by light generating and detecting elements in the sensor.

An example apparatus for processing video data includes a memory configured to store video data; and a processing system implemented in the circuit, the processing system configured to: receive data representing a plurality of neural networks associated with the video bitstream, each neural network of the plurality of neural networks having a different type; receiving data representing an update to at least one of the neural networks, the data including a type corresponding to the at least one of the neural networks and a neural network structure for the update; updating the neural network according to the data representing the update to generate an updated neural network; and providing video data from the video bitstream to the updated neural network to cause the updated neural network to process the video data.

This application relates to implementations of storing fuse data in a memory device. Some implementations can include an array of memory cells having different portions of cells for storing data. A first portion of the array can store fuse data and can contain a chalcogenide storage element, while a second portion of the array can store user data. Sensing circuitry can be coupled with the array and can determine a value of the fuse data using various signaling techniques. In some cases, the sensing circuitry can implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.