27 results about "Differential signaling" patented technology

Modem datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and / or PCIe domains, addressing interoperability challenges.

Illustrative communication interfaces and protocols for multi-service data communication between a hearing device and an accessory are described herein. For example, an example hearing system may include a hearing device configured to be worn by a recipient, an accessory configured to interoperate with the hearing device while worn separately by the recipient, and a communication interface between the hearing device and the accessory. The communication interface may include two physical conductors configured to carry differential signaling generated in accordance with a frame protocol that defines a data frame configured to communicate a first dataset and a second dataset. The first dataset is associated with a first data service performed in accordance with a first quality-of-service. The second dataset is associated with a second data service performed in accordance with a second quality-of-service different from and incompatible with the first quality-of-service. Corresponding systems and methods are also disclosed.

Modern datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and / or PCIe domains, addressing interoperability challenges.

The application discloses an interlaced differential signal loop system and a method thereof. The TX+ pin and the RX+ pin and the TX- pin and the RX- pin in the first differential signal interface of the line conversion card are electrically connected to each other to form a loop. The line conversion card does not need to perform additional detection, and can provide a differential signal loop detection of a differential signal generated by a central processing unit of a to-be-tested circuit board. The TX+ pin and the RX+ pin and the TX- pin and the RX- pin are electrically connected to each other to avoid the situation that a signal short circuit cannot be detected. Therefore, the technical effect that the differential signal loop detection is realized by the line conversion card to improve the differential signal detection efficiency can be achieved.

Disclosed in the present invention are a low-voltage differential signaling device and a low-voltage differential signaling driver. An output circuit of the low-voltage differential signaling driver comprises a first current source and a differential push-pull output circuit, wherein the first current source is connected between a power source end and the differential push-pull output circuit, and the differential push-pull output circuit is connected to a differential output end of the low-voltage differential signaling driver, and is used for generating a first output voltage and a second output voltage on the basis of a first input signal and a second input signal. A turn-off circuit of the low-voltage differential signaling driver is connected to the differential output end of the low-voltage differential signaling driver and is used for turning off the first current source by using a short-circuited power source on the differential output end when the low-voltage differential signaling driver is in a leakage protection state. A first end of a substrate clamping circuit of the low-voltage differential signaling driver is connected to the power source end, and a second end thereof provides a substrate potential to a MOS transistor in the first current source. When the low-voltage differential signaling driver is in the leakage protection state, the substrate clamping circuit is in an off-state in the direction from the second end to the first end, such that effective leakage protection can still be performed on the low-voltage differential signaling driver when the low-voltage differential signaling driver is in a power-off state.

An example device for processing video data includes a memory configured to store video data; and a processing system implemented in circuitry, the processing system being configured to: receive data representing a plurality of neural networks associated with a video bitstream, each of the plurality of neural networks having a different type; receive data representing an update to at least one of the neural networks, the data including a type corresponding to the at least one of the neural networks and a neural network structure for the update; update the neural network according to the data representing the update to generate an updated neural network; and provide video data from the video bitstream to the updated neural network to cause the updated neural network to process the video data.

A CMS includes a camera mounted to a commercial vehicle. The camera is configured to provide a video feed of an external environment of the commercial vehicle. The CMS includes an electronic control unit (ECU) that includes processing circuitry operatively connected to memory. The processing circuitry is configured to receive the video feed from the camera over a wired interface, and the video feed is serialized. The processing circuitry is configured to deserialize the video feed according to a first low-voltage differential signaling (LVDS) standard based on the video feed being serialized according to the first LVDS standard, and deserialize the video feed according to a second LVDS standard based on the video feed being serialized according to the second LVDS standard. A method for a camera monitor system (CMS) is also disclosed.

Systems and methods for light emitting diode (LED) displays. An LED display includes display panels connected to form the LED display. The LED display includes a module for controlling a plurality of LED lamps in the LED display based on the content of the image. Wherein each module integrates therein at least one controller and a plurality of drivers that operate together to control an amount of light emitted by each of the plurality of LED lamps in some of the display panels according to pixel values in corresponding portions of the image. Wherein the at least one controller and the plurality of drivers in each module communicate via a low voltage differential signaling (LVDS) signal.

Device comprising: an interface logic for differential signaling on a plurality of paths, where the interface logic is configured to transmit a plurality of flits, wherein the plurality of flits has a plurality of nibbles, and wherein a first of the plurality of flits is transmitted with a clean flit boundary such that each of the plurality of paths is used to transmit initial nibbles of the first flit in a first unit interval (UI), and wherein initial nibbles of a second flit of the plurality of flits, together with final nibbles of the first flit, are transmitted on the plurality of paths during a subsequent UI.

A differential signaling circuit is provided. The differential signaling circuit includes: a differential amplifier configured to generate differential signals; a first signal path circuit; a second signal path circuit; a phase control circuit configured to receive the differential signals having a common phase, output DC signals having a common level in a first operating period, and transmit the differential signals to the first signal path circuit and the second signal path circuit, respectively, in a second operating period; and a duty ratio correction circuit connected between the first signal path circuit and the second signal path circuit, and configured to control duty ratios of the differential signals to be equal to each other in the second operating period.

An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

A connector that provides a solderless mating interface and includes ground shields with terminal pairs, a tail aligner with apertures, and a gasket with apertures. The connector has compression signal contacts coupled to the terminal pairs and compressible compliant pins integral with the ground shield. The compression signal contacts and compliant pins extend through the tail aligner and gasket apertures. The compliant pins may be eye-of-the-needle type and extend below the gasket and tail aligner. The ground shields may be nested within a connector housing. The connector provides a solderless, mechanically robust connection suitable for high-speed differential signaling applications.

The invention discloses a high-speed image transmission method and system based on low-voltage differential signals and a medium, and the method adopts a 1: 28 clock data ratio transmission format. The sending card splits original image data by taking 28 bits as a group, adds a synchronous head, a row effective signal, a field effective signal, a reserved bit and 24 RGB data bits to obtain an LVDS serial data signal, and outputs the LVDS serial data signal to the receiving card through a pair of LVDS clock differential pairs and a pair of LVDS data differential pairs; and the receiving card analyzes the 28-bit LVDS parallel data signal from the LVDS serial data signal, recodes the analyzed 28-bit LVDS parallel data signal into the LVDS serial data signal, and transmits the LVDS serial data signal to the next level of cascaded receiving card through the output differential pair. According to the invention, the occupation of hardware pin resources is reduced, and the type selection requirement on the FPGA chip is reduced, so that the hardware cost is saved.

A differential signal receiver is provided. The differential signal receiver includes a first differential difference amplifier, a second differential difference amplifier, a latch and a first inverter. The first differential difference amplifier and the second differential difference amplifier compare a voltage value of an input signal with a first threshold value and a second threshold value, respectively, so as to output a first difference signal and a second difference signal, respectively. The second threshold value is an opposite value of the first threshold value. The latch has a set terminal for receiving the first difference signal and a reset terminal for receiving the second difference signal. The first inverter is configured to receive the first latch signal and output the first output signal. The first output signal has a duty cycle being the same as a duty cycle of the input signal.

The invention provides a signal processing system and method based on an LPTI controller. The system comprises an LPTI controller which comprises a channel controller, a link manager, a transmitting channel and a receiving channel; wherein the channel controller is connected with the link manager, and the transmitting channel is connected with the receiving channel; the link manager is connected with the channel controller, the transmitting channel and the receiving channel; the transmitting channel comprises a frame generator, an encoder, a transmitting cache and a transmitting low-voltage differential signal parallel-to-serial controller which are connected in sequence, and the frame generator is connected with the channel controller; the frame generator is connected with the link manager; the receiving channel comprises a frame parser, a decoder, a word alignment module, a receiving cache and a receiving low-voltage differential signal serial-to-parallel controller which are connected in sequence, and the frame parser is connected with the channel controller; the frame analyzer is connected with the link manager; the link manager further comprises a link manager state machine, and the link manager state machine is used for carrying out signal receiving and transmitting training on the controller.

An apparatus and method for reducing differential cross-talk in a pin arrangement of a socket are described. Socket pins within a differential pair use a modified shape to tighten the intra-pair pin coupling to reduce the crosstalk without changing the pin map. The middle vertical segment of one pin of a diagonally adjacent differential pin pair is modified to be closer to the other pin than other corresponding locations of the pins. The spring beam that extends from the middle vertical segment of the one pin is modified to accommodate the package landing pad that the spring beam contacts to maintain a uniform pitch.

A digital tape measure device is configured with an optical encoder that facilitates improved measurement capabilities. The optical encoder may be configured in one of several different optical configurations to process differential signaling generated by light generating and detecting elements in the sensor.

An example apparatus for processing video data includes a memory configured to store video data; and a processing system implemented in the circuit, the processing system configured to: receive data representing a plurality of neural networks associated with the video bitstream, each neural network of the plurality of neural networks having a different type; receiving data representing an update to at least one of the neural networks, the data including a type corresponding to the at least one of the neural networks and a neural network structure for the update; updating the neural network according to the data representing the update to generate an updated neural network; and providing video data from the video bitstream to the updated neural network to cause the updated neural network to process the video data.

The present subject matter relates to methods, circuitry and equipment providing a multi-functional, cost effective, media independent, open platform for communication services using differential signaling interfaces. The methods, circuitry and equipment comprise a plurality of input amplifiers, output amplifiers, and multiplexer switches or resistive dividers. which provide the ability to monitor, provide service protection switching, provide redundant services, provide on-demand service, provide service upgrades, security, test. and troubleshoot any communication devices and services.

A rotating electric machine includes a shaft angle sensor communicating with an external controller via differential signaling. This construction permits the controller to be located away from the axial end of the motor while reliably transmitting rotor angle or speed information to the controller over a relatively long electrical harness. The shaft angle sensor is mounted on a sensor board carried by the machine casing at the non-drive end of the rotor shaft. The sensor board can optionally act as a hub at which signals from multiple machine sensors are gathered to be placed in communication with the controller via the same electrical harness used to transmit the sensor information.

The present subject matter relates to methods, circuitry and equipment providing a multi-functional, cost effective, media independent, open platform device for communication services using differential signaling interfaces. The methods, circuitry and equipment comprise a plurality of input amplifiers, output amplifiers, and retimers. A non-blocking cross-point switch may be used to switch any differential signals from the cross-point switch input to output. The device aggregates communication services from a plurality of lower service capacity connectors and interfaces to a single higher capacity connector and interfaces. The device can establish a demarcation point with a single device capable of supporting any communication services, any physical media interfaces, from any location.

The invention relates to the technical field of high-speed circuit board design, and discloses a PCB (printed circuit board) wiring structure capable of realizing differential signal subpicosecond-level isochronous matching in an ultra-high-speed ultra-wideband range, which comprises a first transmission line and a second transmission line in a differential signal transmission line pair, the first transmission line is a linear path, and the second transmission line is a linear path. The second transmission line is a curve path formed by periodically splicing a plurality of arc-shaped structures, the arc-shaped structure of a single period is formed by splicing a plurality of arc segments through rotation copying and mirror image copying, and the first transmission line and the second transmission line are equal in physical length; wherein the arc segment satisfies the following two key parameter conditions: (a) the radius of the arc segment is Rgt; w is the line width of the transmission line; (b) a central included angle AOBlt corresponding to the arc line segment; the temperature is 40 DEG C; the invention provides a design method of a PCB wiring structure which is simple in structure, can be widely applied and can realize subpicosecond-level isochronous matching of differential signals in an ultra-wideband range.

This application relates to implementations of storing fuse data in a memory device. Some implementations can include an array of memory cells having different portions of cells for storing data. A first portion of the array can store fuse data and can contain a chalcogenide storage element, while a second portion of the array can store user data. Sensing circuitry can be coupled with the array and can determine a value of the fuse data using various signaling techniques. In some cases, the sensing circuitry can implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.

An interface circuit enabling communication via a differential transceiver with both differential signaling and non-differential signaling field devices connected to the same bus includes switches and control logic to enable differential signaling on the bus in a first mode and non-differential signaling on the bus in a second mode. In the second mode of non-differential signaling, the differential conductors of the bus are held at the same potential. Further in the second mode of non-differential signaling, a differential signal is created within the interface circuit from one signal of the bus and provided to the differential transceiver.

Illustrative communication interfaces and protocols for multi-service data communication between a hearing device and an accessory are described herein. For example, an example, an illustrative system includes a hearing device, an accessory configured to interoperate with the hearing device, and a communication interface between the hearing device and the accessory, the communication interface configured to carry differential signaling generated in accordance with a frame protocol. The frame protocol defines a data frame configured to communicate a first dataset and a second dataset, the first dataset associated with a first quality-of-service and the second dataset associated with a second quality-of-service different from and incompatible with the first quality-of-service.

Differential signaling transmitter circuitry includes upper and lower driver stacks, each with at least one upper blocking transistor and a bias transistor, further includes first and second control loops. A first control loop includes a replica stack including replicas of the bias transistor and blocking transistors of a first one of the driver stacks, and a second control loop includes replica stacks, one with replicas of the bias and blocking transistors of the upper driver stack and one with replicas of the bias and blocking transistors of the lower driver stack. One of the replica stacks in the second control loop receives an output from the first control loop. First and second switching circuitry couples outputs of the first and second control loops to gates of bias transistor in the upper and lower driver stacks, respectively, responsive to a data signal.

This invention discloses a low-voltage differential signaling device and its driver. The driver includes an output circuit, a bias circuit, and a first clamping circuit. The output circuit includes a push-pull circuit and a first tail current source disposed between the power supply terminal and the push-pull circuit. The bias circuit has a bias current generating unit that provides a first bias current. The first clamping circuit provides a second bias current to the bias circuit. When the enable signal is at a first level, the bias circuit provides a first preset bias voltage to the first tail current source according to the sum of the first bias current and the second bias current, and the driver is in a normal state. When the enable signal is at a second level, the bias circuit provides a second preset bias voltage to the first tail current source according to the second bias current, and the driver is in a high-impedance state. The second preset value is less than the voltage value at the power supply terminal and greater than the first preset value, thereby improving the enable speed when the output state of the LVDS driver switches from a high-impedance state to a normal state.