272results about "Synchronisation information channels" patented technology

The invention relates to the technical field of high-frequency multichannel synchronous transmission, in particular to a time domain reflection compensation design method for high-frequency signal transmission loss, which comprises the following steps of: 1, responding to a synchronous trigger signal to generate an active reflection reference signal with a determined time domain position; 2, aligning time marks between channels through cross-correlation operation; 3, extracting a reflection feature template of the channel from the alignment signal, and recognizing and eliminating crosstalk components through convolution operation with an adjacent channel template; 4, constructing a time-varying transfer function model according to the amplitude envelope attenuation characteristic and the carrier phase jump characteristic of the reflection characteristic template; and 5, generating a compensation filter based on the time-varying transfer function model, and verifying the compensation effect through secondary reflection. Through cross-correlation operation, accurate alignment of multi-channel signal time scales is realized, the time delay difference between different transmission channels is overcome, signal synchronization of each channel is ensured, and the beam forming precision is improved.

This disclosure is generally directed to a full-duplex transceiver including a primary circuit and a secondary circuit communicating using a clock signal of the primary circuit (e.g., a single clock signal). The primary circuit may include circuitry to generate and / or forward the clock signal to the secondary circuit. The secondary circuit may sample received data using the clock signal. Moreover, the secondary circuit may generate data, perform data processing operations, and / or transmit data using the clock signal of the primary circuit.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

A system includes a plurality of semiconductor chips that are stacked on top of each other and that include first and second semiconductor chips. The first semiconductor chip includes a clock signal generating circuit, a transmitting circuit, and a receiving circuit. The clock signal generating circuit generates a clock signal and a delayed version of the clock signal. The transmitting circuit transmits a first data signal in response to the clock signal. The receiving circuit receives a second data signal in response to the delayed version of the clock signal. For example, the receiving circuit receives the delayed version of the clock signal at substantially the same time that the transmitting circuit receives the clock signal.

Some embodiments relate to a communication network comprising at least one receiver system optically coupled to a plurality of transmitter systems for transmission of synchronization signals generated by the at least one receiver system to the plurality of transmitter systems over a unidirectional synchronization channel. The at least one receiver system configured to embed into the synchronization signals thereby generated additional data indicative of an internal time count thereof for synchronization of transmission of data / signals from each one of the plurality of transmitter systems to said at least one receiver system over a sparse data / signals unidirectional communication channel.

In an alignment marker search method, a first module receives a first data stream, where the first data stream is obtained by multiplexing a plurality of second data streams at a reference granularity, any second data stream includes an AM and data from at least one FEC codeword, and the reference granularity is a quantity of bits corresponding to n symbols included in the FEC codeword; obtains a first data segment from a first location in the first data stream at the reference granularity; and performs AM search on the first data segment. The reference granularity is the quantity of bits corresponding to the n symbols. Therefore, when a burst bit error occurs in the first data stream, a quantity of symbols affected by the burst bit error is small.

In a first aspect, the disclosure provides an apparatus (412a) for wireless communication, comprising: a first clock loop (420) comprising a first plurality of latches (422, 424) that generate a first plurality of clock signals (I, Q) having a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) having a corresponding second plurality of phases, where the first clock loop is configured to be enabled or disabled based on the first enable signal and the second clock loop is configured to be enabled or disabled based on the second enable signal. And wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

Systems and methods are disclosed for phase calibration between clock and data lanes at a data link receiver. In calibration mode, matching signals are transmitted over the clock and data lanes, and a phase offset is measured at the receiver. A phase shifter in one signal path is adjusted to a first phase to obtain a desired phase offset. For operation mode, the phase shifter is set based on the first phase. Embodiments measure phase offset using an XOR gate and use a phase interpolator as the phase shifter. Embodiments with multiple data lanes apply coarse calibration to a shared clock lane relative to a first data lane, and similar fine calibration to other data lanes. Calibration provides optimum signal-to-noise ratio or timing margin, enabling high transmission speeds at relatively low power. Variations are disclosed.

One example includes a data alignment system. The system includes a bit alignment detector configured to detect bit-wise alignment of transmission signals provided from respective transmit channels based on a receiver signal provided by a remote receiver. The transmission signals can be combined to generate the receiver signal via a data combiner in the remote receiver. The system also includes a data alignment detector configured to detect alignment of data in each of the transmission signals. The system further includes a delay controller configured to provide at least one delay signal to at least one of the transmit channels to selectively delay a respective at least one of the transmission signals in response to at least one of the bit alignment detector failing to detect the bit-wise alignment of the transmission signals and the data alignment detector failing to detect alignment of the data in each of the transmission signals.

Aspects of this technical solution can generate, according to one or more first environment metrics, a three-dimensional (3D) model including a first surface corresponding to one or more physical ways through a physical environment, the one or more first environment metrics indicative of boundaries of the one or more physical ways, generate, according to one or more second environment metrics, one or more geometric two-dimensional (2D) objects on the first surface, the second environment metrics indicative of the one or more physical ways, identify, according to one or more viewpoint metrics indicative of cameras of a physical object configured to move along the one or more physical ways, one or more viewpoints oriented to capture corresponding portions of the 3D model, and render, from the one or more corresponding portions of the 3D model, one or more 2D images each corresponding to respective ones of the viewpoints.

A wireless communication system, according to one embodiment of the present invention, comprises: a first communication module; and at least one second communication module wirelessly connected to the first communication module, wherein the first communication module is wirelessly connected to the second communication module to which driving power is applied from the same power source as that of the first communication module.

A system includes a first integrated circuit coupled to a printed circuit board (PCB) and a second integrated circuit coupled to the PCB. The system further includes a ground referenced signaling (GRS) link coupled between the first integrated circuit and the second integrated circuits through the PCB. Unencoded data is transmitted on the GRS link according to a memory coherence protocol.

The invention discloses a multi-path frequency-adjustable signal generation system based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of signal generation. The system comprises an adjustable frequency signal generation module, an FPGA register read-write control module, an SPI communication module and a top layer module. The top layer module adopts a generate block statement to realize batch instantiation of a multi-path signal output module, a positioning register mechanism is introduced, and a group of register resources are used for controlling a multi-path output channel, so that the problem of register resource waste caused by repeated instantiation of the module in the traditional design is effectively solved. According to the system, remote configuration of an FPGA internal register by a CPU is achieved through an SPI communication interface, and the frequency-adjustable signal generation module supports independent adjustment of parameters such as frequency, high pulse width and low pulse width. And when the positioning register is matched with a specific output channel and the data updating flag bit is valid, the system accurately sends the characteristic parameters to the corresponding channel, so that the accuracy of each path of signal parameters is ensured. According to the method, the code redundancy and the development time are remarkably reduced, and the system maintainability is improved.

A communication system, apparatus, method, and one or more non-transitory computer-readable storage devices that implement integration of perception and communication employ the following steps: transmitting a radio frequency (RF) signal. The RF signal includes one or more communication symbols for communication and one or more perceived signal components for perceiving an object, the RF signal including timing information of the one or more perceived signal components.

A system for clock synchronization, including a quantum control processor (QCP) and digital-analog inter-converters. Each digital-analog inter-converter includes a frequency conversion module and a signal synchronization module. The signal synchronization module includes a D flip-flop (DFF). The QCP generates a signal for global synchronization (Sync_GLB) and reference clock signals (REFCLKs), and the Sync GLB and the corresponding REFCLK to the frequency conversion module, and transmits the Sync GLB to the signal synchronization module. The frequency conversion module performs frequency conversion on the REFCLK to obtain a target clock signal, generates an instruction for signal synchronization according to the signal for global synchronization, and transmits the instruction for signal synchronization and the target clock signal to the signal synchronization module. The signal synchronization module performs signal synchronization on the target clock signal via the DFF, based on the signal for global synchronization. The present disclosure further provides a method for controlling signal synchronization. The DFF relocks the signal for global synchronization to the target clock signal having a low jitter, reducing signal delay and improving precision of signal synchronization.

A signal driving circuit includes a first driver, a control signal generation circuit, and a second driver. The first driver is configured to generate a first transmission signal based on an input signal and a clock signal. The control signal generation circuit is configured to generate a delay clock signal by delaying the clock signal and to generate a first control clock signal and a second control clock signal with different pulse widths than the pulse width of the delay clock signal. The second driver is configured to generate a second transmission signal, based on the first transmission signal and the first and second control clock signals.

An embodiment includes a forward data receiving device that demodulates and receives an Amplitude Shift Keying (ASK) modulation signal, and includes: an input module configured to receive the ASK modulation signal as an input; a resonance regulating rectifier module configured to regulate and rectify an input voltage of the ASK modulation signal on the basis of Pulse Width Modulation (PWM) according to a preset target voltage, and apply a regulated voltage through an output transistor; and a demodulation module configured to demodulate the ASK modulation signal according to a trend in a change of the input voltage compared to the regulated voltage, wherein the resonance regulating rectifier module includes a comparison unit configured to generate a gate signal for controlling on / off of the output transistor, and generate a sample signal for demodulating the ASK modulation signal.

The present invention provides an effective hardware architecture for a combined aggregation and distribution unit (CCDU) ​​ORAN-compliant clock synchronizer module for 5G foundation applications required to handle L1, L2, and L3 schedules of the network. The CCDU design can achieve CU and DU functionality in a single unit and can operate over a wide temperature range. The single board approach of the CCDU makes the CCDU more reliable and less costly. The CCDU can support different types of synchronization and can provide site alarms over dry contacts for accommodating external alarm devices.

Systems, methods, and circuits for performing bidirectional communication using an edge time in a signal are provided. In one example, a method involves receiving a common signal on a signal line between one device and another. The common signal comprises a series of signal periods, and each signal period includes a first edge of a first type and a second edge of a second type, different from the first type. In each signal period of the series of signal periods, information to be communicated by the other device is determined at least based on the determined time of the first edge, and a time for a subsequent second edge with respect to the signal period is determined based on information to be communicated to the other device.The subsequent second edge is generated at the selected time in a subsequent signal period of the series of signal periods.

A time transfer method based on undifferenced and uncombined PPP-RTK is applied to a time transfer system including a PPP-RTK network end observation station network and PPP-RTK user end observation stations. The network end observation station network includes GNSS reference stations and a network data processing center. The user end observation stations include a time reference station and an ordinary user station. The method includes: acquiring GNSS observations collected by the GNSS reference stations and performing an undifferenced and uncombined PPP-RTK resolution to generate network end products; each of the user end observation stations performing an undifferenced and uncombined PPP-RTK resolution by using collected GNSS observations and the network end product to generate multi-GNSS receiver clock biases; and solving a combined inter-station clock bias by using the receiver clock biases of the ordinary user end observation stations and those of the time reference station serving also as user end.

Disclosed are a resource configuration method and apparatus, and a computer storage medium, being used for enabling, when a remaining minimum system information control resource set and an associated synchronization information block are in a time division multiplexing mode, the configuration of the remaining minimum system information control resource set to be more flexible, being applicable to more application scenarios. The resource configuration method comprises: determining that a remaining minimum system information control resource set (RMSI CORESET) and an associated synchronization information block (SS Block) occupy different symbols for transmission in a time division multiplexing mode; and determining the configuration parameters of the RMSI CORESET and the associated SS Block, the remaining minimum system information control resource sets associated with the SS Blocks in each SS Block burst set having identical configuration parameters.

Multiple examples are disclosed of SerDes transmitters and receivers. In one example, a transmitter comprises a mapping block to receive a clock signal and a two-bit data signal and to generate a plurality of pairs of digital values; a plurality of current steering blocks, each of the plurality of current steering blocks receiving one of the plurality of pairs of digital values to generate a pair of currents; a current summer and modulation block to receive the pair of currents from each of the plurality of current steering blocks to generate a differential output signal; wherein the differential output signal is a single frequency pulse amplitude modulated signal wherein the single frequency is a frequency of the clock signal.

This invention discloses an optimized method for TCMS and ATC time synchronization control. When ATC communication is normal, the time parameter information sent by ATC is valid, the ATP bypass switch is not in the bypass position, the time difference between the TCMS internal clock and the standard time sent by the ATC during normal communication exceeds 2 seconds, and the ATC heartbeat read in the current cycle differs from the called ATC heartbeat cache variable, and the ATC heartbeat read in the previous cycle also differs from the called ATC heartbeat cache variable, the TCMS internal clock is synchronized with the ATC time when all the above conditions are met. This method solves the problem of TCMS misinterpreting a change in ATC heartbeat when the gateway device is powered on again while the ATC heartbeat is stopped, causing the TCMS time to synchronize with the ATC time at the moment before the gateway power failure. This method has strong versatility and improves the reliability and stability of TCMS system clock control.

The method for synchronizing a first time domain (DMN1) with a second time domain (DMN2) of a system-on-chip (SoC) comprises: - detecting at least one periodic triggering event (TRG) generated in the first time domain (DMN1), the second time domain (DMN2) or in a third time domain (DMN3); - acquiring, at the times of said at least one triggering event (TRG), current timestamp values ​​(TS1, TS2) representative of the instantaneous states of the time domain(s) other than the triggering time domain; - comparing, in the third time domain (DMN3), between differential durations between current timestamp values ​​respectively acquired successively (PPS_1, PPS_2); and - synchronizing the second time domain (DMN2) with the first time domain (DMN1), from said comparison.

The present invention provides a signal synchronization device and a digital signal output device. A digital circuit counts a first frequency signal to generate a count value, generates an output voltage according to the count value, and an analog circuit generates a feedback signal according to the output voltage. A synchronization circuit samples the feedback signal according to a second frequency signal to generate a synchronization signal. A control circuit generates a voltage control signal according to the second frequency signal and the synchronization signal to control the digital circuit to stop counting the first frequency signal, wherein the frequency of the first frequency signal is lower than the frequency of the second frequency signal.

This application relates to the field of communication technologies, and discloses an alignment marker search method and apparatus, a system, and a computer-readable storage medium. The method includes: A first module receives a first data stream, where the first data stream is obtained by multiplexing a plurality of second data streams at a reference granularity, any second data stream includes an AM and data from at least one FEC codeword, and the reference granularity is a quantity of bits corresponding to n symbols included in the FEC codeword; obtains a first data segment from a first location in the first data stream at the reference granularity, and performs AM search on the first data segment. In the method, the reference granularity is the quantity of bits corresponding to the n symbols. Therefore, when a burst bit error occurs in the first data stream, a quantity of symbols affected by the burst bit error is small. In comparison with a data stream obtained through bit multiplexing, the first data stream in this method has higher tolerance to the burst bit error.

A method of a network exposure function (NEF) in a communication system is provided. The method comprising: receiving, from an application function (AF), a synchronization information including a valid time and a time domain for a time synchronization service; generating a synchronization activation request message based on the synchronization information; receiving, from a policy control function (PCF), a notification message indicating a PDU session; and transmitting, to at least one of a user equipment (UE) and a user plane function (UPF), the synchronization activation request message.

The invention relates to a semiconductor device and a semiconductor system for performing simultaneous bidirectional communication. A semiconductor device includes a serializer, a transmission circuit, and a reception circuit. The serializer is configured to generate transmission data from the first output data signal and the second output data signal based on the first transmission clock signal and the second transmission clock signal. The transmission circuit is configured to drive a node electrically coupled to the signal transmission line based on the transmission data. The receive circuit is configured to generate receive data based on the first receive clock signal and the second receive clock signal, the first output data signal and the second output data signal, and a voltage level of the node.

A system and method for combining and separating non-orthogonal signals. A transmitting component includes a set of generators of non-orthogonal signals and an adder for forming a group mixture. A receiving component includes a band-pass selective filter, an analog-to-digital converter and a calculator-solver for separating signals or channels. The system and method are designed to provide an almost ideal channels separation due to a new original group mixture processing procedure performed by the calculator-solver. The system and method provide significant increase in noise-immunity and the achievement of transmission rates that are exceeded the Shannon's Capacity of the group path.

Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.