724results about "Synchronisation information channels" patented technology

Accordingly, there are disclosed herein receivers and receiving methods that provide a graceful transition from PAM2 to PAM4 signaling. One illustrative method includes: negotiating a link speed having PAM4 signaling; performing adaption of at least one gain or filter coefficient during PAM2 signaling; switching to PAM4 detection before receiving PAM4 signaling; disabling said adaptation before said switching to PAM4 detection; detecting PAM4 signaling using at least one statistic of detected PAM4 symbols; and enabling said adaptation after PAM4 signaling is detected. Another illustrative method includes: negotiating a link speed having PAM4 signaling; adapting at least one of gain and filter coefficients during PAM2 signaling; monitoring for a change in at least one signal characteristic while performing PAM2 detection; and transitioning to PAM4 detection after detecting said change.

A communication device includes a first port that receives a signal related to a first time source, a second port that receives a signal related to a second time source, a switch that selects the first port or the second port, and processor circuitry configured to execute time synchronization processing by using a signal received via the selected port, detect an event that deteriorates accuracy of the time synchronization processing, transmit information related to a threat to the time synchronization processing to a communication management device when the event is detected, and receive information of recommend port from the communication management device, wherein, when the processor circuitry receives the information from the communication management device, the switch selects the first port or the second port based on a priority of the first time source, a priority of the second time source, and the information received from the communication management device.

In some examples, a system provides multi-chassis link aggregation by the first and second electronic devices that are part of a logical device supporting an MCLAG, where the first electronic device includes a first time clock, and the second electronic device includes a second time clock. The first and second time clocks perform, over a link between the first and second electronic devices of the logical device, a clock source selection process to select one of the first and second time clocks as a clock source and another one of the first and second time clocks as a clock sink as part of a time synchronization process in the system.

The present invention provides an efficient hardware architecture for an ORAN compliant clock synchronizer module of a combined centralized unit and a distributed unit (CCDU) for a 5G basement application required for processing L1, L2 and L3 scheduling of the network. The CCDU design may provide the functionality of a CU and a DU with single unit and can operate over wide temperature range. A single board approach of the CCDU make the CCDU more reliable and less costly. The CCDU can support different kinds of synchronization and can provide site alarms over dry contacts to equip with external alarm device.

The invention relates to the technical field of high-frequency multichannel synchronous transmission, in particular to a time domain reflection compensation design method for high-frequency signal transmission loss, which comprises the following steps of: 1, responding to a synchronous trigger signal to generate an active reflection reference signal with a determined time domain position; 2, aligning time marks between channels through cross-correlation operation; 3, extracting a reflection feature template of the channel from the alignment signal, and recognizing and eliminating crosstalk components through convolution operation with an adjacent channel template; 4, constructing a time-varying transfer function model according to the amplitude envelope attenuation characteristic and the carrier phase jump characteristic of the reflection characteristic template; and 5, generating a compensation filter based on the time-varying transfer function model, and verifying the compensation effect through secondary reflection. Through cross-correlation operation, accurate alignment of multi-channel signal time scales is realized, the time delay difference between different transmission channels is overcome, signal synchronization of each channel is ensured, and the beam forming precision is improved.

A method performed by a first device that has an internal clock. The method transmits a signal to a second device to share a clock of the first device. The method presents an extended reality (XR) environment and plays back audio content on the first electronic device, wherein the XR environment is also presented and the audio content is played back on the second electronic device The method generates timebase information that includes a first timebase that that defines a relationship between the shared clock and internal clock and a second timebase that defines a relationship between the first timebase and a playback state of the audio content. The method transmits the timebase information to the second device that synchronizes the playback state of the audio content in the second device, with the playback state of the audio content in the first device.

A receiving device, comprising: a clock generator circuit configured to generate a base clock signal; a counter configured to count cycles or edges of the base clock signal while a measurement pulse is received over a one-wire serial bus during a first transaction conducted over the one-wire serial bus, the measurement pulse having a pulse duration defined by a number of clock cycles of a transmitter clock signal; and a controller configured to adjust a count value of the counter when the counter is timing actuation of a trigger using a correction value that represents a difference between the cycles or edges of the base clock signal counted while the measurement pulse was being received and the number of clock cycles of the transmitter clock signal that defines the pulse duration.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

The present application provides a chip communication circuit, method and apparatus based on automatic clock synchronization. The method includes: determining clock synchronization information of a first battery management chip in response to a received control instruction; replacing a chip selection enable signal in the control instruction with a clock synchronization signal carrying the clock synchronization information of the first battery management chip to obtain a new control instruction; and transmitting the new control instruction to other battery management chips, so that the other battery management chips perform automatic clock synchronization based on the clock synchronization information carried in the new control instruction; where the other battery management chips are battery management chips among the multiple battery management chips except for the first battery management chip, and a daisy chain with a sinusoidal sawtooth waveform is used for isolated communication between different battery management chips.

Systems and methods for regaining phase synchronization between a CMTS core and an RPD, where the phase synchronization is regained over repeated temporal periods preferably divided between a first interval having a frequency adjustment of a first magnitude and a second interval having a frequency adjustment of a second magnitude.

A device according to the present disclosure includes: a PLL configured to modulate and output a frequency of a clock used to synchronize communication data in accordance with a regulation signal applied thereto, and a controller configured to generate the regulation signal according to a modulation waveform which is a successive form of a plurality of modulation wave units determined by a set modulation profiled, and apply the regulation signal to the PLL. The modulation wave unit is a signal whose sum of signal values during its time length becomes zero for the first time, and at least two successive modulation wave units among the plurality of modulation wave units differ from each other in at least one of the time length and the form of the signal.

Provided are a data transmission circuit system and a data reception circuit system, which use an edge of a pulse signal. The data transmission circuit system modulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a clock pulse signal and rising edges (or falling edges) of a data pulse signal. The data reception circuit system demodulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a recovered clock pulse signal and rising edges (or falling edges) of a data pulse signal.

The embodiment of the invention provides a multi-channel-oriented adaptive signal recovery method, device and equipment, which are applied to the technical field of communication, and the method comprises the following steps: carrying out frame synchronization on a data frame of each channel according to a unique identification code and a channel identifier in frame header information; performing quality evaluation and threshold comparison on effective information of each channel according to key information for guiding soft information combination in the frame header information, and adaptively matching a soft information combination mode according to a quality evaluation and threshold comparison result; merging according to a data frame synchronization result and the matched soft information merging mode to obtain an optimal channel receiving soft value; demodulating the channel receiving soft value, and calculating a log-likelihood ratio; and performing iterative decoding based on the log-likelihood ratio to recover an original signal. In this way, the compatible processing capacity of a communication system on signals with different qualities in a multi-channel transmission scene can be improved, the quality of soft information required by iterative decoding is improved, and the reliability of the communication system is improved.

Provided is a vehicle control system that includes a first electronic device and a second electronic device. The first electronic device includes: a first timer unit; a generation unit that generates time information indicating time counted by the first timer unit; and a first transmission unit that transmits the time information to the second electronic device, and also transmits, to the second electronic device, elapsed time information indicating elapsed time from the start of generation of the time information till transmission of the time information generated. The second electronic device includes: a second timer unit; a reception unit; and an adjustment unit that adjusts time counted by the second timer unit based on the time information and the elapsed time information received by the reception unit.

This disclosure is generally directed to a full-duplex transceiver including a primary circuit and a secondary circuit communicating using a clock signal of the primary circuit (e.g., a single clock signal). The primary circuit may include circuitry to generate and / or forward the clock signal to the secondary circuit. The secondary circuit may sample received data using the clock signal. Moreover, the secondary circuit may generate data, perform data processing operations, and / or transmit data using the clock signal of the primary circuit.

An apparatus and method for directly exposing, by user plane function / network side-time sensitive networking translator (UPF / NW-TT), event result information to time sensitive networking (TSN) or time sensitive communication time synchronization function (TSCTSF) through service interface (Nupf) in wireless communication system. A method of operating event processing for TSN or TSC includes: when policy control function (PCF) performs TSC event subscription, receiving TSC management and control information for direct reporting notification of event result from TSN-application function or TSCTSF and transmitting the TSC management and control information to session management function (SMF); regenerating the TSC management and control information and transmitting the regenerated TSC management and control information to UPF / NW-TT through N4 interface; and receiving the TSC management and control information from SMF, and when a corresponding event occurs, transmitting the TSC management information including the event result to a target in the control information through SBI.

The invention discloses a signal synchronization method and system based on a free space quantum key distribution system, and belongs to the technical field of key transmission. A high-power synchronous laser is adopted as a synchronous light source, a preset frame identification head is adopted to modulate a synchronous light signal, the modulated synchronous light signal serves as reference light and is sent to a receiving end, then synchronous coding is conducted on the synchronous signal received by a synchronous detector of the receiving end, and position information of the synchronous signal is generated and sent to a single photon detector of the receiving end; and performing sequence correspondence on the quantum signal received by the single-photon detector at the receiving end and the synchronizing signal according to the position information to finish signal synchronization. Frame synchronization is achieved through the synchronous laser, bit synchronization is achieved through synchronous coding and sequence correspondence, interference of an atmospheric channel can be effectively resisted, and the bit error rate of the system is reduced.

Techniques, methods and system, for synchronization of sparse data signals are disclosed, comprising mixing a serial stream of sparse data signals with a serial stream of synchronization signals, to thereby add redundancy to the serial stream of sparse data signals and enable clock regeneration from a serial stream of mixed signals produced by said mixing, emulating the serial stream of synchronization signals by applying the clock regeneration to the serial stream of mixed signals, and generating a stream of parallel synchronization signals having a frequency of the serial stream of synchronization signals, deserializing the serial stream of mixed signals into a stream of parallel mixed signals having a data rate lower than a data rate of the serial signal streams, and demixing the stream of parallel synchronization signals with the stream of parallel mixed signals and thereby removing the redundancy introduced by the mixing into the sparse data signals and generating a parallel stream of demixed signals substantially synchronized with said synchronization signals.

A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.

This disclosure provides in a first aspect, an apparatus (412a) for wireless communications including a first clock loop (420) comprising a first plurality of latches (422, 424) generating a first plurality of clock signals (I, Q) with a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) with a corresponding second plurality of phases, wherein the first clock loop is configured to be enabled or disabled based on a first enable signal, and wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

The embodiment of the invention relates to the technical field of clock synchronization, and discloses a clock synchronization method and system, electronic equipment and a storage medium. The clock synchronization method comprises the steps that clock frequencies of a master chip and a slave chip are synchronized, and the master chip and the slave chip interact through an inter-chip communication channel; determining a clock calibration value, wherein the clock calibration value is used for representing a clock difference between the master chip and the slave chip; and according to the clock calibration value, carrying out clock calibration so as to synchronize the clocks of the master chip and the slave chip. The synchronization precision of the master chip and the slave chip is improved at least while additional interfaces are not introduced to the master chip and the slave chip.

The invention discloses a cable sensor network time service compensation method, device and equipment and a medium, and belongs to the technical field of network time service, and the method comprises the following steps: collecting process historical data of a cable network actual error compensation system, and taking error data of a satellite second clock and a crystal oscillator second clock as an initial sample; aggregating the initial samples to obtain aggregated samples under each step size scale; constructing an error feature vector containing an aggregation sample of the current scale and an accumulated error of the current time point information; performing modeling on the error feature vectors by using a Gaussian-like process regression model to obtain a Gaussian-like process regression model of each step size scale; error estimation values of all step size scales are generated in sequence, and a time service error estimation value of the current moment is obtained by combining the difference error estimation values of the lowest step size scale and the highest step size scale; and compensating the accumulated error of the crystal oscillator clock based on the time service error estimation value at the current moment. According to the invention, the synchronization precision and practicability are improved.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

The circuits and methods described herein provide a technical solution for technical issues for USB links. To reduce or eliminate the effects associated with the entry of a USB link into a low power mode, an initial link acquisition may be performed while disabling spread spectrum clock (SSC) modulation. After initial link acquisition, SSC modulation may be dynamically enabled at a later stage. This delayed activation of the retimer provides improved performance compared to a solution in which SSC modulation is continually activated, including reducing the complexity of the timing training process and enabling faster USB link re-establishment. This reduced link acquisition period may enable the system to enter the power saving mode more frequently and may reduce the latency involved in exiting the power saving mode. This may maintain or improve the overall USB transmission speed, and may reduce USB-related power consumption for USB-connected devices.

A system includes a plurality of semiconductor chips that are stacked on top of each other and that include first and second semiconductor chips. The first semiconductor chip includes a clock signal generating circuit, a transmitting circuit, and a receiving circuit. The clock signal generating circuit generates a clock signal and a delayed version of the clock signal. The transmitting circuit transmits a first data signal in response to the clock signal. The receiving circuit receives a second data signal in response to the delayed version of the clock signal. For example, the receiving circuit receives the delayed version of the clock signal at substantially the same time that the transmitting circuit receives the clock signal.

The embodiments of the present application provide a method, device and system for sending precision information. The method includes: a first network element switches from a tracking state to a holding state; the first network element sends status information to a second network element, and the status information includes the precision information of the first network element in the holding state. Through the above method, the second network element can obtain the status information of the first network element in the holding state, and perform clock synchronization with the first network element or with the second network element according to the status information, ultimately achieving more accurate clock synchronization and further improving the performance of the clock synchronization system.

Some embodiments relate to a communication network comprising at least one receiver system optically coupled to a plurality of transmitter systems for transmission of synchronization signals generated by the at least one receiver system to the plurality of transmitter systems over a unidirectional synchronization channel. The at least one receiver system configured to embed into the synchronization signals thereby generated additional data indicative of an internal time count thereof for synchronization of transmission of data / signals from each one of the plurality of transmitter systems to said at least one receiver system over a sparse data / signals unidirectional communication channel.

In an alignment marker search method, a first module receives a first data stream, where the first data stream is obtained by multiplexing a plurality of second data streams at a reference granularity, any second data stream includes an AM and data from at least one FEC codeword, and the reference granularity is a quantity of bits corresponding to n symbols included in the FEC codeword; obtains a first data segment from a first location in the first data stream at the reference granularity; and performs AM search on the first data segment. The reference granularity is the quantity of bits corresponding to the n symbols. Therefore, when a burst bit error occurs in the first data stream, a quantity of symbols affected by the burst bit error is small.

The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data transmission rate than a 4G communication system such as LTE. The present invention relates to a method for an application function (AF) entity for time sensitive communication (TSC) in a wireless communication system, the method comprising the steps of: obtaining first delay-related information on a time sensitive network (TSN); obtaining second delay-related information on a 5th generation system (5GS); and transmitting, to a policy control function (PCF) entity, a quality of service (QoS)-related request based on the first delay-related information and the second delay-related information.