134results about "Synchronisation information channels" patented technology

Some embodiments relate to a communication network comprising at least one receiver system optically coupled to a plurality of transmitter systems for transmission of synchronization signals generated by the at least one receiver system to the plurality of transmitter systems over a unidirectional synchronization channel. The at least one receiver system configured to embed into the synchronization signals thereby generated additional data indicative of an internal time count thereof for synchronization of transmission of data / signals from each one of the plurality of transmitter systems to said at least one receiver system over a sparse data / signals unidirectional communication channel.

The invention discloses a multi-path frequency-adjustable signal generation system based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of signal generation. The system comprises an adjustable frequency signal generation module, an FPGA register read-write control module, an SPI communication module and a top layer module. The top layer module adopts a generate block statement to realize batch instantiation of a multi-path signal output module, a positioning register mechanism is introduced, and a group of register resources are used for controlling a multi-path output channel, so that the problem of register resource waste caused by repeated instantiation of the module in the traditional design is effectively solved. According to the system, remote configuration of an FPGA internal register by a CPU is achieved through an SPI communication interface, and the frequency-adjustable signal generation module supports independent adjustment of parameters such as frequency, high pulse width and low pulse width. And when the positioning register is matched with a specific output channel and the data updating flag bit is valid, the system accurately sends the characteristic parameters to the corresponding channel, so that the accuracy of each path of signal parameters is ensured. According to the method, the code redundancy and the development time are remarkably reduced, and the system maintainability is improved.

A system for clock synchronization, including a quantum control processor (QCP) and digital-analog inter-converters. Each digital-analog inter-converter includes a frequency conversion module and a signal synchronization module. The signal synchronization module includes a D flip-flop (DFF). The QCP generates a signal for global synchronization (Sync_GLB) and reference clock signals (REFCLKs), and the Sync GLB and the corresponding REFCLK to the frequency conversion module, and transmits the Sync GLB to the signal synchronization module. The frequency conversion module performs frequency conversion on the REFCLK to obtain a target clock signal, generates an instruction for signal synchronization according to the signal for global synchronization, and transmits the instruction for signal synchronization and the target clock signal to the signal synchronization module. The signal synchronization module performs signal synchronization on the target clock signal via the DFF, based on the signal for global synchronization. The present disclosure further provides a method for controlling signal synchronization. The DFF relocks the signal for global synchronization to the target clock signal having a low jitter, reducing signal delay and improving precision of signal synchronization.

The present invention provides an effective hardware architecture for a combined aggregation and distribution unit (CCDU) ​​ORAN-compliant clock synchronizer module for 5G foundation applications required to handle L1, L2, and L3 schedules of the network. The CCDU design can achieve CU and DU functionality in a single unit and can operate over a wide temperature range. The single board approach of the CCDU makes the CCDU more reliable and less costly. The CCDU can support different types of synchronization and can provide site alarms over dry contacts for accommodating external alarm devices.

Systems, methods, and circuits for performing bidirectional communication using an edge time in a signal are provided. In one example, a method involves receiving a common signal on a signal line between one device and another. The common signal comprises a series of signal periods, and each signal period includes a first edge of a first type and a second edge of a second type, different from the first type. In each signal period of the series of signal periods, information to be communicated by the other device is determined at least based on the determined time of the first edge, and a time for a subsequent second edge with respect to the signal period is determined based on information to be communicated to the other device.The subsequent second edge is generated at the selected time in a subsequent signal period of the series of signal periods.

A time transfer method based on undifferenced and uncombined PPP-RTK is applied to a time transfer system including a PPP-RTK network end observation station network and PPP-RTK user end observation stations. The network end observation station network includes GNSS reference stations and a network data processing center. The user end observation stations include a time reference station and an ordinary user station. The method includes: acquiring GNSS observations collected by the GNSS reference stations and performing an undifferenced and uncombined PPP-RTK resolution to generate network end products; each of the user end observation stations performing an undifferenced and uncombined PPP-RTK resolution by using collected GNSS observations and the network end product to generate multi-GNSS receiver clock biases; and solving a combined inter-station clock bias by using the receiver clock biases of the ordinary user end observation stations and those of the time reference station serving also as user end.

Disclosed are a resource configuration method and apparatus, and a computer storage medium, being used for enabling, when a remaining minimum system information control resource set and an associated synchronization information block are in a time division multiplexing mode, the configuration of the remaining minimum system information control resource set to be more flexible, being applicable to more application scenarios. The resource configuration method comprises: determining that a remaining minimum system information control resource set (RMSI CORESET) and an associated synchronization information block (SS Block) occupy different symbols for transmission in a time division multiplexing mode; and determining the configuration parameters of the RMSI CORESET and the associated SS Block, the remaining minimum system information control resource sets associated with the SS Blocks in each SS Block burst set having identical configuration parameters.

Multiple examples are disclosed of SerDes transmitters and receivers. In one example, a transmitter comprises a mapping block to receive a clock signal and a two-bit data signal and to generate a plurality of pairs of digital values; a plurality of current steering blocks, each of the plurality of current steering blocks receiving one of the plurality of pairs of digital values to generate a pair of currents; a current summer and modulation block to receive the pair of currents from each of the plurality of current steering blocks to generate a differential output signal; wherein the differential output signal is a single frequency pulse amplitude modulated signal wherein the single frequency is a frequency of the clock signal.

This invention discloses an optimized method for TCMS and ATC time synchronization control. When ATC communication is normal, the time parameter information sent by ATC is valid, the ATP bypass switch is not in the bypass position, the time difference between the TCMS internal clock and the standard time sent by the ATC during normal communication exceeds 2 seconds, and the ATC heartbeat read in the current cycle differs from the called ATC heartbeat cache variable, and the ATC heartbeat read in the previous cycle also differs from the called ATC heartbeat cache variable, the TCMS internal clock is synchronized with the ATC time when all the above conditions are met. This method solves the problem of TCMS misinterpreting a change in ATC heartbeat when the gateway device is powered on again while the ATC heartbeat is stopped, causing the TCMS time to synchronize with the ATC time at the moment before the gateway power failure. This method has strong versatility and improves the reliability and stability of TCMS system clock control.

The method for synchronizing a first time domain (DMN1) with a second time domain (DMN2) of a system-on-chip (SoC) comprises: - detecting at least one periodic triggering event (TRG) generated in the first time domain (DMN1), the second time domain (DMN2) or in a third time domain (DMN3); - acquiring, at the times of said at least one triggering event (TRG), current timestamp values ​​(TS1, TS2) representative of the instantaneous states of the time domain(s) other than the triggering time domain; - comparing, in the third time domain (DMN3), between differential durations between current timestamp values ​​respectively acquired successively (PPS_1, PPS_2); and - synchronizing the second time domain (DMN2) with the first time domain (DMN1), from said comparison.

A method of a network exposure function (NEF) in a communication system is provided. The method comprising: receiving, from an application function (AF), a synchronization information including a valid time and a time domain for a time synchronization service; generating a synchronization activation request message based on the synchronization information; receiving, from a policy control function (PCF), a notification message indicating a PDU session; and transmitting, to at least one of a user equipment (UE) and a user plane function (UPF), the synchronization activation request message.

A system and method for combining and separating non-orthogonal signals. A transmitting component includes a set of generators of non-orthogonal signals and an adder for forming a group mixture. A receiving component includes a band-pass selective filter, an analog-to-digital converter and a calculator-solver for separating signals or channels. The system and method are designed to provide an almost ideal channels separation due to a new original group mixture processing procedure performed by the calculator-solver. The system and method provide significant increase in noise-immunity and the achievement of transmission rates that are exceeded the Shannon's Capacity of the group path.

Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.

A receiving device, comprising: a clock generator circuit configured to generate a base clock signal; a counter configured to count cycles or edges of the base clock signal while a measurement pulse is received over a one-wire serial bus during a first transaction conducted over the one-wire serial bus, the measurement pulse having a pulse duration defined by a number of clock cycles of a transmitter clock signal; and a controller configured to adjust a count value of the counter when the counter is timing actuation of a trigger using a correction value that represents a difference between the cycles or edges of the base clock signal counted while the measurement pulse was being received and the number of clock cycles of the transmitter clock signal that defines the pulse duration.

An example method includes: recording, at a first sensor device, (i) a first informational signal as detected at the first sensor device; and (ii) a reference signal as detected at the first sensor device; recording, at a second sensor device (i) a second informational signal as detected at the second sensor device; and (ii) the reference signal as detected at the second sensor device; determining a time shift between the reference signal as recorded by the first sensor device and the reference signal as recorded by the second sensor device; and applying the determined time shift to the second informational signal to time-align the first informational signal and the second informational signal.

A communication link initialization method includes that a master node sends a first information frame to a slave node. The first information frame includes first synchronization information. The slave node implements synchronization with the master node based on the first synchronization information. The slave node sends a second information frame to the master node. The second information frame includes second synchronization information. The master node implements synchronization with the slave node based on the second synchronization information. The master node sends a third information frame to the slave node. The third information frame is used to indicate a first training information frame. The slave node trains a link between the master node and the slave node based on the third information frame. The slave node sends a fourth information frame to the master node.

An eye margin test method includes receiving an analog input signal, receiving an analog input signal, generating a recovery clock signal based on the digital input signal, delaying the recovery clock signal by adjusting a first delay control code, obtaining a first delay margin code based on the delayed recovery clock signal, delaying the digital input signal by adjusting a second delay control code, obtaining a second delay margin code based on the delayed digital input signal, and obtaining an eye margin code by adding the first delay margin code and the second delay margin code.

The application discloses a data alignment method and system, an electronic device and a storage medium, and relates to the field of data processing. The method is applied to a transmission link with multiple data channels, and comprises the following steps: for each data channel, at different delay times, detecting whether the sampling edge of a clock signal is in a stable region of a transmission signal based on a preset training code; if yes, and the latched value obtained based on the sampling edge at the current delay time belongs to a first set, recording the detection result as a first flag; otherwise, recording the detection result as a second flag; sorting the first flags of the data channels according to the order of the delay times to obtain a first continuous interval formed by continuous first flags; obtaining a common delay time interval as a first common interval; and delaying the clock signal based on the delay time at the center of the first common interval to correct the phase deviation of any data channel in the transmission link.

This invention relates to an electrical device. An embodiment of the electrical device includes: a first circuit board having a first signal processing device; and a second circuit board having a second signal processing device. The first signal processing device has a processor, a main communication interface, and a peripheral device communication interface. The main communication interface is used for data communication with the second signal processing device. The second signal processing device has a slave communication interface and a second peripheral device communication interface. The slave communication interface is used for data communication with the first signal processing device. The main communication interface transmits a first interrupt to the processor, and the second peripheral device communication interface transmits a second interrupt to the slave communication interface. Thus, stable and scalable data communication can be performed.

The present disclosure relates to a 5G or pre-5G communication system to be provided for supporting a data transmission rate higher than that of a 4G communication system such as LTE. The method according to the present disclosure is a time synchronization method for transmitting time sensitive networking (TSN) data in a session management function (SMF) device of a mobile communication system, and may comprise a step of determining a time interval for updating time sensitive communications assistance information (TSCAI), and providing the determined time interval to respective nodes of the mobile communication system.

Embodiments include systems and methods for processing sensor data and generating operational instructions of hardware of egos (e.g., autonomous vehicles, robots). The ego includes any number of machine-learning architectures, often neural network architectures, for processing sensor data and recognizing the environment around the ego and making decisions on the ego's behavior. The neural network architectures of the ego ingest sensor data and execute any number of operations related to a particular domain or task, such as object recognition or path planning, using the sensor data. A graph partitioner is trained to assign functions in the software of the neural networks and the sensor data to certain hardware processing units. Several compilers are used to generate the instructions based upon the assigned type of processing unit.

A time synchronization subdevice includes a periodic data receiver that receives periodic data transmitted periodically from a time synchronization reference device, an acquirer that acquires first priority information indicating a first priority assigned to the time synchronization reference device, a first priority transmitter that transmits the first priority information to another time synchronization subdevice, a second priority information transmitter that transmits, when the periodic data is interrupted, transmission information indicating a second priority assigned to the time synchronization subdevice, a second priority information receiver that receives reception information indicating a second priority assigned to a device different from the time synchronization subdevice, and a distributor that distributes, when the periodic data is interrupted and the second priority indicated with the transmission information is higher than the second priority indicated with the reception information, time measured by a clocking unit as new shared time to the another time synchronization subdevice.

The circuit includes a plurality of signal processing units, each of which outputs a clock signal and output data based on input data and synchronized with the clock signal to a corresponding track from among the plurality of tracks. A first circuit, acting on a reference track selection signal to choose a reference track from the plurality of tracks, selects an output clock signal corresponding to the reference track from among the output clock signals output by each of the plurality of signal processing units and outputs this signal to each of the plurality of signal processing units. Each of the plurality of signal processing units then compares and outputs the clock signal and output data based either on a reference clock signal or on the clock signal output by another signal processing unit from among the plurality of signal processing units.

A multi-chip module (MCM includes a substrate and first and second integrated circuit chips disposed on the substrate. The second IC chip includes transceiver circuitry configured to communicate with the first IC chip. The transceiver circuitry includes transmit circuitry having an inverter circuit to generate a first signal for transmission to the first IC chip along a signaling link. The signaling link includes a line termination impedance. Receiver circuitry includes a receiver circuit to receive a second signal from the first IC chip along the signaling link concurrently with transmission of the first signal along the signaling link. Hybrid circuitry is coupled to the transmit circuitry and to the receiver circuitry. The hybrid circuitry is configured to cancel a received component of the first signal. The hybrid circuitry includes a replica termination impedance that is configured in an open state.

Systems and methods provide for a low complexity and low latency implementation for cellular fronthauling. At a baseband unit ("BBU"), data packets received from a data network are converted into analog data signals, which are in turn converted into analog optical signals that are optically amplified and sent over a hollow core fiber ("HCF") -based fronthaul link(s) to a remote radio unit(s) ("RRU(s)"). At the RRU(s), the analog optical signals are converted into analog data signals that are sent over the air as radio frequency ("RF") signals via an antenna(s). In some cases, the analog data signals are filtered and amplified prior to RF signal transmission. RF signals that are received, via antennas, at an RRU are conversely filtered and converted into analog optical signals, transmitted over the HCF-based fronthaul link(s) to the BBU, where the analog optical signals are converted into data packets for transmission over the data network.

Some methods for triggering cameras in an autonomous vehicle (AV). The methods include receiving, by a programmable circuit, Generalized Precision Time Protocol (gPTP) information for synchronizing the programmable circuit with a gPTP Grand Master (GM); generating, by the programmable circuit, a pulse per second (PPS) signal having a peri-od of one second based on the gPTP time information; generating, by the programmable circuit, a synchronizing signal having a period less than the period of the PPS signal; generating, by the programmable circuit, a triggering signal based on the PPS signal, wherein a period of the triggering signal is the same as the period of the synchronizing signal; and sending, by the programmable circuit and to one or more cameras of an AV, the triggering signal for triggering the one or more cameras to capture one or more images. Systems and computer program products are also provided.

The application discloses a kind of data transmission processing method and system of semiconductor production equipment, it is related to semiconductor data transmission technical field, including, establishing the alias mapping of accessory equipment and main equipment and setting mutual signal gate control rule, process stage window is mapped as network time slot generation time slot scheduling table, establishment release theme, complete timing synchronization, output synchronization ready identification;According to the set of tracing keys and the gap list, when serial number is continuous, seal the current process stage window tracing record and backfill token trigger next window scroll, when there is gap, call guide frame switching and execute gap retransmission in the time slot of next window, update time slot scheduling table, alias mapping table and corresponding release theme.The application forms the set of tracing keys and the gap list by comparing window serial number and reply handle, and when detecting gap, it is executed minimum back-off retransmission and dynamic time slot self-healing update, so that data transmission process has self-recovery characteristics.

An operating method of an electronic device is disclosed. An electronic device according to an embodiment of the present disclosure may comprise: a communication unit including a first interface and a second interface; and a processor electrically connected to the communication unit via the first interface or the second interface, wherein the processor: requests clock information of the communication unit from the communication unit via the first interface; receives clock information of the communication unit from the communication unit via the first interface; receives an interrupt signal and first time information on a generation time point of the interrupt signal from the communication unit via the second interface; and generates clock information of the processor on the basis of the clock information of the communication unit and the first time information.

The present application provides a chip communication circuit, method and apparatus based on automatic clock synchronization. The method includes: determining clock synchronization information of a first battery management chip in response to a received control instruction; replacing a chip selection enable signal in the control instruction with a clock synchronization signal carrying the clock synchronization information of the first battery management chip to obtain a new control instruction; and transmitting the new control instruction to other battery management chips, so that the other battery management chips perform automatic clock synchronization based on the clock synchronization information carried in the new control instruction; where the other battery management chips are battery management chips among the multiple battery management chips except for the first battery management chip, and a daisy chain with a sinusoidal sawtooth waveform is used for isolated communication between different battery management chips, thereby solving the problem of high communication power consumption and unsynchronized clocks of battery management chips in existing daisy chain communication methods.

The present application provides methods and apparatuses for implementing clock extension based on an integrated circuit bus IIC. The present application additionally provides a clock extension indication signal line between an IIC master device and a control device in a communication control system. The IIC master device sends a first notification to the control device through the clock extension indication signal line to enable clock extension, so that the control device maintains a pin of a slave device SCL in a low-level state, to suspend data transmission. In the absence of a second notification sent by the IIC master device to the control device through the clock extension indication signal line to cancel clock extension, even if the specified period of the SCL clock cycle ends, the slave device SCL pin connected to the slave device SCL will not be controlled to be in a high impedance state as it would be in the conventional IIC data transmission mechanism. Instead, the SCL pin will be maintained at a low level until the second notification is received, breaking the limitation of the existing data transmission mechanism and implementing triggering of clock extension mechanism by the IIC master device.