368results about "Synchronisation information channels" patented technology

Accordingly, there are disclosed herein receivers and receiving methods that provide a graceful transition from PAM2 to PAM4 signaling. One illustrative method includes: negotiating a link speed having PAM4 signaling; performing adaption of at least one gain or filter coefficient during PAM2 signaling; switching to PAM4 detection before receiving PAM4 signaling; disabling said adaptation before said switching to PAM4 detection; detecting PAM4 signaling using at least one statistic of detected PAM4 symbols; and enabling said adaptation after PAM4 signaling is detected. Another illustrative method includes: negotiating a link speed having PAM4 signaling; adapting at least one of gain and filter coefficients during PAM2 signaling; monitoring for a change in at least one signal characteristic while performing PAM2 detection; and transitioning to PAM4 detection after detecting said change.

The invention relates to the technical field of high-frequency multichannel synchronous transmission, in particular to a time domain reflection compensation design method for high-frequency signal transmission loss, which comprises the following steps of: 1, responding to a synchronous trigger signal to generate an active reflection reference signal with a determined time domain position; 2, aligning time marks between channels through cross-correlation operation; 3, extracting a reflection feature template of the channel from the alignment signal, and recognizing and eliminating crosstalk components through convolution operation with an adjacent channel template; 4, constructing a time-varying transfer function model according to the amplitude envelope attenuation characteristic and the carrier phase jump characteristic of the reflection characteristic template; and 5, generating a compensation filter based on the time-varying transfer function model, and verifying the compensation effect through secondary reflection. Through cross-correlation operation, accurate alignment of multi-channel signal time scales is realized, the time delay difference between different transmission channels is overcome, signal synchronization of each channel is ensured, and the beam forming precision is improved.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

This disclosure is generally directed to a full-duplex transceiver including a primary circuit and a secondary circuit communicating using a clock signal of the primary circuit (e.g., a single clock signal). The primary circuit may include circuitry to generate and / or forward the clock signal to the secondary circuit. The secondary circuit may sample received data using the clock signal. Moreover, the secondary circuit may generate data, perform data processing operations, and / or transmit data using the clock signal of the primary circuit.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

A system includes a plurality of semiconductor chips that are stacked on top of each other and that include first and second semiconductor chips. The first semiconductor chip includes a clock signal generating circuit, a transmitting circuit, and a receiving circuit. The clock signal generating circuit generates a clock signal and a delayed version of the clock signal. The transmitting circuit transmits a first data signal in response to the clock signal. The receiving circuit receives a second data signal in response to the delayed version of the clock signal. For example, the receiving circuit receives the delayed version of the clock signal at substantially the same time that the transmitting circuit receives the clock signal.

Some embodiments relate to a communication network comprising at least one receiver system optically coupled to a plurality of transmitter systems for transmission of synchronization signals generated by the at least one receiver system to the plurality of transmitter systems over a unidirectional synchronization channel. The at least one receiver system configured to embed into the synchronization signals thereby generated additional data indicative of an internal time count thereof for synchronization of transmission of data / signals from each one of the plurality of transmitter systems to said at least one receiver system over a sparse data / signals unidirectional communication channel.

In an alignment marker search method, a first module receives a first data stream, where the first data stream is obtained by multiplexing a plurality of second data streams at a reference granularity, any second data stream includes an AM and data from at least one FEC codeword, and the reference granularity is a quantity of bits corresponding to n symbols included in the FEC codeword; obtains a first data segment from a first location in the first data stream at the reference granularity; and performs AM search on the first data segment. The reference granularity is the quantity of bits corresponding to the n symbols. Therefore, when a burst bit error occurs in the first data stream, a quantity of symbols affected by the burst bit error is small.

The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data transmission rate than a 4G communication system such as LTE. The present invention relates to a method for an application function (AF) entity for time sensitive communication (TSC) in a wireless communication system, the method comprising the steps of: obtaining first delay-related information on a time sensitive network (TSN); obtaining second delay-related information on a 5th generation system (5GS); and transmitting, to a policy control function (PCF) entity, a quality of service (QoS)-related request based on the first delay-related information and the second delay-related information.

A clock signal in a clock distribution network is transmitted using network packets with the clock signal embedded within a bit of the network packets. The clock signal is adjusted to account for propagation delay in transmitting the clock signal throughout a clock distribution network. The propagation delay is computed using a round-trip packet. When a previous clock signal is received, a timer is set to a local clock's estimate of when the next clock signal will occur minus the propagation delay to the downstream device. When this timer expires, the clock signal is sent to the downstream device, which will allow it to arrive at the downstream device at the same time as the next clock signal is received on the local device.

In a first aspect, the disclosure provides an apparatus (412a) for wireless communication, comprising: a first clock loop (420) comprising a first plurality of latches (422, 424) that generate a first plurality of clock signals (I, Q) having a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) having a corresponding second plurality of phases, where the first clock loop is configured to be enabled or disabled based on the first enable signal and the second clock loop is configured to be enabled or disabled based on the second enable signal. And wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

Systems and methods are disclosed for phase calibration between clock and data lanes at a data link receiver. In calibration mode, matching signals are transmitted over the clock and data lanes, and a phase offset is measured at the receiver. A phase shifter in one signal path is adjusted to a first phase to obtain a desired phase offset. For operation mode, the phase shifter is set based on the first phase. Embodiments measure phase offset using an XOR gate and use a phase interpolator as the phase shifter. Embodiments with multiple data lanes apply coarse calibration to a shared clock lane relative to a first data lane, and similar fine calibration to other data lanes. Calibration provides optimum signal-to-noise ratio or timing margin, enabling high transmission speeds at relatively low power. Variations are disclosed.

One example includes a data alignment system. The system includes a bit alignment detector configured to detect bit-wise alignment of transmission signals provided from respective transmit channels based on a receiver signal provided by a remote receiver. The transmission signals can be combined to generate the receiver signal via a data combiner in the remote receiver. The system also includes a data alignment detector configured to detect alignment of data in each of the transmission signals. The system further includes a delay controller configured to provide at least one delay signal to at least one of the transmit channels to selectively delay a respective at least one of the transmission signals in response to at least one of the bit alignment detector failing to detect the bit-wise alignment of the transmission signals and the data alignment detector failing to detect alignment of the data in each of the transmission signals.

Aspects of this technical solution can generate, according to one or more first environment metrics, a three-dimensional (3D) model including a first surface corresponding to one or more physical ways through a physical environment, the one or more first environment metrics indicative of boundaries of the one or more physical ways, generate, according to one or more second environment metrics, one or more geometric two-dimensional (2D) objects on the first surface, the second environment metrics indicative of the one or more physical ways, identify, according to one or more viewpoint metrics indicative of cameras of a physical object configured to move along the one or more physical ways, one or more viewpoints oriented to capture corresponding portions of the 3D model, and render, from the one or more corresponding portions of the 3D model, one or more 2D images each corresponding to respective ones of the viewpoints.

The present invention provides an efficient hardware architecture for an ORAN compliant clock synchronizer module of a combined centralized unit and a distributed unit (CCDU) for a 5G basement application required for processing L1, L2 and L3 scheduling of the network. The CCDU design may provide the functionality of a CU and a DU with single unit and can operate over wide temperature range. A single board approach of the CCDU make the CCDU more reliable and less costly. The CCDU can support different kinds of synchronization and can provide site alarms over dry contacts to equip with external alarm device.

The present invention provides a communication signal timing error compensation method and device, which includes: processing a signal sent by a transmitter through upsampling, a shaping filter, a transmission channel, a matched filter, and downsampling in sequence to obtain time domain samples of the signal; convolving the filter coefficients of the shaping filter with the filter coefficients of the matched filter to obtain filter coefficients of the time domain samples, and extracting the effective filter coefficients of each time domain sample; constructing a matrix based on the effective filter coefficients of the time domain samples, extracting a submatrix from the matrix based on the number of delayed samples corresponding to each timing error, and calculating the timing compensation coefficient for each timing error based on the submatrix; querying the timing compensation coefficient corresponding to the actual timing error of the current signal, performing timing compensation on the current signal based on the timing compensation coefficient corresponding to the actual timing error, and obtaining a timing-compensated signal. The present invention has a simple structure and low computational complexity, effectively reducing computational complexity and storage space.

A wireless communication system, according to one embodiment of the present invention, comprises: a first communication module; and at least one second communication module wirelessly connected to the first communication module, wherein the first communication module is wirelessly connected to the second communication module to which driving power is applied from the same power source as that of the first communication module.

A system includes a first integrated circuit coupled to a printed circuit board (PCB) and a second integrated circuit coupled to the PCB. The system further includes a ground referenced signaling (GRS) link coupled between the first integrated circuit and the second integrated circuits through the PCB. Unencoded data is transmitted on the GRS link according to a memory coherence protocol.

The invention discloses a multi-path frequency-adjustable signal generation system based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of signal generation. The system comprises an adjustable frequency signal generation module, an FPGA register read-write control module, an SPI communication module and a top layer module. The top layer module adopts a generate block statement to realize batch instantiation of a multi-path signal output module, a positioning register mechanism is introduced, and a group of register resources are used for controlling a multi-path output channel, so that the problem of register resource waste caused by repeated instantiation of the module in the traditional design is effectively solved. According to the system, remote configuration of an FPGA internal register by a CPU is achieved through an SPI communication interface, and the frequency-adjustable signal generation module supports independent adjustment of parameters such as frequency, high pulse width and low pulse width. And when the positioning register is matched with a specific output channel and the data updating flag bit is valid, the system accurately sends the characteristic parameters to the corresponding channel, so that the accuracy of each path of signal parameters is ensured. According to the method, the code redundancy and the development time are remarkably reduced, and the system maintainability is improved.

A video packaging and origination service can include one or more encoder components that receive content for encoding and transmitting to requesting entities. During the operation of the encoder components, a management service associated with the video packaging and origination service can receive information related to updates or modifications to the encoder components. Responsive to the information, the management service can instantiate and configure an updated encoder. Once the updated encoder component is instantiated and configured, both the updated and target encoder components receive content for streaming, encode content and generating encoding content. Additionally, the updated encoder component can initiate a notification to the target encoder component that a handover will be occurring and begin a negotiation process identifying a handover event. Based on the negotiated handover event, the target encoder component can illustratively cease operation upon evaluation and detection of the handover event.

A communication system, apparatus, method, and one or more non-transitory computer-readable storage devices that implement integration of perception and communication employ the following steps: transmitting a radio frequency (RF) signal. The RF signal includes one or more communication symbols for communication and one or more perceived signal components for perceiving an object, the RF signal including timing information of the one or more perceived signal components.

A system for clock synchronization, including a quantum control processor (QCP) and digital-analog inter-converters. Each digital-analog inter-converter includes a frequency conversion module and a signal synchronization module. The signal synchronization module includes a D flip-flop (DFF). The QCP generates a signal for global synchronization (Sync_GLB) and reference clock signals (REFCLKs), and the Sync GLB and the corresponding REFCLK to the frequency conversion module, and transmits the Sync GLB to the signal synchronization module. The frequency conversion module performs frequency conversion on the REFCLK to obtain a target clock signal, generates an instruction for signal synchronization according to the signal for global synchronization, and transmits the instruction for signal synchronization and the target clock signal to the signal synchronization module. The signal synchronization module performs signal synchronization on the target clock signal via the DFF, based on the signal for global synchronization. The present disclosure further provides a method for controlling signal synchronization. The DFF relocks the signal for global synchronization to the target clock signal having a low jitter, reducing signal delay and improving precision of signal synchronization.

A system includes a first coupled to a printed circuit board (PCB) and a second device coupled to the PCB. The system further includes a link coupled with the first device, the second device, and the PCB. The link includes a clock lane associated with associated with transmitting a clock signal and one or more data lanes corresponding to the clock lane, where the link is configured to transmit ground referenced signaling (GRS).

A signal driving circuit includes a first driver, a control signal generation circuit, and a second driver. The first driver is configured to generate a first transmission signal based on an input signal and a clock signal. The control signal generation circuit is configured to generate a delay clock signal by delaying the clock signal and to generate a first control clock signal and a second control clock signal with different pulse widths than the pulse width of the delay clock signal. The second driver is configured to generate a second transmission signal, based on the first transmission signal and the first and second control clock signals.

The subject-matter of the present disclosure provides a transmitter for a master clock of an audio system. The transmitter comprises an input configured to receive a message to be sent to a receiver of an audio device of the audio system and clock frequency information of a clock signal for synchronising the audio device; a data stream generator configured to determine a data stream based on the message; a pulse shaper configured to generate an encoded clock signal in the form of a rectangular wave having an initiating edge timing based on the clock frequency and a terminating edge timing being earlier than or later than a half cycle of the encoded clock signal depending on a bit value of the data stream; and an output configured to transmit the encoded clock signal to the receiver.

An embodiment includes a forward data receiving device that demodulates and receives an Amplitude Shift Keying (ASK) modulation signal, and includes: an input module configured to receive the ASK modulation signal as an input; a resonance regulating rectifier module configured to regulate and rectify an input voltage of the ASK modulation signal on the basis of Pulse Width Modulation (PWM) according to a preset target voltage, and apply a regulated voltage through an output transistor; and a demodulation module configured to demodulate the ASK modulation signal according to a trend in a change of the input voltage compared to the regulated voltage, wherein the resonance regulating rectifier module includes a comparison unit configured to generate a gate signal for controlling on / off of the output transistor, and generate a sample signal for demodulating the ASK modulation signal.

The present invention discloses a data synchronization method based on a phased array system, which relates to the technical field of data synchronization. The data synchronization method based on a phased array system includes the following steps: system determination of a digital phased array system, system clock synchronization, system acquisition synchronization, DDC module synchronization, and system data transmission synchronization. The data synchronization method based on a phased array system facilitates problem troubleshooting. Whether in design or actual use, if a problem occurs, the problem can be quickly found by step-by-step troubleshooting according to the modularization. This can effectively improve the efficiency of system data synchronization and optimize the data processing efficiency of related systems. At the same time, the modularization setting can reduce equipment costs and improve the convenience of equipment maintenance. The corresponding modules can be deleted according to the complexity of the system. For a relatively simple system, removing a certain synchronization step in the middle will not affect the overall synchronization function.

The present invention provides an effective hardware architecture for a combined aggregation and distribution unit (CCDU) ​​ORAN-compliant clock synchronizer module for 5G foundation applications required to handle L1, L2, and L3 schedules of the network. The CCDU design can achieve CU and DU functionality in a single unit and can operate over a wide temperature range. The single board approach of the CCDU makes the CCDU more reliable and less costly. The CCDU can support different types of synchronization and can provide site alarms over dry contacts for accommodating external alarm devices.

Systems, methods, and circuits for performing bidirectional communication using an edge time in a signal are provided. In one example, a method involves receiving a common signal on a signal line between one device and another. The common signal comprises a series of signal periods, and each signal period includes a first edge of a first type and a second edge of a second type, different from the first type. In each signal period of the series of signal periods, information to be communicated by the other device is determined at least based on the determined time of the first edge, and a time for a subsequent second edge with respect to the signal period is determined based on information to be communicated to the other device.The subsequent second edge is generated at the selected time in a subsequent signal period of the series of signal periods.