535results about "Synchronisation information channels" patented technology

Accordingly, there are disclosed herein receivers and receiving methods that provide a graceful transition from PAM2 to PAM4 signaling. One illustrative method includes: negotiating a link speed having PAM4 signaling; performing adaption of at least one gain or filter coefficient during PAM2 signaling; switching to PAM4 detection before receiving PAM4 signaling; disabling said adaptation before said switching to PAM4 detection; detecting PAM4 signaling using at least one statistic of detected PAM4 symbols; and enabling said adaptation after PAM4 signaling is detected. Another illustrative method includes: negotiating a link speed having PAM4 signaling; adapting at least one of gain and filter coefficients during PAM2 signaling; monitoring for a change in at least one signal characteristic while performing PAM2 detection; and transitioning to PAM4 detection after detecting said change.

A communication device includes a first port that receives a signal related to a first time source, a second port that receives a signal related to a second time source, a switch that selects the first port or the second port, and processor circuitry configured to execute time synchronization processing by using a signal received via the selected port, detect an event that deteriorates accuracy of the time synchronization processing, transmit information related to a threat to the time synchronization processing to a communication management device when the event is detected, and receive information of recommend port from the communication management device, wherein, when the processor circuitry receives the information from the communication management device, the switch selects the first port or the second port based on a priority of the first time source, a priority of the second time source, and the information received from the communication management device.

In some examples, a system provides multi-chassis link aggregation by the first and second electronic devices that are part of a logical device supporting an MCLAG, where the first electronic device includes a first time clock, and the second electronic device includes a second time clock. The first and second time clocks perform, over a link between the first and second electronic devices of the logical device, a clock source selection process to select one of the first and second time clocks as a clock source and another one of the first and second time clocks as a clock sink as part of a time synchronization process in the system.

The invention relates to the technical field of high-frequency multichannel synchronous transmission, in particular to a time domain reflection compensation design method for high-frequency signal transmission loss, which comprises the following steps of: 1, responding to a synchronous trigger signal to generate an active reflection reference signal with a determined time domain position; 2, aligning time marks between channels through cross-correlation operation; 3, extracting a reflection feature template of the channel from the alignment signal, and recognizing and eliminating crosstalk components through convolution operation with an adjacent channel template; 4, constructing a time-varying transfer function model according to the amplitude envelope attenuation characteristic and the carrier phase jump characteristic of the reflection characteristic template; and 5, generating a compensation filter based on the time-varying transfer function model, and verifying the compensation effect through secondary reflection. Through cross-correlation operation, accurate alignment of multi-channel signal time scales is realized, the time delay difference between different transmission channels is overcome, signal synchronization of each channel is ensured, and the beam forming precision is improved.

A method performed by a first device that has an internal clock. The method transmits a signal to a second device to share a clock of the first device. The method presents an extended reality (XR) environment and plays back audio content on the first electronic device, wherein the XR environment is also presented and the audio content is played back on the second electronic device The method generates timebase information that includes a first timebase that that defines a relationship between the shared clock and internal clock and a second timebase that defines a relationship between the first timebase and a playback state of the audio content. The method transmits the timebase information to the second device that synchronizes the playback state of the audio content in the second device, with the playback state of the audio content in the first device.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

Systems and methods for regaining phase synchronization between a CMTS core and an RPD, where the phase synchronization is regained over repeated temporal periods preferably divided between a first interval having a frequency adjustment of a first magnitude and a second interval having a frequency adjustment of a second magnitude.

A device according to the present disclosure includes: a PLL configured to modulate and output a frequency of a clock used to synchronize communication data in accordance with a regulation signal applied thereto, and a controller configured to generate the regulation signal according to a modulation waveform which is a successive form of a plurality of modulation wave units determined by a set modulation profiled, and apply the regulation signal to the PLL. The modulation wave unit is a signal whose sum of signal values during its time length becomes zero for the first time, and at least two successive modulation wave units among the plurality of modulation wave units differ from each other in at least one of the time length and the form of the signal.

Provided are a data transmission circuit system and a data reception circuit system, which use an edge of a pulse signal. The data transmission circuit system modulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a clock pulse signal and rising edges (or falling edges) of a data pulse signal. The data reception circuit system demodulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a recovered clock pulse signal and rising edges (or falling edges) of a data pulse signal.

This disclosure is generally directed to a full-duplex transceiver including a primary circuit and a secondary circuit communicating using a clock signal of the primary circuit (e.g., a single clock signal). The primary circuit may include circuitry to generate and / or forward the clock signal to the secondary circuit. The secondary circuit may sample received data using the clock signal. Moreover, the secondary circuit may generate data, perform data processing operations, and / or transmit data using the clock signal of the primary circuit.

Techniques, methods and system, for synchronization of sparse data signals are disclosed, comprising mixing a serial stream of sparse data signals with a serial stream of synchronization signals, to thereby add redundancy to the serial stream of sparse data signals and enable clock regeneration from a serial stream of mixed signals produced by said mixing, emulating the serial stream of synchronization signals by applying the clock regeneration to the serial stream of mixed signals, and generating a stream of parallel synchronization signals having a frequency of the serial stream of synchronization signals, deserializing the serial stream of mixed signals into a stream of parallel mixed signals having a data rate lower than a data rate of the serial signal streams, and demixing the stream of parallel synchronization signals with the stream of parallel mixed signals and thereby removing the redundancy introduced by the mixing into the sparse data signals and generating a parallel stream of demixed signals substantially synchronized with said synchronization signals.

The embodiment of the invention relates to the technical field of clock synchronization, and discloses a clock synchronization method and system, electronic equipment and a storage medium. The clock synchronization method comprises the steps that clock frequencies of a master chip and a slave chip are synchronized, and the master chip and the slave chip interact through an inter-chip communication channel; determining a clock calibration value, wherein the clock calibration value is used for representing a clock difference between the master chip and the slave chip; and according to the clock calibration value, carrying out clock calibration so as to synchronize the clocks of the master chip and the slave chip. The synchronization precision of the master chip and the slave chip is improved at least while additional interfaces are not introduced to the master chip and the slave chip.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

A system includes a plurality of semiconductor chips that are stacked on top of each other and that include first and second semiconductor chips. The first semiconductor chip includes a clock signal generating circuit, a transmitting circuit, and a receiving circuit. The clock signal generating circuit generates a clock signal and a delayed version of the clock signal. The transmitting circuit transmits a first data signal in response to the clock signal. The receiving circuit receives a second data signal in response to the delayed version of the clock signal. For example, the receiving circuit receives the delayed version of the clock signal at substantially the same time that the transmitting circuit receives the clock signal.

Some embodiments relate to a communication network comprising at least one receiver system optically coupled to a plurality of transmitter systems for transmission of synchronization signals generated by the at least one receiver system to the plurality of transmitter systems over a unidirectional synchronization channel. The at least one receiver system configured to embed into the synchronization signals thereby generated additional data indicative of an internal time count thereof for synchronization of transmission of data / signals from each one of the plurality of transmitter systems to said at least one receiver system over a sparse data / signals unidirectional communication channel.

In an alignment marker search method, a first module receives a first data stream, where the first data stream is obtained by multiplexing a plurality of second data streams at a reference granularity, any second data stream includes an AM and data from at least one FEC codeword, and the reference granularity is a quantity of bits corresponding to n symbols included in the FEC codeword; obtains a first data segment from a first location in the first data stream at the reference granularity; and performs AM search on the first data segment. The reference granularity is the quantity of bits corresponding to the n symbols. Therefore, when a burst bit error occurs in the first data stream, a quantity of symbols affected by the burst bit error is small.

The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data transmission rate than a 4G communication system such as LTE. The present invention relates to a method for an application function (AF) entity for time sensitive communication (TSC) in a wireless communication system, the method comprising the steps of: obtaining first delay-related information on a time sensitive network (TSN); obtaining second delay-related information on a 5th generation system (5GS); and transmitting, to a policy control function (PCF) entity, a quality of service (QoS)-related request based on the first delay-related information and the second delay-related information.

A clock signal in a clock distribution network is transmitted using network packets with the clock signal embedded within a bit of the network packets. The clock signal is adjusted to account for propagation delay in transmitting the clock signal throughout a clock distribution network. The propagation delay is computed using a round-trip packet. When a previous clock signal is received, a timer is set to a local clock's estimate of when the next clock signal will occur minus the propagation delay to the downstream device. When this timer expires, the clock signal is sent to the downstream device, which will allow it to arrive at the downstream device at the same time as the next clock signal is received on the local device.

The invention provides a signal data synchronization method for a multi-microphone array, and the method comprises the steps: generating a digital synchronization signal through a main control processing unit, generating an analog synchronization signal through a digital-to-analog converter, and transmitting the analog synchronization signal to each microphone array unit; each microphone array unit obtains a respective synchronizing signal and transmits the synchronizing signal to the main control processing unit; the re-sampler adjusts the sampling interval of the synchronizing signal, and the phase discriminator detects the phase difference between the re-sampled synchronizing signal and the local high-frequency synchronizing signal and feeds back the phase difference to the re-sampler until the re-sampled synchronizing signal and the local high-frequency synchronizing signal have the same frequency and keep a stable phase difference; and performing mobile cross-correlation on the resampled synchronizing signal and a local high-frequency synchronizing signal in the delay estimator, and compensating delay deviation through a delayer. And the main control processing unit performs synchronization processing by using the local synchronization signal and the received return synchronization signal, and further adjusts the microphone signal of the array unit to achieve strict sample synchronization.

In a first aspect, the disclosure provides an apparatus (412a) for wireless communication, comprising: a first clock loop (420) comprising a first plurality of latches (422, 424) that generate a first plurality of clock signals (I, Q) having a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) having a corresponding second plurality of phases, where the first clock loop is configured to be enabled or disabled based on the first enable signal and the second clock loop is configured to be enabled or disabled based on the second enable signal. And wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

Systems and methods are disclosed for phase calibration between clock and data lanes at a data link receiver. In calibration mode, matching signals are transmitted over the clock and data lanes, and a phase offset is measured at the receiver. A phase shifter in one signal path is adjusted to a first phase to obtain a desired phase offset. For operation mode, the phase shifter is set based on the first phase. Embodiments measure phase offset using an XOR gate and use a phase interpolator as the phase shifter. Embodiments with multiple data lanes apply coarse calibration to a shared clock lane relative to a first data lane, and similar fine calibration to other data lanes. Calibration provides optimum signal-to-noise ratio or timing margin, enabling high transmission speeds at relatively low power. Variations are disclosed.

The embodiments of the present application relate to the technical field of clock synchronization. Disclosed are a clock synchronization method and system, and an electronic device and a storage medium. The clock synchronization method comprises: synchronizing a clock frequency of a master chip with that of a slave chip, wherein the master chip interacts with the slave chip by means of an inter-chip communication channel; determining a clock calibration value, wherein the clock calibration value is used for representing a clock difference between the master chip and the slave chip; and performing clock calibration on the basis of the clock calibration value, so as to synchronize a clock of the master chip with that of the slave chip. Therefore, an improvement in the synchronization precision of a master chip and slave chip is at least facilitated while no additional interface is introduced onto the master chip and the slave chip.

The invention provides a clock extension implementation method and device based on an integrated circuit bus (IIC). According to the invention, the clock extension indication signal line is added between the IIC master device and the control device in the communication control system, and the IIC master device sends the first notification to the control device through the clock extension indication signal line to start clock extension, so that the control device maintains the SCL pin of the slave device to be in a low-level state to pause data transmission, and the communication control efficiency is improved. Under the condition that a second notice sent by the IIC master device to the control device through the clock extension indication signal line to cancel the clock extension is not received, even if the specified time period of the SCL clock period is ended, the SCL pin is maintained at a low level instead of being controlled to be in a high-resistance state in a conventional IIC data transmission mechanism, so that the SCL pin is prevented from being in a high-resistance state, and the SCL pin is prevented from being in a high-resistance state. According to the invention, the limitation of the current data transmission mechanism is broken, and the clock extension mechanism is triggered by the IIC master device.

A device according to the present disclosure includes: a PLL configured to modulate and output a frequency of a clock used to synchronize communication data in accordance with a regulation signal applied thereto, and a controller configured to generate the regulation signal according to a modulation waveform which is a successive form of a plurality of modulation wave units determined by a set modulation profiled, and apply the regulation signal to the PLL. The modulation wave unit is a signal whose sum of signal values during its time length becomes zero for the first time, and at least two successive modulation wave units among the plurality of modulation wave units differ from each other in at least one of the time length and the form of the signal.

One example includes a data alignment system. The system includes a bit alignment detector configured to detect bit-wise alignment of transmission signals provided from respective transmit channels based on a receiver signal provided by a remote receiver. The transmission signals can be combined to generate the receiver signal via a data combiner in the remote receiver. The system also includes a data alignment detector configured to detect alignment of data in each of the transmission signals. The system further includes a delay controller configured to provide at least one delay signal to at least one of the transmit channels to selectively delay a respective at least one of the transmission signals in response to at least one of the bit alignment detector failing to detect the bit-wise alignment of the transmission signals and the data alignment detector failing to detect alignment of the data in each of the transmission signals.

Aspects of this technical solution can generate, according to one or more first environment metrics, a three-dimensional (3D) model including a first surface corresponding to one or more physical ways through a physical environment, the one or more first environment metrics indicative of boundaries of the one or more physical ways, generate, according to one or more second environment metrics, one or more geometric two-dimensional (2D) objects on the first surface, the second environment metrics indicative of the one or more physical ways, identify, according to one or more viewpoint metrics indicative of cameras of a physical object configured to move along the one or more physical ways, one or more viewpoints oriented to capture corresponding portions of the 3D model, and render, from the one or more corresponding portions of the 3D model, one or more 2D images each corresponding to respective ones of the viewpoints.

Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.

An apparatus and method for directly exposing, by user plane function / network side-time sensitive networking translator (UPF / NW-TT), event result information to time sensitive networking (TSN) or time sensitive communication time synchronization function (TSCTSF) through service interface (Nupf) in wireless communication system. A method of operating event processing for TSN or TSC includes: when policy control function (PCF) performs TSC event subscription, receiving TSC management and control information for direct reporting notification of event result from TSN-application function or TSCTSF and transmitting the TSC management and control information to session management function (SMF); regenerating the TSC management and control information and transmitting the regenerated TSC management and control information to UPF / NW-TT through N4 interface; and receiving the TSC management and control information from SMF, and when a corresponding event occurs, transmitting the TSC management information including the event result to a target in the control information through SBI.

The present invention provides an efficient hardware architecture for an ORAN compliant clock synchronizer module of a combined centralized unit and a distributed unit (CCDU) for a 5G basement application required for processing L1, L2 and L3 scheduling of the network. The CCDU design may provide the functionality of a CU and a DU with single unit and can operate over wide temperature range. A single board approach of the CCDU make the CCDU more reliable and less costly. The CCDU can support different kinds of synchronization and can provide site alarms over dry contacts to equip with external alarm device.