7389results about "Electronic circuit testing" patented technology

The invention discloses a PCBA circuit board welding spot detection method based on multi-modal data fusion, and relates to the technical field of electronic manufacturing quality detection.The PCBA circuit board welding spot detection method comprises the steps that a distributed sensing network is constructed, multi-modal data are collected, welding spot information is obtained in an omnibearing mode, and time-space alignment of the multi-modal data is carried out; performing feature extraction on the multi-modal data, dynamically weighting each modal feature through an attention mechanism, and highlighting key defect characterization; a welding spot spatial topological graph is constructed by using a graph neural network, and a spatial relationship between welding spots is modeled. By integrating optical, X-Ray, thermal, mechanics, electricity and other multi-dimensional data, the information limitation of single-mode detection is broken through, the complementation of different mode data is utilized, the attention mechanism is combined to dynamically weight each mode feature, the complex defect is accurately identified, the graph neural network is utilized to model the welding spot space topological relation, the associated defect is further captured, and the defect detection accuracy is improved. And the defect classification accuracy is improved.

The invention discloses an integrated circuit chip test system based on an AI algorithm, and relates to the technical field of integrated circuit chip testing, the integrated circuit chip test system comprises a chip test platform, the chip test platform is in communication connection with the following modules: a data acquisition module, which is used for collecting historical test data from existing integrated circuit chip test equipment, and sending the collected historical test data to the chip test platform; carrying out preprocessing and integration on the chip test data set to obtain a chip test data set; and the model training optimization module is used for analyzing the chip test data set, learning the relationship between the chip performance and the test vector, and training a test vector AI optimization model. According to the method, by analyzing historical test data and automatically generating the optimized test vector, a redundant item-by-item test process in a traditional test is avoided, key test nodes are accurately positioned through the test vector AI optimization model, and unnecessary test steps are reduced, so that the test time is remarkably shortened, and the test efficiency is improved.

The invention provides a power management chip pin state intelligent detection method and system. The method comprises the steps that temperature difference quantity is input into a gradient heat conduction compensation structure, and compensation current opposite to a temperature gradient vector is generated based on temperature field distribution in the copper-based composite material; superposing and coupling the voltage fluctuation signal and the compensation current to generate a reference voltage signal; performing frequency component separation processing on the reference voltage signal, and extracting electromagnetic interference characteristic data in a frequency component; performing time sequence correlation on the electromagnetic interference characteristic data and the temperature distribution data, dynamically adjusting an interference suppression parameter through closed-loop control, and acting the adjusted interference suppression parameter on an interference suppression process of a reference voltage signal to generate a pin state detection signal; and detecting the pin state of the power management chip according to the pin state detection signal. According to the invention, the pin voltage stability and the state detection precision of the power management chip are improved.

The invention provides a method and system for preparing a high-temperature anti-aging test board for chip testing, and relates to the technical field of data energy storage and resource scheduling, and the method comprises the steps: designing a schematic circuit diagram and a PCB wiring scheme; a test plate is made of a high-temperature resistant material; bare board verification, electrical performance verification, program setting verification, high temperature verification and junction temperature measurement verification are carried out; using data is recorded, ultrasonic cleaning and drying are carried out, and a performance evaluation model is established through a hardware management system to judge whether maintenance or replacement is needed. According to the invention, the accuracy of chip testing in a high-temperature environment is improved, and the service life of the test board is prolonged.

The invention relates to the technical field of chip testing, and discloses an LED driving chip testing method, device and equipment and a storage medium, and the method comprises the steps: carrying out the multi-point temperature excitation and constant-current output synchronous collection of an LED driving chip, and obtaining electrothermal coupling test data; performing thermal resistance network decomposition on the temperature field in the chip to obtain temperature distribution characteristic parameters; performing nonlinear function fitting on the temperature-constant current coupling relation to obtain an electrothermal coupling transfer coefficient; performing four-dimensional coupling calculation on the temperature distribution characteristic parameter and the electrothermal coupling transfer coefficient to obtain four-dimensional coupling response characteristic data; and partial differential sensitivity calculation is carried out based on the four-dimensional coupling response characteristic data, and an electrothermal coupling sensitivity analysis result is obtained.According to the method, the problem of test errors caused by time desynchrony in a traditional separated temperature-current test is solved, quantitative sensitivity analysis of electrothermal coupling parameters is achieved, and the sensitivity of the electrothermal coupling parameters is improved. Therefore, the test accuracy of the LED driving chip is improved.

The invention provides a circuit board electrical performance test and diagnosis method, which comprises the following steps of: constructing a structured process-electrical data set by collecting process parameters such as etching time, pressing temperature, drilling precision, copper foil thickness and the like and electrical test indexes such as impedance deviation, leakage current, signal attenuation and the like; screening key process variables by adopting mutual information analysis and a maximum correlation-minimum redundancy criterion; through modeling of a three-layer causal diagram and a structural equation, quantitative influence evaluation of process parameters on electrical performance and fault types is realized; when a fault is detected, the system can automatically perform reverse reasoning, identify a main manufacturing deviation item and generate attribution diagnosis and process optimization suggestions, so that the accuracy of fault diagnosis and the pertinence of process adjustment are improved, and the fault occurrence rate is reduced and the product quality is improved.

The invention discloses a method for diagnosing an IGBT open-circuit fault and a current sensor fault of a T-type three-level inverter, belongs to the technical field of inverter fault diagnosis, and is used for solving the problems of diagnosis and positioning when a three-level T-type inverter IGBT switch tube and a sensor have faults. Comprising the following steps: classifying and marking and numbering fault types of an open-circuit fault of a T-type three-level inverter IGBT and a fault of a current sensor; fault samples are collected and divided into a training set and a test set according to the proportion of 7: 3; a TCN-LSTM-SelfAction fault diagnosis model is constructed, and model training is carried out by using the training set; the trained model is used for evaluating the accuracy of fault type diagnosis of the training set and the test set. According to the diagnosis method, the fault types and the fault positions of the IGBT open-circuit fault and the current sensor fault can be diagnosed at the same time, the TCN and the LSTM are selected to be combined, local information and global relation of fault features can be captured at the same time, and meanwhile, the performance of a model is improved by combining a self-attention mechanism in the LSTM, and the accuracy is improved.

Provided is an integrated probe pin that includes an upper plunger having a first tip adapted to come into contact with a circuit to be inspected to transmit and receive electrical signals to and from the circuit to be inspected; a lower plunger having a second tip adapted to come into contact with an inspection circuit to transmit and receive the electrical signals to and from the inspection circuit; and an elastic part located between the upper plunger and the lower plunger to elastically support the upper plunger and the lower plunger, wherein the upper plunger, the lower plunger, and the elastic part are manufactured as an integral body using 3D printing and made of one or more metal materials.

The invention provides a semiconductor chip automatic test optimization system, and belongs to the technical field of electrical variable measurement. Comprising an acquisition module used for establishing an electrical variable time sequence arranged according to a time sequence, a drift analysis module used for calculating a short-time fluctuation amplitude value, a long-term drift slope and a high-frequency noise amplitude value based on the impedance time sequence arranged according to the time sequence, and a contact judgment module. The evaluation module is used for constructing a contact impedance coefficient based on a short-time fluctuation amplitude value, a long-term drift slope and a high-frequency noise amplitude value in a jth sliding window, and evaluating and optimizing the contact impedance coefficient, and the data marking module is used for marking electrical variable measurement data corresponding to a test channel which is evaluated to be instable in contact as low confidence. According to the system, the ith test channel of the temperature sensor chip can be tested more accurately, the short-time fluctuation amplitude value, the long-term drift slope and the high-frequency noise amplitude value are calculated at the same time, multi-source data participates, and the test accuracy is improved.

The invention relates to the technical field of semiconductor parallel testing, and provides a semiconductor device parallel testing method and system based on a multi-channel IC testing machine. The method comprises the following steps: acquiring a parallel test task set, and extracting key test characteristics of each task; calculating test conflicts among the tasks, and generating a task conflict matrix; outputting a channel distance matrix according to the test machine channel position; defining a conflict scheduling objective function, jointly solving a distance matrix and a conflict matrix, and outputting a task channel mapping relation; and loading the task set according to the mapping relation to execute the test. The technical problems of parallel test conflicts and unreasonable test resource allocation caused by difference of voltage, current, frequency or drive circuit characteristics of different test tasks are solved, and under the premise of guaranteeing the test accuracy and the system stability, through collaborative optimization mapping of the conflict matrix and the distance matrix, the test efficiency is improved. And the resource allocation of the multi-channel IC test machine is optimized, the interference conflict between tasks is reduced, and the parallel test efficiency is improved.

The invention discloses a printed circuit board withstand voltage detection and evaluation method, which comprises the following steps: in the whole withstand voltage detection process, aiming at different process batches and environments, acquiring electrical signals, process parameters, environment variables and multi-modal visual data, and carrying out time sequence synchronization marking and standardized preprocessing; extracting multi-source features by using a feature coding algorithm, and establishing a multi-mode distribution model covering signal mutation, visual defects and working condition anomalies; through cross-modal feature fusion and a time sequence causal inference model, an abnormal event causal relationship graph is automatically constructed, and a voltage withstanding failure root cause chain is identified and positioned; according to the method, the efficient structured management of the detection data, the accurate traceability of the abnormal reasons and the cross-batch analysis are realized, and the capability of diagnosing and preventing the withstand voltage abnormality of the printed circuit board is remarkably improved.

The invention provides a semiconductor chip defect detection positioning method and system, and relates to the technical field of semiconductor chip detection, and the method comprises the steps: obtaining an original image and electrical test data; forming a defect candidate area based on local density analysis; variational mode decomposition is carried out on the electrical data, and electrical characteristic abnormal points are marked; mapping the image features to an electrical characteristic space and calculating mutual information values to determine defect points; and calculating the distribution and path of a diffusion field and determining the severity of the defect. According to the invention, accurate positioning and severity evaluation of chip defects are realized, and the detection efficiency and accuracy are improved.

The invention provides a multi-probe array real-time pressure optimization and control method for wafer testing, and relates to the technical field of semiconductor testing, and the method comprises the steps: collecting real-time pressure data and a wafer stress limit value, building an initial distribution state, calculating the contact area and angle through displacement, determining a stress concentration factor, and carrying out the pressure correction, calculating strain rate distribution to identify a sensitive area to perform pressure compensation, monitoring a stress-strain ratio to identify a microcrack initiation point to determine an optimal pressurization parameter, and performing real-time monitoring and early warning. According to the invention, the damage risk in the wafer testing process can be reduced, and the testing precision and the yield can be improved.

The invention discloses a method and system for testing a direct-current offset compensation circuit of an optical transceiving driving chip and a medium, and relates to the technical field of photoelectric integrated circuit testing, and the method comprises the following steps: carrying out the time alignment of a test waveform and an offset track of the optical transceiving driving chip, extracting the phase dislocation amount and the amplitude kick amount between beats, and carrying out the calculation of the phase offset amount and the amplitude kick amount; a continuous change result is mapped into a time sequence conflict observation band which is used for identifying a beat overlapping region; and on the basis of the phase dislocation trend of the time sequence conflict observation band, determining a beat overlapping point of the direct current offset compensation loop, and generating an overlapping beat index according to the duration of amplitude kick and the polarity direction for identifying an interference node. According to the method, millisecond-level beat observation and microsecond-level overlapping identification are realized in a test stage, interference nodes are accurately extracted, a coupling strength graph is constructed, and by combining beat rearrangement and an energy unloading strategy, nonlinear oscillation is inhibited, oscillation and overload risks are reduced, eye pattern quality and error code stability are improved, and chip test precision and robustness are enhanced.

The invention relates to the field of chip testing, in particular to a chip signal integrity test analysis method, device and equipment and a storage medium. The method comprises the following steps: extracting a chip performance index based on a chip design requirement document; performing saturation frequency excitation setting based on the chip performance index to generate an excitation test signal; performing a multi-port signal excitation test and parallel signal sampling based on the excitation test signal to generate a high signal-to-noise ratio response data set; obtaining a chip layout design file; performing chip communication link analysis on the chip layout design file, and constructing communication line layout data; performing signal mapping and waveform quality evaluation on the communication line layout data based on the high signal-to-noise ratio response data set to obtain a node signal distortion rate; and performing signal integrity quantization and theoretical signal integrity score comparison based on the node signal distortion rate, and marking a fault node. According to the invention, the chip testing efficiency is improved, and the signal abnormal part of the chip is accurately and efficiently detected.

The invention discloses a method and system for testing the electrical performance of a semiconductor chip, and the method comprises the steps: building a mapping relation between dielectric loss and loss frequency through obtaining the dielectric loss data, internal material characteristics and dynamic load power factors of the chip under each frequency band, recognizing a loss abnormal region, and analyzing the influence of the loss abnormal region on the performance of the chip; correcting test data by adopting a minimum mean square error algorithm, and optimizing the impedance of the power supply network and the dynamic switching characteristic of a functional module; calculating the breakdown voltage distribution of each layer in the chip, identifying a high-voltage risk region, optimizing the voltage distribution by using a gradient descent algorithm, and dynamically adjusting the working voltage and current; power factor fluctuation is analyzed through a sliding window algorithm, an abnormal area is identified, a power factor is optimized through a PID algorithm, and the working state and transient response of a chip in a dynamic load are improved. According to the method, the problems of nonlinearity of high-frequency dielectric loss, non-uniform breakdown voltage distribution and unstable power factor response under a dynamic load are solved, and comprehensive and accurate evaluation and optimization of chip performance are realized.

The invention provides a chip test calibration device and method, and relates to the technical field of chip test. The chip test calibration device comprises a base, a cooling air supply device, a control device, a chip and two groups of manipulators. According to the invention, the chip is heated by setting different temperature environments in stages, and the multi-point synchronous temperature measurement of each temperature stage is combined, so that the heat distribution on the surface of the chip can be comprehensively captured, and the calibration error caused by non-uniform temperature or a detection blind area is avoided; the chip is automatically circulated among the heating station, the detection station and the cooling station, synchronous processing and continuous detection of multiple chips are achieved, the single-batch detection period is greatly shortened, the surface of the chip is directly blown by directional airflow, an efficient air return channel is matched, the temperature of the chip can be rapidly reduced after detection is completed, idle waiting for station switching is reduced, and the overall production efficiency is improved.

The invention relates to a fault diagnosis method, system and device for a chip test equipment control circuit, and the method comprises the steps: obtaining an operation parameter set of the chip test equipment control circuit, carrying out the abnormal threshold matching, and obtaining a fault classification result; performing power supply dynamic signal tracking on the chip test equipment control circuit based on the fault classification result to obtain power supply deviation data, and extracting a static offset set of the chip test equipment control circuit; performing internal failure association on the power supply deviation data and the static offset set, and performing peripheral failure association identification on the chip test equipment control circuit to obtain a diagnosis data set; and constructing a hierarchical fault tree according to the diagnosis data set, and performing peripheral root cause matching on the chip test equipment control circuit to obtain fault positioning information. According to the invention, the propagation path and the influence range of the fault can be comprehensively analyzed, and the fault positioning accuracy is improved.

The invention is suitable for the technical field of chip testing, and particularly relates to a continuous fault analysis method based on voltage glitches, and the method comprises the steps: obtaining the offline data of a sample chip, and providing basic data for the subsequent determination of a voltage glitch parameter cluster. And according to the offline data of the sample chip, determining a voltage burr parameter cluster corresponding to the sample chip, and based on the voltage burr parameter cluster, controlling burr injection equipment to perform voltage burr injection on the sample chip in an offline state so as to provide a precondition for subsequent fault data acquisition. Fault collection data of the sample chip is obtained, abnormal data generated when the chip operates in the simulated fault environment is collected, and a core basis is provided for continuous fault analysis. The continuous fault analysis is performed on the sample chip based on the fault acquisition data, the sample analysis result of the sample chip is determined, the fault analysis efficiency is improved, the test cost is reduced, and the universality of the test result is improved.

The invention provides an automatic chip aging test method and system and a medium, and relates to the technical field of semiconductors, and the method comprises the steps: after a type identifier of a to-be-tested chip is identified, calling an aging test parameter group corresponding to the type identifier, and carrying out the aging test of the to-be-tested chip through the aging test parameter group, after the key electrical parameters of the to-be-tested chip in the aging test process are collected, comparison is carried out to obtain a comparison result, when the comparison result exceeds a preset threshold range, abnormal recording operation is automatically carried out, and the current aging test link of the to-be-tested chip is terminated. By automatically recording abnormal information and terminating the aging process, full-automatic closed-loop processing from data acquisition and analysis to decision and control is realized, the test efficiency is improved, test equipment and samples are effectively protected, resource waste and misjudgment risks are reduced, and the problems of low aging trend identification precision and slow response speed are solved.

The embodiment of the invention provides a wafer testing device and testing method, and belongs to the technical field of wafer testing. The wafer testing device comprises an MEMS probe chip installed and connected on a testing machine, and a testing position used for fixing a tested chip. A test contact of a probe of the MEMS probe chip is in contact with a PAD of a tested chip during testing, and the MEMS probe chip is used for collecting a detection signal of the tested chip; wherein a probe of the MEMS probe chip is integrated in the MEMS probe chip based on a cantilever beam type; and the test machine is used for generating a test result corresponding to the tested chip based on the detection signal of the tested chip. The MEMS probe chip in the scheme of the invention adopts a modular design, is convenient to quickly replace, reduces the maintenance cost and time, and provides a better solution for the test requirements of high-frequency and high-density packaged chips.

A probe card mounted in an of electronic device testing apparatus is described, having a probe head housing a plurality of contact probes, each having a first end portion which abuts onto contact pads of a device under test, a main board and a connected intermediate board which provides a distance spatial transformation between contact pads made on opposite faces thereof. The intermediate board is a space transformer which includes a plurality of modules that are plate-shaped and coplanar, and structurally and functionally independent from each other. Each module has a first face facing towards the probe head and a first plurality of contact pads whereonto respective second end portions of the contact probes abut and an opposite second face facing towards the main board. The second face has a second plurality of contact pads connected to the first plurality of contact pads.

The invention relates to a large current tester for charging pile chip detection, which comprises a base and a cover body, and is characterized in that the top of the base is provided with a positioning mechanism for positioning a chip; a testing mechanism for detecting a chip is mounted at the bottom of the base, the testing mechanism comprises a testing plate and a plurality of probe modules electrically connected with the testing plate, each probe module comprises a heat conduction block, a connecting piece and probe elastic pieces distributed in an array, the connecting piece is sequentially connected with the heat conduction block and the probe elastic pieces in series, and the probe elastic pieces are electrically connected with the testing plate. The probe elastic sheet is arranged on the inner side of the heat conduction block to form a probe module; a pressing assembly for fixing the chip is arranged on the inner side of the cover body, and a control assembly for driving the pressing assembly to be close to the base is arranged at the top of the cover body. During testing, the probe elastic sheets are elastically deformed, stable contact between each probe elastic sheet and the corresponding pin can be guaranteed, the probe elastic sheets are distributed independently, it is guaranteed that the probe elastic sheets have high conduction efficiency in the detection process, and the stability and precision of large-current testing are guaranteed.

The invention belongs to the field of chip testing, and provides a test mode control circuit and method and a chip. The circuit comprises a data clock width identification module, a data time sequence generation module and a test control module, wherein the data time sequence generation module is respectively connected with the data clock width identification module and the test control module. The data clock width identification module receives test mode data and a clock single-line signal through an input / output pin of the chip, and processes the test mode data and the clock single-line signal to obtain a first signal; the data time sequence generation module receives test mode data and a clock single-line signal through an input / output pin of the chip, and processes the first signal according to the test mode data and the clock single-line signal to obtain a second signal; and the test control module detects the second signal, and if the second signal is matched with a preset signal, the chip enters a test mode. According to the invention, through a single-line transmission technology, the chip can enter a test mode only by multiplexing one input / output pin of the chip.

The invention relates to the technical field of circuit board processing, and discloses an intelligent dust collector customized circuit board positioning device which comprises an operation table. The positioning and clamping assembly is used for clamping the circuit board in a centered positioning mode; the protection assembly is used for preventing the clamped circuit board from falling off during movement; the positioning and clamping assembly comprises a locking part used for switching the two clamping states of elastic clamping and rigid clamping. Through the arrangement of the positioning and clamping assembly, the four mounting boxes can synchronously perform centering movement, and clamping pieces on the four mounting boxes can perform centering positioning and clamping on a rectangular circuit board, so that the effect of automatic positioning is achieved, the positioning accuracy is high, and the positioning accuracy is high in cooperation with the rotation of an annular frame. And an operator can detect and assemble the rectangular circuit board, so that the number of operable procedures on the operation table is increased, and the overall working efficiency is improved.

The invention, which relates to the technical field of the probe test fixture, discloses a multidirectional self-adaptive adjustment chip probe test fixture comprising a base, and the top end of the base is provided with a probe test assembly. According to the invention, the self-adaptive adjustment of the direction and inclination angle of the chip is realized through the adjusting mechanism, so that the clamping test of various types of chips can be supported, the replacement frequency of the clamp is reduced, the cost and maintenance time are reduced, the debugging time is shortened, the adjustment precision is ensured, and meanwhile, the signal loss is reduced. Mechanical self-locking and unlocking of the fixed gear A and the fixed gear B are achieved through the locking mechanism, so that the stability of the chip after inclination angle adjustment and direction adjustment is guaranteed, manual operation is not needed, and the automation degree is high; the chip is stably clamped through the clamping mechanism, and the chip can be accurately rotated by 90 degrees when clamping is released, so that test edges are automatically switched, the test efficiency is remarkably improved, and manual operation errors are reduced.

The invention relates to the technical field of semiconductors, and provides a method for determining a working curve of a chip, a program product, a storage medium and electronic equipment. The method for determining the working curve of the chip comprises the steps that by running a test case for a target chip, the corresponding minimum working voltage of the target chip at a plurality of target frequency points is obtained, and the minimum working voltage is the minimum working voltage enabling the target chip to correctly execute the test case; and fitting a working curve of the target chip by using the plurality of target frequency points and the corresponding minimum working voltage, wherein the working curve is a curve representing the relationship between the frequency and the minimum working voltage. According to the method, the working curve of the target chip can be simply and efficiently determined, and the minimum working voltage of the target chip under the frequency can be obtained by randomly assigning one working frequency based on the working curve, so that great convenience is provided for obtaining the minimum working voltage of the target chip under different frequencies, and the working efficiency of the target chip is improved. And the method has good universality.

An inspection method according to one aspect of the present disclosure is for inspecting a wiring board P by applying an inspection voltage or an inspection current to an inspection target X. The inspection target X is a part of the wiring board P that comprises an insulator and a conductor and on which an electric component is mounted. The inspection target is subject to a plurality of inspections, and the inspections include a first inspection for inspecting the conduction state of the conductor or the insulator, and a second inspection for inspecting time-series data of the conductive state of the conductor or the insulator. The result of the first inspection and the result of the second inspection are recorded in a recording device. A third inspection is further included, which is carried out after the first inspection and the second inspection, in a state where processing is performed and an electric component is mounted in a subsequent process. The result of the third inspection is recorded in association with the result of the first inspection and the result of the second inspection.

The invention relates to the field of chip fault positioning, in particular to a chip fault rapid positioning method and device, equipment and a storage medium. The method comprises the following steps: acquiring temperature sensing data and time sequence signals in a chip operation process; performing multi-index deviation calculation on the temperature sensing data and the time sequence signal to generate a state deviation index; performing real-time comparison detection on the state deviation degree index based on a preset first deviation threshold value, and when the state deviation degree of the index deviation curve exceeds the preset first deviation threshold value, triggering a fault early warning mode; identifying abnormal function parameters based on the fault early warning mode; identifying the dependency relationship of each functional module of the chip; constructing a fault propagation model based on the dependency relationship; and inputting the abnormal function parameters into the fault propagation model for analysis, and outputting a fault source candidate set. According to the method, by focusing on a high-probability area, the defect searching time is remarkably shortened, and the chip fault position is efficiently and quickly positioned.

The present invention provides an electro-conductive contact pin which can implement a narrow-pitch and an inspection device including same. Furthermore, the present invention provides an electro-conductive contact pin which uses a guide housing formed to have consistent thickness overall, including a portion corresponding to a lower part of an interference member and prevents damage due to interference with the interference member, and an inspection device including same.