5765results about "Electronic circuit testing" patented technology

The invention provides a circuit board electrical performance test and diagnosis method, which comprises the following steps of: constructing a structured process-electrical data set by collecting process parameters such as etching time, pressing temperature, drilling precision, copper foil thickness and the like and electrical test indexes such as impedance deviation, leakage current, signal attenuation and the like; screening key process variables by adopting mutual information analysis and a maximum correlation-minimum redundancy criterion; through modeling of a three-layer causal diagram and a structural equation, quantitative influence evaluation of process parameters on electrical performance and fault types is realized; when a fault is detected, the system can automatically perform reverse reasoning, identify a main manufacturing deviation item and generate attribution diagnosis and process optimization suggestions, so that the accuracy of fault diagnosis and the pertinence of process adjustment are improved, and the fault occurrence rate is reduced and the product quality is improved.

The invention discloses a method for diagnosing an IGBT open-circuit fault and a current sensor fault of a T-type three-level inverter, belongs to the technical field of inverter fault diagnosis, and is used for solving the problems of diagnosis and positioning when a three-level T-type inverter IGBT switch tube and a sensor have faults. Comprising the following steps: classifying and marking and numbering fault types of an open-circuit fault of a T-type three-level inverter IGBT and a fault of a current sensor; fault samples are collected and divided into a training set and a test set according to the proportion of 7: 3; a TCN-LSTM-SelfAction fault diagnosis model is constructed, and model training is carried out by using the training set; the trained model is used for evaluating the accuracy of fault type diagnosis of the training set and the test set. According to the diagnosis method, the fault types and the fault positions of the IGBT open-circuit fault and the current sensor fault can be diagnosed at the same time, the TCN and the LSTM are selected to be combined, local information and global relation of fault features can be captured at the same time, and meanwhile, the performance of a model is improved by combining a self-attention mechanism in the LSTM, and the accuracy is improved.

The invention provides a semiconductor chip automatic test optimization system, and belongs to the technical field of electrical variable measurement. Comprising an acquisition module used for establishing an electrical variable time sequence arranged according to a time sequence, a drift analysis module used for calculating a short-time fluctuation amplitude value, a long-term drift slope and a high-frequency noise amplitude value based on the impedance time sequence arranged according to the time sequence, and a contact judgment module. The evaluation module is used for constructing a contact impedance coefficient based on a short-time fluctuation amplitude value, a long-term drift slope and a high-frequency noise amplitude value in a jth sliding window, and evaluating and optimizing the contact impedance coefficient, and the data marking module is used for marking electrical variable measurement data corresponding to a test channel which is evaluated to be instable in contact as low confidence. According to the system, the ith test channel of the temperature sensor chip can be tested more accurately, the short-time fluctuation amplitude value, the long-term drift slope and the high-frequency noise amplitude value are calculated at the same time, multi-source data participates, and the test accuracy is improved.

The invention relates to the technical field of semiconductor parallel testing, and provides a semiconductor device parallel testing method and system based on a multi-channel IC testing machine. The method comprises the following steps: acquiring a parallel test task set, and extracting key test characteristics of each task; calculating test conflicts among the tasks, and generating a task conflict matrix; outputting a channel distance matrix according to the test machine channel position; defining a conflict scheduling objective function, jointly solving a distance matrix and a conflict matrix, and outputting a task channel mapping relation; and loading the task set according to the mapping relation to execute the test. The technical problems of parallel test conflicts and unreasonable test resource allocation caused by difference of voltage, current, frequency or drive circuit characteristics of different test tasks are solved, and under the premise of guaranteeing the test accuracy and the system stability, through collaborative optimization mapping of the conflict matrix and the distance matrix, the test efficiency is improved. And the resource allocation of the multi-channel IC test machine is optimized, the interference conflict between tasks is reduced, and the parallel test efficiency is improved.

The invention discloses a printed circuit board withstand voltage detection and evaluation method, which comprises the following steps: in the whole withstand voltage detection process, aiming at different process batches and environments, acquiring electrical signals, process parameters, environment variables and multi-modal visual data, and carrying out time sequence synchronization marking and standardized preprocessing; extracting multi-source features by using a feature coding algorithm, and establishing a multi-mode distribution model covering signal mutation, visual defects and working condition anomalies; through cross-modal feature fusion and a time sequence causal inference model, an abnormal event causal relationship graph is automatically constructed, and a voltage withstanding failure root cause chain is identified and positioned; according to the method, the efficient structured management of the detection data, the accurate traceability of the abnormal reasons and the cross-batch analysis are realized, and the capability of diagnosing and preventing the withstand voltage abnormality of the printed circuit board is remarkably improved.

The invention provides a semiconductor chip defect detection positioning method and system, and relates to the technical field of semiconductor chip detection, and the method comprises the steps: obtaining an original image and electrical test data; forming a defect candidate area based on local density analysis; variational mode decomposition is carried out on the electrical data, and electrical characteristic abnormal points are marked; mapping the image features to an electrical characteristic space and calculating mutual information values to determine defect points; and calculating the distribution and path of a diffusion field and determining the severity of the defect. According to the invention, accurate positioning and severity evaluation of chip defects are realized, and the detection efficiency and accuracy are improved.

The invention discloses a method and system for testing a direct-current offset compensation circuit of an optical transceiving driving chip and a medium, and relates to the technical field of photoelectric integrated circuit testing, and the method comprises the following steps: carrying out the time alignment of a test waveform and an offset track of the optical transceiving driving chip, extracting the phase dislocation amount and the amplitude kick amount between beats, and carrying out the calculation of the phase offset amount and the amplitude kick amount; a continuous change result is mapped into a time sequence conflict observation band which is used for identifying a beat overlapping region; and on the basis of the phase dislocation trend of the time sequence conflict observation band, determining a beat overlapping point of the direct current offset compensation loop, and generating an overlapping beat index according to the duration of amplitude kick and the polarity direction for identifying an interference node. According to the method, millisecond-level beat observation and microsecond-level overlapping identification are realized in a test stage, interference nodes are accurately extracted, a coupling strength graph is constructed, and by combining beat rearrangement and an energy unloading strategy, nonlinear oscillation is inhibited, oscillation and overload risks are reduced, eye pattern quality and error code stability are improved, and chip test precision and robustness are enhanced.

The invention relates to the field of chip testing, in particular to a chip signal integrity test analysis method, device and equipment and a storage medium. The method comprises the following steps: extracting a chip performance index based on a chip design requirement document; performing saturation frequency excitation setting based on the chip performance index to generate an excitation test signal; performing a multi-port signal excitation test and parallel signal sampling based on the excitation test signal to generate a high signal-to-noise ratio response data set; obtaining a chip layout design file; performing chip communication link analysis on the chip layout design file, and constructing communication line layout data; performing signal mapping and waveform quality evaluation on the communication line layout data based on the high signal-to-noise ratio response data set to obtain a node signal distortion rate; and performing signal integrity quantization and theoretical signal integrity score comparison based on the node signal distortion rate, and marking a fault node. According to the invention, the chip testing efficiency is improved, and the signal abnormal part of the chip is accurately and efficiently detected.

The invention provides a chip test calibration device and method, and relates to the technical field of chip test. The chip test calibration device comprises a base, a cooling air supply device, a control device, a chip and two groups of manipulators. According to the invention, the chip is heated by setting different temperature environments in stages, and the multi-point synchronous temperature measurement of each temperature stage is combined, so that the heat distribution on the surface of the chip can be comprehensively captured, and the calibration error caused by non-uniform temperature or a detection blind area is avoided; the chip is automatically circulated among the heating station, the detection station and the cooling station, synchronous processing and continuous detection of multiple chips are achieved, the single-batch detection period is greatly shortened, the surface of the chip is directly blown by directional airflow, an efficient air return channel is matched, the temperature of the chip can be rapidly reduced after detection is completed, idle waiting for station switching is reduced, and the overall production efficiency is improved.

The invention provides an automatic chip aging test method and system and a medium, and relates to the technical field of semiconductors, and the method comprises the steps: after a type identifier of a to-be-tested chip is identified, calling an aging test parameter group corresponding to the type identifier, and carrying out the aging test of the to-be-tested chip through the aging test parameter group, after the key electrical parameters of the to-be-tested chip in the aging test process are collected, comparison is carried out to obtain a comparison result, when the comparison result exceeds a preset threshold range, abnormal recording operation is automatically carried out, and the current aging test link of the to-be-tested chip is terminated. By automatically recording abnormal information and terminating the aging process, full-automatic closed-loop processing from data acquisition and analysis to decision and control is realized, the test efficiency is improved, test equipment and samples are effectively protected, resource waste and misjudgment risks are reduced, and the problems of low aging trend identification precision and slow response speed are solved.

A probe card mounted in an of electronic device testing apparatus is described, having a probe head housing a plurality of contact probes, each having a first end portion which abuts onto contact pads of a device under test, a main board and a connected intermediate board which provides a distance spatial transformation between contact pads made on opposite faces thereof. The intermediate board is a space transformer which includes a plurality of modules that are plate-shaped and coplanar, and structurally and functionally independent from each other. Each module has a first face facing towards the probe head and a first plurality of contact pads whereonto respective second end portions of the contact probes abut and an opposite second face facing towards the main board. The second face has a second plurality of contact pads connected to the first plurality of contact pads.

The invention relates to the technical field of circuit board processing, and discloses an intelligent dust collector customized circuit board positioning device which comprises an operation table. The positioning and clamping assembly is used for clamping the circuit board in a centered positioning mode; the protection assembly is used for preventing the clamped circuit board from falling off during movement; the positioning and clamping assembly comprises a locking part used for switching the two clamping states of elastic clamping and rigid clamping. Through the arrangement of the positioning and clamping assembly, the four mounting boxes can synchronously perform centering movement, and clamping pieces on the four mounting boxes can perform centering positioning and clamping on a rectangular circuit board, so that the effect of automatic positioning is achieved, the positioning accuracy is high, and the positioning accuracy is high in cooperation with the rotation of an annular frame. And an operator can detect and assemble the rectangular circuit board, so that the number of operable procedures on the operation table is increased, and the overall working efficiency is improved.

An inspection method according to one aspect of the present disclosure is for inspecting a wiring board P by applying an inspection voltage or an inspection current to an inspection target X. The inspection target X is a part of the wiring board P that comprises an insulator and a conductor and on which an electric component is mounted. The inspection target is subject to a plurality of inspections, and the inspections include a first inspection for inspecting the conduction state of the conductor or the insulator, and a second inspection for inspecting time-series data of the conductive state of the conductor or the insulator. The result of the first inspection and the result of the second inspection are recorded in a recording device. A third inspection is further included, which is carried out after the first inspection and the second inspection, in a state where processing is performed and an electric component is mounted in a subsequent process. The result of the third inspection is recorded in association with the result of the first inspection and the result of the second inspection.

The invention relates to the field of chip fault positioning, in particular to a chip fault rapid positioning method and device, equipment and a storage medium. The method comprises the following steps: acquiring temperature sensing data and time sequence signals in a chip operation process; performing multi-index deviation calculation on the temperature sensing data and the time sequence signal to generate a state deviation index; performing real-time comparison detection on the state deviation degree index based on a preset first deviation threshold value, and when the state deviation degree of the index deviation curve exceeds the preset first deviation threshold value, triggering a fault early warning mode; identifying abnormal function parameters based on the fault early warning mode; identifying the dependency relationship of each functional module of the chip; constructing a fault propagation model based on the dependency relationship; and inputting the abnormal function parameters into the fault propagation model for analysis, and outputting a fault source candidate set. According to the method, by focusing on a high-probability area, the defect searching time is remarkably shortened, and the chip fault position is efficiently and quickly positioned.

The present invention provides an electro-conductive contact pin which can implement a narrow-pitch and an inspection device including same. Furthermore, the present invention provides an electro-conductive contact pin which uses a guide housing formed to have consistent thickness overall, including a portion corresponding to a lower part of an interference member and prevents damage due to interference with the interference member, and an inspection device including same.

The invention is applicable to the technical field of PCB testing, and particularly relates to a PCB electrical performance testing method, which comprises the following steps of: acquiring test object information; wherein the object information comprises a PCB image and at least one test area, the PCB image corresponds to the PCB and reflects the circuit structure of the PCB, the test area is marked on the PCB image, and the test area comprises a main test position and an auxiliary test position; when an electrical performance test instruction is received, contact judgment information is obtained based on the test object information; when it is detected that the auxiliary test probe is in stable contact with the auxiliary test position, the control device controls the main test probe to continuously send test signals and collect test results in real time, and test analysis information is obtained based on the test results. According to the PCB electrical performance test method provided by the embodiment of the invention, the problem of high test error caused by asynchronous actions of the main test probe and the auxiliary test probe can be improved.

The invention relates to the technical field of interconnection testing, in particular to an electrical performance and defect synchronous testing system of a CoWoS packaging TSV interconnection structure, which comprises a signal sorting module, a defect positioning module, a partition classification module, a hot area distribution positioning module and a load evaluation module. According to the method, through real-time monitoring and collection of the multi-source signals, the dynamic state of the key node in the TSV interconnection structure can be efficiently extracted and analyzed, the limitation of traditional single-point testing is broken through, abnormal fluctuation is accurately detected, a defect area is rapidly positioned, the recognition capability of electrical abnormity in the micro interconnection structure is improved, and the detection accuracy is improved. The device operation state and the load problem can be calibrated, the reliability of the packaging structure is optimized, the monitoring accuracy of the electrical performance of the complex interconnection structure is remarkably improved, the global problem is prevented from being missed, electrical anomalies of different hierarchies and regions are covered, the effectiveness of defect identification and fault prediction is enhanced, the detection efficiency and accuracy are improved, and the reliability of the packaging structure is improved. And the risks of missing detection and misjudgment are reduced.

The invention relates to the technical field of circuit board detection, in particular to a quality detection system of an integrated circuit board, which comprises an image acquisition module used for cooperatively acquiring a surface image and a temperature distribution image of the integrated circuit board through a camera array and a multispectral light source; the preprocessing module is used for carrying out noise suppression, distortion correction and multispectral fusion on the surface image and the temperature distribution image and generating a standardized detection image; the defect detection module is used for extracting welding spot contour features, wire connectivity features and dielectric layer thickness features from the standardized detection image, the welding spot image and the inner layer wiring image of the integrated circuit board can be separated, interlayer interference is eliminated, multi-dimensional more accurate evaluation of defect risks is achieved, and the defect detection accuracy is improved. Misjudgment caused by traditional isolated analysis is avoided, the irradiation angle and intensity of the multispectral light source can be dynamically adjusted, and the reliability and efficiency of quality detection of the integrated circuit board are improved.

The invention relates to the technical field of wafer test equipment, in particular to a heating aging test tool which comprises a storage rack and further comprises a wafer clamp placed on the storage rack. The detection assembly comprises a plurality of elastic probes located on one side of the storage rack and a heating disc; and the hot air guide assembly comprises a ventilation male head arranged on one side of the heating disc, an air guide pipe is arranged on the side, away from the ventilation male head, of the heat conduction cover, the air amount in the cavity is gradually decreased from near to far away from the air guide pipe, and the air flow speed is gradually decreased. A hot air flow guide assembly is arranged on a conveying frame, heat of a heating disc is guided to the position above a wafer through airflow through a heat conduction cover, the space above the wafer is divided into a plurality of cavities, the space size and the space shape of each cavity are set, the air flow speed and the contained hot air amount of each space are adjusted, and therefore the heat conduction efficiency of the wafer is improved. The influence of heat loss in the air flow process is reduced, so that the heating effects of all parts of the wafer are similar, and the detection effect is improved.

The invention relates to the technical field of nano-probe detection, and particularly discloses a nano-probe test system for feeding back contact force in real time, comprising the following modules: a probe execution module comprising a nano-probe and a piezoelectric ceramic driver, the nano-probe realizing three-dimensional micro-displacement and establishing controllable contact with a wafer; the multi-dimensional signal sensing module is used for synchronously acquiring a contact resistance signal and a nanoprobe deformation signal; the data processing and control module is used for realizing signal analysis, force value calculation and driving control of a contact resistance signal and a nanoprobe deformation signal; the man-machine interaction module comprises a touch display screen and a real-time data recorder and is used for realizing visualization of force signals; the data processing and control module carries out cooperative analysis on the contact resistance signal and the nanoprobe deformation signal obtained by the multi-dimensional signal sensing module to obtain the real-time contact force of the nanoprobe and the wafer. The system solves the problem that a traditional nanoprobe detection system cannot feed back the contact force in real time.

The invention provides a reliability detection method and system based on chip module packaging and a medium. The method comprises the following steps: querying a basic threshold value by obtaining chip module packaging process detection parameters and design data; combining the real-time influence data with a preset rule to obtain compensation data, and calculating a correction threshold value; obtaining a process capability state and threshold control data through historical data and statistical process control, further calculating a dynamic threshold, and comparing detection parameters to obtain a process state; after all procedures are qualified, evaluating edge states to obtain risk factors and summing the risk factors to obtain a comprehensive risk value, obtaining a final threshold by combining reliability test data and a reference threshold, and determining the reliability state of the module after comparison; therefore, through calculation processing and threshold comparison of the basic threshold, the corrected threshold, the dynamic threshold and the final threshold, the technology for detecting the packaging reliability of the chip module is realized.

The invention is suitable for the technical field of semiconductor testing, and provides a chip mass production testing environment recovery method and device and electronic equipment, and the chip mass production testing environment recovery method is used for carrying out anomaly detection on a second module used for executing a chip testing task. After an exception is found, a first module used for user interaction and monitoring triggers recovery in an overtime tolerance interval, at least a second module is restarted, and a mass production test environment context stored by the first module is injected, so that the second module quickly returns to a runnable state with existing batch parameters and a process state; and then the second module is automatically reconnected with the ATE test equipment, marks the current tested chip as retestable and sends the retestable chip to the chip processing equipment, so that the chip processing equipment confirms the test process and switches to the next to-be-tested chip, and the second module continues to execute the test task. According to the scheme, the continuity and the stability of the chip mass production test in the abnormal scene are realized.

The invention belongs to the technical field of performance testing, and particularly discloses an intelligent testing system and method for the impedance performance of an HDI circuit board, and the method comprises the steps: immediately starting an interlayer collection module after the lamination of each line layer, carrying out the electrical precise alignment through a POFV test structure, and collecting the in-situ impedance data; the diagnosis prediction module analyzes and processes the data, generates an impedance deviation parameter set, calculates an impedance performance standard coefficient fused with a layer influence factor, and analyzes and outputs a trend result through a time sequence; the impedance state judgment module carries out abnormity judgment based on a preset rule according to the standard coefficient and the trend result; when the judgment result is abnormal, an adjustment triggering marking module is started; and finally, a test report output module generates a test report containing the impedance performance score and the impedance performance distribution of the whole board. According to the invention, layer-by-layer, real-time and closed-loop intelligent test and regulation of impedance performance are realized, and product quality and production efficiency are effectively improved.

The invention discloses an LED chip service life rapid estimation method and device and a medium, and relates to the technical field of electrical digital data processing, and the method comprises the steps: designing a current pulse stress sequence for a calibration sample based on photoelectric thermal characteristic data, synchronously collecting photoelectric thermal response data before and after a pulse, and carrying out verification completion and mapping storage; generating a photoelectric thermal pulse response data set; according to the photoelectric thermal pulse response data set, photoelectric thermal change characteristics of the LED chip sensitive to the service life are extracted, and a photoelectric thermal pulse service life fingerprint of the LED chip is constructed; constructing a service life rapid estimation model, and predicting the service life of the LED chip according to the photoelectric thermal pulse service life fingerprint and the working condition information to generate the predicted service life of the LED chip; according to the method, the photoelectric thermal pulse life fingerprint of the LED chip is constructed, the photoelectric thermal evolution process under the pulse stress is compressed into a unified life characterization carrier, and a degradation feature basis capable of being directly called is provided for life modeling.

The invention belongs to the technical field of PCB flying probe detection equipment, and particularly relates to a flying probe compensation method and system based on PCB curved surface modeling, and the method comprises the steps: obtaining the size of a PCB, and carrying out the equilateral triangle grid division; in the visual alignment process, the laser distance measuring sensor is synchronously driven to carry out rapid non-contact height measurement on the vertex of the grid; based on the vertex three-dimensional coordinates, fitting triangular patches through a space plane equation and splicing the triangular patches into a three-dimensional curved surface model; performing bilinear interpolation on an area formed by adjacent patches in the model to smooth a curved surface; and finally, selecting an interpolation function according to the position of the test point to calculate the accurate height, and generating a Z-axis displacement compensation value of the probe. According to the high-precision measurement and self-adaptive compensation of the PCB warpage, the efficiency and precision of the flying probe test are considered, and the problem of poor contact or overvoltage damage of the probe caused by the board warpage is effectively solved.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention provides a chip aging test system and method based on a field programmable gate array, and the system is characterized in that a drive control panel comprises a processor module, a communication interface module, and an external connector module; the external connector module comprises a first connector and a second connector; the processor module is used for receiving a test instruction sent by the upper computer through the communication interface module, generating a test signal and a control signal, and receiving a test result acquisition instruction sent by the upper computer after the communication interface module sends response information to the upper computer; the first end of the processor module is also used for sending the interrupt information to an upper computer through the communication interface module and displaying the interrupt information; and the third end of the processor module is connected with the second connector and is used for outputting the control signal to the test board. Test signals are output to multiple groups of tested chips of the test board in parallel through the first connector, the second connector controls the test sequence of the to-be-tested chips on the test board, and hundreds of chips are driven by a single drive board and used for aging test.

The invention relates to an electrified vibration test clamp for a pin-containing surface-mounted integrated circuit, belonging to the technical field of integrated circuit test. Comprising a road board part and a structural member part, and the structural member part comprises a limiting base, a fixing buckle and a silica gel sheet for pressing the fixing buckle. The test circuit and peripheral elements thereof are arranged on one side of the circuit board, and the package of the device to be tested is independently arranged on the other side of the circuit board. The limiting base is used for being installed and fixed on a functional circuit board, a positioning groove for containing a device is formed in the limiting base, the position of a notch is just consistent with the packaging layout position of the device on the circuit board, and after the device is placed in the notch, pins can be matched with bonding pads in a one-to-one correspondence mode. The fixing buckle is installed and fixed on the notch of the limiting base for placing the device and reliably presses the pin of the device. The problems that the reliability of surface pressing type and pin locking type testing technologies is poor and a testing device is easily damaged during an electrified vibration test of an existing pin-mounted surface-mounted integrated circuit are solved. The device can be widely applied to electrified vibration and related environment tests of surface-mounted integrated circuits with pins.

The utility model provides a high-voltage pulse generating device and a test system. The high-voltage pulse generating device comprises a main control unit, a driving circuit, a pulse control circuit with a wide bandgap semiconductor power device, and an output circuit, the first end of the main control unit is coupled with the first end of the driving circuit, the second end of the driving circuit is coupled with the first end of the pulse control circuit, and the second end of the pulse control circuit is coupled with the output circuit; the main control unit is configured to generate two paths of first PWM (Pulse Width Modulation) signals with dead time control; the two paths of first PWM signals are sent to the driving circuit; and the driving circuit is configured to process the first PWM signal and then drive the pulse control circuit, so that the output circuit generates a high-voltage pulse signal. According to the utility model, the structure is simple, the cost can be greatly reduced, the output pulse speed can be flexibly set, and the CMTI test requirements of different isolated gate drivers can be met.

The invention discloses a low-temperature CMOS carrier MFP and microscopic parameter extraction method and system, which are corresponding schemes, in the scheme, a carrier MFP extraction model for eliminating a microscopic unknown quantity is constructed by utilizing a geometric scaling rule of quasi-ballistic transport and an existing effective mobility extraction technology, and an MFP extraction model for eliminating the microscopic unknown quantity is constructed by utilizing the geometric scaling rule of quasi-ballistic transport and the existing effective mobility extraction technology; the MFP extracted by the carrier MFP extraction model is ensured to be a pure experiment observation value on the basis that effective quality, Fermi velocity and scattering time do not need to be predicted based on the self-consistency of macroscopic current and voltage data along with the change of channel length; meanwhile, on the basis, the microcosmic parameters are decoupled, so that the decoupled microcosmic parameters are extracted one by one; compared with an existing scheme, the method can be directly applied to a standard wafer-level test board in the industry, MFP distribution of hundreds of devices can be rapidly counted, and a feasible engineering scheme is provided for low-temperature process monitoring.