13263results about "Electronic circuit testing" patented technology

The invention provides a defect detection method and system for integrated circuit manufacturing. Wherein in the integrated circuit packaging stage, packaged chips are divided into a first type of chips meeting a preset physical characteristic threshold value and a second type of chips exceeding the physical characteristic threshold value through a pneumatic sorting device; performing scanning electron microscope imaging on the surface of the second type of chip, generating a three-dimensional topological structure by using an image reconstruction technology, and positioning a micron-sized particle defect area by comparing reference type differences; synchronously applying high-frequency electric signal excitation in the sorting process, detecting impedance response of the second type of chips, and recording an abnormal signal sequence exceeding a preset frequency domain range; performing space-time correlation matching on the micron-sized particle defect area and the abnormal signal sequence, and judging that the defect is a multi-layer composite defect when a preset coupling condition is met; and dynamically adjusting the mesh diameter and vibration frequency parameters of the pneumatic sorting device. According to the technical scheme provided by the invention, accurate identification of the multi-layer composite defect of the chip is realized, and the defect interception efficiency is remarkably improved.

The invention discloses a PCBA circuit board welding spot detection method based on multi-modal data fusion, and relates to the technical field of electronic manufacturing quality detection.The PCBA circuit board welding spot detection method comprises the steps that a distributed sensing network is constructed, multi-modal data are collected, welding spot information is obtained in an omnibearing mode, and time-space alignment of the multi-modal data is carried out; performing feature extraction on the multi-modal data, dynamically weighting each modal feature through an attention mechanism, and highlighting key defect characterization; a welding spot spatial topological graph is constructed by using a graph neural network, and a spatial relationship between welding spots is modeled. By integrating optical, X-Ray, thermal, mechanics, electricity and other multi-dimensional data, the information limitation of single-mode detection is broken through, the complementation of different mode data is utilized, the attention mechanism is combined to dynamically weight each mode feature, the complex defect is accurately identified, the graph neural network is utilized to model the welding spot space topological relation, the associated defect is further captured, and the defect detection accuracy is improved. And the defect classification accuracy is improved.

The invention relates to the technical field of probe testing, and discloses a probe testing device and method, and the method comprises the steps: carrying out the synchronous collection of the electric signal response characteristics of a plurality of chip testing probes in a chip contact process, analyzing the signal transmission interference relation between the probes, and obtaining a multi-probe signal coupling feature pattern; identifying a target signal transmission channel to obtain a first test probe configuration scheme; performing test signal input and response acquisition on the chip to obtain electrical characteristic time-frequency data of the chip; and performing multi-probe collaborative analysis and feature extraction on the time-frequency data of the electrical characteristics of the chip to obtain abnormal indication information of the electrical performance of the chip, and adjusting test parameters and contact positions of a plurality of chip test probes to obtain a configuration scheme of a second test probe. Therefore, the test system can intelligently adjust the subsequent test strategy according to the preliminary test result, and the intelligence and automation of the test process are realized.

The invention relates to the technical field of chip testing, in particular to a chip testing method and a chip testing system. The method comprises the following steps: acquiring a thermal imaging image of a working state of a chip; global color temperature offset optimization is carried out on the thermal imaging image of the working state of the chip, and spatial heat distribution mining is carried out, so that a chip heat distribution diagram is constructed; performing multi-moment heat distribution tracking processing on the chip heat distribution diagram, performing dynamic heat distribution evolution fitting, and constructing a dynamic heat distribution trend evolution diagram; acquiring a high-definition image of a to-be-tested chip; performing chip assembly visual monitoring on the high-definition image of the to-be-tested chip, performing heat distribution trend rendering based on the dynamic heat distribution trend evolution graph, and constructing a chip assembly heat distribution trend rendering model. According to the invention, through limit working condition test analysis, the evaluation efficiency and accuracy of the chip performance are improved.

The invention relates to the technical field of chip testing, and provides a chip temperature characteristic testing method, system and equipment, and the method comprises the steps: obtaining transient thermal response data and steady-state thermal distribution data of a chip, carrying out the feature extraction of the transient thermal response data, obtaining a feature thermal mode set, and carrying out the feature extraction of the feature thermal mode set; performing heat transfer analysis on the steady-state heat distribution data by utilizing the characteristic heat mode set to obtain a long-term temperature drift curve; and evaluating the long-term temperature drift curve to obtain a thermal reliability score and a thermal degradation prediction parameter, and generating life prediction data of the chip based on the thermal reliability score and the thermal degradation prediction parameter. By combining the analysis of transient thermal response data and steady-state thermal distribution data, the accuracy and reliability of temperature characteristic test are improved, and the problem that the traditional method is difficult to accurately capture the transient change characteristic of the chip temperature and identify the long-term temperature drift trend under a dynamic working condition or a complex load condition, and the test accuracy is insufficient is solved.

The invention relates to the technical field of chip aging tests, and discloses a chip aging test fixture control method and device and a storage medium, and the method comprises the steps: carrying out the parameter collection of a test fixture, and obtaining original test data; performing control signal analysis and signal fusion, and inputting a fused temperature control instruction into a temperature control unit of the test fixture to obtain steady-state test data; performing multi-dimensional analysis and data screening to obtain effective test data; performing performance feature extraction to obtain performance feature data; grouping is carried out, the weight coefficient of each test channel is calculated, weighting processing is carried out in combination with a failure mode standard, and aging characteristic data is obtained; and inputting the aging characteristic data into the life prediction model to calculate a performance prediction value and a life prediction value to obtain a chip aging test result, the chip performance degradation characteristics can be accurately captured, the performance prediction value and the life prediction value are output at the same time, and a comprehensive aging evaluation result is provided.

The present invention discloses a system and method for quickly testing the anti-hydrolysis performance of LED chips, wherein the system comprises: a temperature and humidity regulator, the temperature and humidity regulator is provided with a cavity; a rotating device connected to the inner wall of the cavity, the rotating device can rotate along the inner wall of the cavity; a bracket, the bracket is a cup-shaped structure, the LED chip is mounted on the bracket and forms a conductive connection with the bracket; a test substrate, the bracket is fixed on the test substrate, and the bracket is conductively connected to the test substrate, and the test substrate is connected to the rotating device; the direction of the LED chip is adjusted by the rotating device, a reverse voltage is passed to the test substrate, and the temperature and humidity in the cavity are adjusted to perform an impact test on the LED chip. The direction of the LED chip is adjusted by the rotating device, and the hydrolysis speed of the LED chip is effectively accelerated, thereby shortening the detection time.

The invention relates to the technical field of data processing, and provides a chip electromagnetic compatibility analysis method, device and equipment, and the method comprises the steps: carrying out the multi-dimensional collection of electromagnetic radiation data of a chip, and obtaining time domain electromagnetic signal data, frequency domain electromagnetic signal data and space electromagnetic distribution data; an electromagnetic interference influence matrix of the chip is constructed and decomposed, after electromagnetic interference source distribution information and interference propagation path information are obtained, an electromagnetic compatibility dynamic evolution sequence of the chip is constructed and analyzed, and an electromagnetic stability parameter and an electromagnetic sensitivity parameter of the chip are calculated; and analyzing the electromagnetic interference influence matrix by using the electromagnetic stability parameter and the electromagnetic sensitivity parameter of the chip, and generating an electromagnetic compatibility evaluation result based on an analysis result. By means of the scheme, the problems that due to the fact that complex interaction between different electromagnetic signals and internal components of the chip cannot be comprehensively captured, a test result is different from performance in an actual operation environment, and interference and operation failure are caused are solved.

The invention discloses an integrated circuit chip test system based on an AI algorithm, and relates to the technical field of integrated circuit chip testing, the integrated circuit chip test system comprises a chip test platform, the chip test platform is in communication connection with the following modules: a data acquisition module, which is used for collecting historical test data from existing integrated circuit chip test equipment, and sending the collected historical test data to the chip test platform; carrying out preprocessing and integration on the chip test data set to obtain a chip test data set; and the model training optimization module is used for analyzing the chip test data set, learning the relationship between the chip performance and the test vector, and training a test vector AI optimization model. According to the method, by analyzing historical test data and automatically generating the optimized test vector, a redundant item-by-item test process in a traditional test is avoided, key test nodes are accurately positioned through the test vector AI optimization model, and unnecessary test steps are reduced, so that the test time is remarkably shortened, and the test efficiency is improved.

The invention relates to the technical field of chip testing, in particular to a chip aging test and analysis method, which comprises the following steps of: constructing an aging parameter matrix containing process deviation, electrical parameters and thermodynamic parameters on the basis of fusion of wafer level and packaged test data, multi-stress cooperative loading is realized through a programmable power supply and a multi-zone temperature control array, transient electric signals, thermal imaging data and leakage current frequency spectrums are acquired in real time, an electrical-thermal coupling coefficient and a process deviation sensitivity factor are extracted in a cross-dimension manner, a non-linear recession model is established, differential aging paths of chip functional blocks are evaluated, and the reliability of the chip functional blocks is improved. And based on the dynamic life prediction model and a fault early warning mechanism, generating and executing an adaptive test optimization strategy to realize early prediction and stress adjustment of multiple failure modes. According to the invention, the efficiency and accuracy of the aging test can be obviously improved, and technical support is provided for high-reliability evaluation of deep submicron and post-mole times of chips.

The invention relates to the technical field of chip testing, and discloses a chip power supply noise influence testing method and device. The method comprises the following steps: carrying out multi-dimensional data acquisition on a chip power supply by utilizing a multi-mode sensing array to obtain original sensing data, and carrying out time synchronization calibration and signal preprocessing to obtain high-quality multi-dimensional data; carrying out time-frequency domain decomposition and correlation calculation on the processed data, and carrying out time delay and position calculation to determine noise source distribution; noise source distribution is mapped to a chip layout, multi-physical field calculation is carried out, a coupling propagation matrix is generated, and a noise propagation characteristic spectrum is obtained through characteristic value decomposition and path calculation; and designing a test condition based on the propagation characteristic spectrum, performing a chip function module performance test, establishing a response relationship between noise and function performance, determining a function failure noise critical value and a tolerance boundary, and forming a complete power supply noise influence test result. According to the method, the accurate positioning of the chip power supply noise is realized, and the evaluation accuracy of the power supply noise influence is improved.

The invention discloses a performance test and verification method, system and device for a multi-core heterogeneous chip and a medium, and the method comprises the steps: configuring a test parameter set according to a target application scene, the test parameter set comprising a processor core type recognition parameter, a communication topology weight parameter and a load balancing threshold parameter; generating a test case covering the heterogeneous computing core cooperative working mode; the method comprises the following steps: acquiring characteristic data during testing through a reconfigurable monitoring sub-module, wherein the characteristic data comprises inter-core communication delay information, shared cache hit rate information and power consumption distribution thermodynamic information; and performing quantitative analysis on the feature data through a multi-dimensional evaluation model to obtain a performance deviation index and an architecture optimization suggestion parameter. By optimizing the chip performance verification process under the multi-core heterogeneous architecture, the verification precision is effectively improved, and the chip performance verification method can be widely applied to the technical field of chip design.

The invention relates to a probe contact impedance real-time monitoring and compensating method and device and a storage medium. The method comprises the following steps: acquiring a first measurement data set containing a probe contact resistance value and a contact force, and inputting the first measurement data set into a double-layer deep learning neural network for training to obtain a probe contact resistance monitoring model; performing two-parameter fault detection to obtain a contact state classification result; generating a two-dimensional compensation matrix based on a contact state classification result, and performing nonlinear mapping calculation on the second measurement data set to obtain a compensation coefficient; the compensation coefficient, the original probe structure parameters and the original probe operation parameters are input into a graph attention stacking auto-encoder for parameter prediction, and target probe structure parameters and target probe operation parameters are obtained; cloud model calculation and weighting operation are carried out, a target compensation instruction is obtained, and the target compensation instruction is used for adjusting the probe position parameters and the probe pressure parameters. According to the invention, the probe testing precision of the chip is improved.

The invention relates to the technical field of electrical fault detection, in particular to a fault detection method and system for key equipment in electrical engineering, and the method comprises the steps: firstly obtaining a post-stage power sudden change degree representing instantaneous abnormality according to the time sequence change of current and voltage outputted by a post-stage circuit; after the mutation degree cluster representing each time period is obtained, according to the change range and discreteness of the post-stage power mutation degree in each mutation degree cluster, screening out an abnormal cluster representing that post-stage circuit output is abnormal; and judging whether the output abnormity of the post-stage circuit is influenced by the pre-stage or not according to the correlation similarity condition between the pre-stage power sudden change degree and the post-stage power sudden change degree at the sampling moment corresponding to the abnormal clustering cluster, thereby more accurately detecting the fault position of the IGBT driving circuit.

The invention provides a power management chip pin state intelligent detection method and system. The method comprises the steps that temperature difference quantity is input into a gradient heat conduction compensation structure, and compensation current opposite to a temperature gradient vector is generated based on temperature field distribution in the copper-based composite material; superposing and coupling the voltage fluctuation signal and the compensation current to generate a reference voltage signal; performing frequency component separation processing on the reference voltage signal, and extracting electromagnetic interference characteristic data in a frequency component; performing time sequence correlation on the electromagnetic interference characteristic data and the temperature distribution data, dynamically adjusting an interference suppression parameter through closed-loop control, and acting the adjusted interference suppression parameter on an interference suppression process of a reference voltage signal to generate a pin state detection signal; and detecting the pin state of the power management chip according to the pin state detection signal. According to the invention, the pin voltage stability and the state detection precision of the power management chip are improved.

The invention discloses a fault monitoring method and system for an analog integrated circuit, and relates to the technical field of integrated circuits, and the method comprises the steps: collecting and recording the electrical parameter data of the analog integrated circuit; preprocessing the electrical parameter data, calculating the resource utilization rate of each subunit and extracting fault feature information; constructing a digital twinborn model corresponding to the analog integrated circuit, and simulating and predicting a fault based on the digital twinborn model; according to the electrical parameter data, the resource utilization rate and the fault feature information, a reinforcement learning algorithm is introduced, and a fault early warning strategy is optimized based on a simulated predicted fault; and according to the fault early warning strategy, early warning thresholds and early warning levels of different fault types are dynamically adjusted, and fault monitoring is realized. According to the invention, abnormal conditions can be found in time, greater damage to the system caused by potential faults is avoided, the real-time performance and accuracy of the monitoring system are ensured, fault information is rapidly provided for maintenance personnel, and the maintenance efficiency is improved.

The invention discloses a fault model construction method for adaptive testing of abnormal values of a system-on-chip. The method relates to the technical field of fault construction of chip testing, and comprises the following steps: testing chips on a large scale under the conditions of different temperatures, voltages, frequencies, loads and the like, acquiring performance parameters such as signal delay and power consumption, screening abnormal values by applying a Z-score or box plot method, and processing by using a sliding window; extracting features through CNN or RNN, and normalizing the features; fault features are classified through K-Means or hierarchical clustering, and the accuracy rate is larger than or equal to 80%; a model is built through an SVM or a decision tree, faults can be predicted, self-updating can be achieved, self-adaptive adjustment can be achieved according to chip parameter changes, independent data verification optimization, one-out-of-leave evaluation and gradient descent optimization are achieved. According to the method, multi-condition testing can be carried out on the system-level chip, abnormal values are accurately screened, features are extracted, faults are classified, a fault model capable of being self-updated is constructed, self-adaptive adjustment and verification optimization are achieved, the accuracy is improved, and the chip testing and fault diagnosis efficiency and accuracy are improved.

The embodiment of the invention discloses a test parameter adjusting and testing system and method, chip testing equipment and electronic equipment. The system comprises a driving link module, a driving service module and a testing module. The driving link module is used for storing each first interface corresponding to at least one device in the chip test equipment; the drive service module is used for calling a first target interface in the drive link module when test parameter adjustment information for a target test item is received, and controlling the first target interface to send the test parameter adjustment information to a target device; and the test module is used for controlling the target device to execute the target test item according to the test parameter adjustment information and acquiring a test result corresponding to the target test item. Therefore, the test parameter information in the target device is directly adjusted in the chip test equipment, so that the test module can test according to the test parameter adjustment information, the adjusted test parameter information does not need to be uploaded to the chip test equipment again, and the test parameter adjustment efficiency is improved.

The invention provides a method and system for preparing a high-temperature anti-aging test board for chip testing, and relates to the technical field of data energy storage and resource scheduling, and the method comprises the steps: designing a schematic circuit diagram and a PCB wiring scheme; a test plate is made of a high-temperature resistant material; bare board verification, electrical performance verification, program setting verification, high temperature verification and junction temperature measurement verification are carried out; using data is recorded, ultrasonic cleaning and drying are carried out, and a performance evaluation model is established through a hardware management system to judge whether maintenance or replacement is needed. According to the invention, the accuracy of chip testing in a high-temperature environment is improved, and the service life of the test board is prolonged.

The invention relates to the technical field of chip testing, and discloses an LED driving chip testing method, device and equipment and a storage medium, and the method comprises the steps: carrying out the multi-point temperature excitation and constant-current output synchronous collection of an LED driving chip, and obtaining electrothermal coupling test data; performing thermal resistance network decomposition on the temperature field in the chip to obtain temperature distribution characteristic parameters; performing nonlinear function fitting on the temperature-constant current coupling relation to obtain an electrothermal coupling transfer coefficient; performing four-dimensional coupling calculation on the temperature distribution characteristic parameter and the electrothermal coupling transfer coefficient to obtain four-dimensional coupling response characteristic data; and partial differential sensitivity calculation is carried out based on the four-dimensional coupling response characteristic data, and an electrothermal coupling sensitivity analysis result is obtained.According to the method, the problem of test errors caused by time desynchrony in a traditional separated temperature-current test is solved, quantitative sensitivity analysis of electrothermal coupling parameters is achieved, and the sensitivity of the electrothermal coupling parameters is improved. Therefore, the test accuracy of the LED driving chip is improved.

The invention relates to an intelligent monitoring method and system based on a power supply and distribution system, and relates to the technical field of power grid monitoring. Establishing a detection interval and determining an interval change parameter; determining an interval change combination according to all the interval change parameters; establishing a historical interval, randomly delimiting a comparison interval of which the width is the detection duration in the historical interval, and determining a comparison change combination in each comparison interval; determining a combination similarity value according to the interval change combination and the comparison change combination, determining the combination similarity value with the maximum value according to a sorting rule, and defining a comparison interval corresponding to the combination similarity value as a similar interval; establishing a prediction interval according to the similar interval, and defining the detection electric power parameter in the prediction interval as a prediction electric power parameter; and outputting an aging early warning signal when the predicted electric power parameter is greater than the preset early warning electric power parameter. The application has the effect of improving the overall operation effect of the power supply and distribution system.

The invention provides a circuit board electrical performance test and diagnosis method, which comprises the following steps of: constructing a structured process-electrical data set by collecting process parameters such as etching time, pressing temperature, drilling precision, copper foil thickness and the like and electrical test indexes such as impedance deviation, leakage current, signal attenuation and the like; screening key process variables by adopting mutual information analysis and a maximum correlation-minimum redundancy criterion; through modeling of a three-layer causal diagram and a structural equation, quantitative influence evaluation of process parameters on electrical performance and fault types is realized; when a fault is detected, the system can automatically perform reverse reasoning, identify a main manufacturing deviation item and generate attribution diagnosis and process optimization suggestions, so that the accuracy of fault diagnosis and the pertinence of process adjustment are improved, and the fault occurrence rate is reduced and the product quality is improved.

The invention relates to an MEMS mode wafer, an MEMS probe card detection method, an MEMS probe card detection device and a storage medium. The detection method is applied to MEMS wafer detection equipment, and comprises the following steps: loading test configuration parameters of an MEMS probe card to be detected; fixing the MEMS probe card to be tested on a probe seat of test equipment; placing an MEMS mode wafer matched with the to-be-tested MEMS probe card at a preset target position on a test platform of test equipment; the MEMS mode wafer comprises a test point array which is the same as a to-be-tested MEMS wafer corresponding to the to-be-tested MEMS probe card; starting a visual alignment system, and aligning the MEMS probe card to be tested with the MEMS mode wafer; the MEMS probe card to be tested is calibrated; and executing the test task of the MEMS wafer to be tested, and detecting the MEMS probe card to be tested. The test task is automatically executed by using the MEMS mode wafer, and the efficient test of the MEMS probe card is realized.

The invention relates to the technical field of PCB detection, and discloses an online defect detection method and system in the PCB production process and computer equipment, the detection accuracy can be improved by combining production parameters, image information and a design circuit diagram, potential defects can be found in the early stage, the PCB is divided into a plurality of areas, and the detection efficiency is improved. According to the PCB, each area can be independently welded and detected, the complexity of the whole PCB is reduced, the PCB is divided into a plurality of areas which are detected one by one, a specific defect area can be effectively positioned, through the regionalized detection and maintenance process, the unqualified area can be locally processed, the production efficiency is improved, and the production cost is reduced. By adopting the strategy based on multi-round detection, feedback and regional repair, through accurate positioning, local repair, detection efficiency improvement and automatic processing, the rejection rate of unqualified products is greatly reduced, the maintenance success rate is improved, and the problems of difficulty in PCB defect detection and resource waste in the prior art can be effectively solved.

An open and short circuit testing device and method. The device comprises a base (1), a support frame (2), a test board (5) and a placement frame (4). The test board (5) is slidably connected to the side opposite to the support frame (2), and the test board (5) moves downwards to drive a gear (14) to rotate; a limiting plate (17) is used for limiting reverse rotation of the gear (14); and a probe (26) is used for connecting to a circuit board to achieve testing. Under normal conditions, the friction force when the probe (26) is inserted into a wiring terminal (29) is less than the minimum elastic force of a second spring (25), when the probe (26) fails to be normally connected to the wiring terminal (29), the probe (26) is pressed downwards when a movable plate (23) moves downwards, the probe (26) is adjusted by means of the second spring (25) at the top of the probe (26), so that the probe (26) returns to normal, the pressure sensor (31) detects whether there is an abnormality, and when the second spring (25) at the top of the probe (26) is compressed, the pressure sensor (31) at the top of the second spring (25) measures an excessively large pressure value, i.e., indicating that a device abnormality occurs during the testing process rather than representing that there is necessarily a problem with the circuit board to be tested itself, thereby improving the accuracy of the testing result.

The invention discloses a method for diagnosing an IGBT open-circuit fault and a current sensor fault of a T-type three-level inverter, belongs to the technical field of inverter fault diagnosis, and is used for solving the problems of diagnosis and positioning when a three-level T-type inverter IGBT switch tube and a sensor have faults. Comprising the following steps: classifying and marking and numbering fault types of an open-circuit fault of a T-type three-level inverter IGBT and a fault of a current sensor; fault samples are collected and divided into a training set and a test set according to the proportion of 7: 3; a TCN-LSTM-SelfAction fault diagnosis model is constructed, and model training is carried out by using the training set; the trained model is used for evaluating the accuracy of fault type diagnosis of the training set and the test set. According to the diagnosis method, the fault types and the fault positions of the IGBT open-circuit fault and the current sensor fault can be diagnosed at the same time, the TCN and the LSTM are selected to be combined, local information and global relation of fault features can be captured at the same time, and meanwhile, the performance of a model is improved by combining a self-attention mechanism in the LSTM, and the accuracy is improved.

The invention discloses a chip test result real-time compensation method based on a PSO-KF algorithm, belongs to the technical field of integrated circuit testing, and solves the problem of how to improve the accuracy and stability of integrated circuit testing. Based on the real-time change of the measurement data and the environmental noise, a particle swarm optimization algorithm is adopted to optimize noise parameters in the Kalman filter; the particle swarm optimization algorithm is used for updating noise parameters after each measurement data is obtained, and the optimal parameters are applied to the Kalman filter again, so that real-time compensation of the measurement data is realized; and the yield is evaluated based on the compensated data, and the data is fed back to the particle swarm optimization algorithm for the next iterative optimization, so that the Kalman filter can be ensured to be adaptive to the noise change and keep the optimal compensation effect, and the technical scheme of the invention improves the precision, yield and product quality of the chip test.

The invention relates to the technical field of CPU card chips, and discloses a CPU card chip test method, device and equipment and a storage medium, and the method comprises the steps: carrying out the data collection of a CPU card chip, and obtaining an initial test data matrix; constructing a test parameter association diagram of the initial test data matrix and predicting missing data to obtain a complete test data matrix; performing principal component analysis on the complete test data matrix to obtain an effective test data set; constructing a multi-level fuzzy set according to the effective test data set to obtain fusion test data; and inputting the fusion test data into a variational auto-encoder for self-supervised pre-training, executing conditional interpolation by using a diffusion state space model to obtain a defect detection result and an uncertainty estimation value, and realizing optimal fusion of electrical characteristics and functional test data by using a multi-stage fuzzy set and an adaptive weight adjustment mechanism. Complementary advantages of dual-channel data are fully utilized, and a more comprehensive and accurate test result is provided.

The invention belongs to the technical field of PCB detection, and particularly relates to a probe tip deviation compensation method, system and equipment, and the method comprises the steps: building a reference coordinate system, controlling a probe swing arm to rotate to a vertical position and a horizontal position respectively, and employing a bonding pad combination on a special calibration plate to calibrate the probe tip deviation. An electric signal detection mode is adopted to accurately measure the deviation value of the needle point in the X-axis direction and the Y-axis direction, and the position of the probe is automatically compensated according to the deviation value. The system comprises a high-precision driving module, a visual positioning module and a signal acquisition module, and realizes a full-automatic calibration process. According to the method, a horizontal and vertical double-position detection mode is innovatively adopted, complex angle calculation is avoided, the calibration efficiency and precision are greatly improved, the problem of needle point position deviation caused by mechanical errors and long-term use in a traditional method is effectively solved, the measurement precision of PCB detection equipment is remarkably improved, and the detection precision of the PCB detection equipment is greatly improved. Meanwhile, the maintenance cost and the operation difficulty are reduced, and the method is suitable for the field of high-precision PCB detection.

The invention relates to a core particle testing method and system, computer equipment, a storage medium and a computer program product, and is applied to the technical field of chip testing. The method comprises the following steps: acquiring the number of module chips of a to-be-tested core particle; determining at least one test environment component matched with the number of the module chips; the at least one test environment assembly is in one-to-one correspondence with the module chips of the to-be-tested core particles; and running each test environment component in parallel, and testing the corresponding module chip through each test environment component according to a preset test case to obtain a test result of each module chip. By adopting the method, different chip specifications can be adapted, the development cost is saved, the test environment components run in parallel when the core particles are tested, and the test efficiency of the core particles is improved.