530 results about "Reverse bias" patented technology

The invention discloses a silicon carbide TrenchMOS device and a manufacturing method thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the arc-shaped lightly-doped N layer is additionally arranged in the middle of the arc-shaped heavily-doped N layer, electric field distribution under reverse bias is smoothed through the doping concentration lower than that of the heavily-doped N layer, the interface electric field sudden change risk is reduced, dynamic loss is reduced, meanwhile, the doping concentration of the central area is diluted through the arc-shaped inner side lightly-doped N layer, a depletion area is promoted to be expanded, and the performance of the device is improved. Electric field distribution between drain gates is optimized, and stray capacitance is reduced to improve high-frequency performance.

The invention relates to the technical field of photovoltaic cells, and discloses a method for improving laser-assisted sintering contact uniformity and a processing device. The method comprises the steps that a probe presses a main grid of a first area on the front face of a battery piece, first laser power is used for scanning a second area on the front face of the battery piece in a laser scanning mode in the fine grid direction, first reverse bias voltage is applied to the battery piece, and a variable resistor adjusts the resistance value of the variable resistor according to the distance between scanning point positions and the probe so as to balance the bias voltage difference of different scanning point positions; performing laser-assisted sintering on the second area; the probe presses a main grid of a second area on the front face of the battery piece, laser scanning is conducted on a first area on the front face of the battery piece in the fine grid direction through second laser power, second reverse bias voltage is applied to the battery piece, the resistance value of the variable resistance piece is adjusted according to the distance between the scanning point position and the probe, and laser-assisted sintering of the first area is completed. According to the method, the bias voltage difference of different scanning point positions can be balanced, the interface contact difference of different areas can be balanced, and the battery performance and effect can be improved.

The invention belongs to the technical field of display driving, and particularly relates to a noise reduction circuit and a gate driving circuit, and the noise reduction circuit comprises a first noise reduction module which is used for carrying out the noise reduction processing of the voltage of a driving control node, a driving output end and a stage transmission output end; the first noise reduction module is also used for enabling a noise reduction transistor in the first noise reduction module to be in a reverse bias state under the action of a second noise reduction control signal; the second noise reduction module is used for carrying out noise reduction processing on voltage on the driving control node, the driving output end and the stage transmission output end; the second noise reduction module is also used for enabling a noise reduction transistor in the second noise reduction module to be in a reverse bias state under the action of the first noise reduction control signal; according to the noise reduction circuit, the noise reduction transistors in the two groups of noise reduction modules are in the reverse bias state when not working, so that the forward bias state of the noise reduction transistors in alternate working is counteracted, the problem that the threshold voltage of the noise reduction transistors drifts is solved, and the noise reduction stability of the noise reduction circuit is improved.

The embodiment of the invention provides a preparation method of a solar cell and the solar cell, and the method comprises the steps: firstly obtaining a substrate cell piece, forming a passive film layer on the substrate cell piece, then forming a grid line on the passive film layer, and then carrying out the sintering. When the grid line is subjected to laser scanning, reverse bias voltage is applied to the grid line, meanwhile, laser scanning is carried out from the middle area of the passive film layer to the edge area, and the laser power when laser scanning is carried out on the middle area is larger than the laser power when laser scanning is carried out on the edge area. When a passive film is formed, due to the influence of a winding plating phenomenon, the passive film has the characteristics that the middle is thin and the edge is thick. The laser power of the edge area is lower, so that the process strength of the edge area can be reduced, and the temperature generated by the edge area can be reduced. Compared with the prior art, the method has the advantages that the high-temperature phenomenon of the edge area can be relieved, the abnormal black edge phenomenon caused by high process strength at the edge is effectively reduced, and the product yield and quality are improved.

The invention discloses a path planning method and device based on a photon pulse reinforcement learning network, and relates to the field of photon pulse reinforcement learning networks, and the method comprises the steps: adjusting the phase of each phase shifter in an explicit MZI network according to a multi-level pulse neural network, and configuring a weight matrix; carrying out pulse signal loading on the light source by using a light modulator to obtain an input signal; obtaining a plurality of linear calculation results by using the weight matrix and the input signal through an interference effect and a coupling effect; inputting the plurality of linear calculation results into the DFB-SA laser, and obtaining a nonlinear activation result by adjusting the injection current of a gain region of the laser and the reverse bias voltage of a saturation region of the laser; and taking the nonlinear activation result as a new input signal, and returning to the step of obtaining a plurality of linear calculation results by using the weight matrix and the input signal until calculation of all levels in the pulse neural network is completed, so that path planning which is high in speed, low in power consumption and easy to configure is realized.

Unidirectional hybrid switch. At least one example is a method operating a hybrid switch, the method comprising: sensing a voltage across an upper terminal and a lower terminal of the hybrid switch, the hybrid switch is forward biased when the upper terminal has higher voltage, and the hybrid switch is reverse biased when the lower terminal has higher voltage; when the hybrid switch is forward biased, selectively conducting a forward current from the upper terminal to the lower terminal by sharing the forward current between a FET switch and a BJT switch, the selectively conducting when a control terminal is asserted; and when the hybrid switch is reversed biased, non-selectively conducting a reverse current from the lower terminal to the upper terminal.

The invention discloses a dynamic reverse bias test method and system for a power semiconductor device, and relates to the technical field of power semiconductor device testing, and the method comprises the steps: obtaining a test parameter of a tested device, and carrying out the test circuit configuration based on the test parameter of the tested device; performing a dynamic reverse bias test based on the configured test circuit to obtain a test result; and analyzing and evaluating a test result. According to the method, the accuracy and reliability of a test result are improved, a solid foundation is provided for a subsequent dynamic reverse bias test, potential problems of the device can be found in time, it is ensured that the test result has an actual reference value, real-time data support is provided for subsequent evaluation and analysis, the performance state of the device can be accurately judged, and the reliability of the device is improved. The safety of the test process is ensured, the integrity and sufficiency of the test are ensured, and misjudgment caused by insufficient test is avoided.

The invention discloses a band-pass type active frequency selective surface based on double-element composite loading. The band-pass type active frequency selective surface comprises at least one resonance unit which is periodically arranged, the resonance unit sequentially comprises a top metal frequency selection surface layer, a first dielectric structure layer, a middle metal feed layer, a second dielectric structure layer and a bottom metal frequency selection surface layer from top to bottom; the top metal layer and the bottom metal layer are composed of square ring aperture grooves subjected to deformation processing, and the middle feed layer is of a cross zigzag metal structure, plays a role in coupling an electromagnetic field and serves as a bias network of the AFSS. And the metal through holes penetrate through the resonance units in the vertical direction, so that the middle layer feeder line can respectively provide reverse bias voltage for independently regulating and controlling the resonance frequency for the PINs and the variable capacitance diodes on the top layer and the bottom layer. According to the invention, the functions of band switching and wide-range frequency tuning can be met, so that the problem of insertion loss increase caused by limited design frequency regulation and control range and element loading of the AFSS in the prior art can be solved.

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

A reconfigurable metasurface sub reflector comprises an array of cell units. Each sub unit is formed of two sub-unit cells formed with at least two conducting layers separated by a dielectric substrate. One conducting layer has, in each of the sub-unit cells, two parallel strips connected by a varactor and the other conducting layer serves as a ground layer. Setting the reverse biasing for each of the varactors controls the azimuth and elevation of reflection from the reconfigurable metasurface sub reflector.

The invention discloses a gallium oxide solar-blind ultraviolet detector based on selective area etching and a preparation method thereof, and belongs to the technical field of semiconductor photoelectric detection. Comprises from bottom to top: a substrate; the first epitaxial layer is located on the substrate, and the first epitaxial layer is a highly doped n-Ga2O3 layer; the second epitaxial layer is located on the first epitaxial layer, and the second epitaxial layer is a lightly doped n-Ga2O3 layer; the third epitaxial layer is located on the second epitaxial layer, the third epitaxial layer is a highly-doped p-NiO layer, and the third epitaxial layer is distributed at intervals through selective area etching; and the first ohmic contact layer is located on the area where the third epitaxial layer is distributed at intervals. The detector adopts a PN junction structure working in a reverse bias state, and compared with a Schottky structure, the detector has the advantages that the built-in electric field intensity and the leakage current level of a device are less affected by high-energy photon irradiation and working environment temperature change, and the anti-irradiation performance of the device and the working capability under an extreme temperature condition are effectively improved.

The present application relates to a cell string fabrication method, a cell string, and a photovoltaic module. The cell string fabrication method comprises the following steps: providing a semiconductor substrate; performing metallization on the semiconductor substrate, so as to obtain cells; connecting the cells to a connecting member, so as to obtain a cell string precursor; and performing an illumination treatment on the cell string precursor and simultaneously applying a reverse bias voltage to the cell string precursor. By adding a target photoelectric treatment step, electric current conduction paths can be increased, and the contact between a metal and a semiconductor substrate can be improved, thereby reducing the series resistance of cells, increasing a fill factor of the cells, and improving the photoelectric conversion efficiency.

The invention relates to the technical field of solar cells, and particularly discloses a method for improving conductive contact of a micro-area of an N-type cell, which comprises the following steps of: (1) performing first micro-area conductive treatment on one side of a cell grid line of the N-type cell: scanning a first side edge of the cell grid line through a first pulse laser beam, and applying a first reverse bias voltage to the cell at the same time; and (2) performing second micro-area conductive treatment on the other side of the cell grid line of the N-type cell: scanning a second side edge, opposite to the first side edge, of the cell grid line through a second pulse laser beam, and applying second reverse bias voltage to the cell at the same time. According to the method, the pulse laser beams with more concentrated energy are used for carrying out single-side scanning on the two side edges of the grid line of the battery piece respectively, and precise treatment on the metal electrode on the basis of not damaging the passivation layer of the battery can be realized, so that the contact performance of the battery is optimized, the contact resistance of the battery is greatly reduced, and the performance of the battery piece is improved.

Embodiments of the present disclosure provide a system for fast impedance tuning. The system includes a radio frequency (RF) generator to generate power, a plasma chamber to receive the power from the RF generator and a RF matching network inserted between the RF generator and the plasma chamber configured to match a plasma load impedance to a RF generator impedance using a solid state based variable capacitor. The RF matching network includes a bias circuit that applies a reverse bias to the solid state based variable capacitor to control a capacitance value of the solid state based variable capacitor. The plasma load impedance is matched with the RF generator impedance when pulsed voltage, multi-level pulsing, or RF match ignition tuning is applied.

The invention belongs to the technical field of semiconductor testing, and discloses a thermistor performance monitoring method and system based on a power module reliability test. The method comprises the following steps: configuring a pin connection structure electrically connected with a thermistor lead on a test burn-in board for a high-temperature, high-humidity and high-voltage reverse bias test; in the process of executing a high-temperature, high-humidity and high-voltage reverse bias test on the power module comprising the thermistor, a lead of the thermistor is electrically connected with a preset current detection loop through the pin connection structure, so that monitoring current flowing through the thermistor is received by the current detection loop, and thermistor performance monitoring is executed. According to the application, the problem that the self degradation risk of the thermistor cannot be monitored in real time in the H3TRB test process to cause a monitoring blind area can be solved, the whole-process monitoring of the performance fluctuation of the thermistor in the strong electric field and high humidity coupling environment is realized, and the integrity of the reliability evaluation of the power module and the safety of the test system are remarkably improved.

A method for simulating a photodetector behavior includes: receiving an input waveform for an photodetector; receiving an input optical power and a reverse bias voltage for the photodetector; searching for, in a lookup-table library, model parameters for a photodetector behavior model based on the input optical power and the reverse bias voltage; and outputting a second waveform from the photodetector behavior model, where the second waveform is indicative of an electrical response of the photodetector receiving the input waveform.

The invention provides a leakage current detection circuit and detection equipment, and belongs to the technical field of semiconductor testing, and the leakage current detection circuit comprises a pulse output circuit, a power supply circuit, a detection circuit and a protection circuit. Wherein the output end of the pulse output circuit is used for connecting the control end of a to-be-tested power semiconductor, the first voltage end of the power supply circuit is used for connecting the first controlled end of the to-be-tested power semiconductor, and the second voltage end of the power supply circuit is connected with the first end of the detection circuit; the second end of the detection circuit is used for connecting a second controlled end of the to-be-detected power semiconductor, the first end of the protection circuit is connected with the first end of the detection circuit, and the second end of the protection circuit is connected with the second end of the detection circuit. According to the embodiment of the invention, the protection circuit provides a low-impedance path for the current peak generated by the high-speed switch of the power semiconductor to be tested, so that the dynamic change data of the leakage current can be accurately and completely obtained during the dynamic reverse bias stress test.

The invention discloses an amorphous silicon passivation layer, a preparation method thereof and a heterojunction battery, and relates to the technical field of batteries, the preparation method comprises the following steps: depositing a first passivation layer on a crystalline silicon substrate by using a first reaction gas, the first reaction gas comprising hydrogen and silane, the flow ratio of hydrogen to silane being (1: 10)-(20: 1); a second reaction gas is adopted to deposit a second passivation layer on the first passivation layer, the second reaction gas comprises hydrogen and silane, and the flow ratio of the hydrogen to the silane is larger than 3: 1 and larger than the flow ratio of the hydrogen to the silane in the first reaction gas; in the step S1, reverse bias voltage is applied to the crystalline silicon substrate, so that the surface potential of the crystalline silicon substrate is below 0.5 eV; in the step S2, bias voltage is applied to the crystalline silicon substrate so as to increase the surface potential of the crystalline silicon substrate. According to the crystalline silicon substrate passivation film prepared by the preparation method, the stability, the electrical performance and the heterogeneous interface passivation performance of a material are improved, and the efficiency and the long-term stability of a heterojunction battery are improved.

According to the multi-beam laser-induced sintering method, a first electrode is arranged on the first surface of a photovoltaic cell to make contact with a first grid line, a second electrode is arranged on the second surface or the first surface of the photovoltaic cell to make contact with a second grid line, and the first electrode and the second electrode are connected with the positive electrode and the negative electrode of a power source respectively to apply reverse bias voltage to the cell; and a plurality of split light spots are adopted to simultaneously scan different scanning areas of the photovoltaic cell for laser-induced sintering. The scanning area is divided into a plurality of strip-shaped blocks in the direction perpendicular to the extending direction of the first electrode, one light splitting light spot corresponds to one scanning area for laser scanning, and different light splitting light spots are different in power density. By means of the method, the laser-induced machining effects of the areas close to and away from the first electrode tend to be consistent; the situation that multiple split light irradiates the same grid line at the same time to reduce the influence of generated large current on the grid line and a cell substrate is avoided, and the laser-induced sintering effect is improved; and the bad EL black edge caused by reverse breakdown and over-processing of the edge area of the battery piece is avoided.

The invention discloses a multi-dimensional doped profile optimized ultrathin body MOSFET device and a preparation process thereof, and belongs to the technical field of semiconductor devices, the multi-dimensional doped profile optimized ultrathin body MOSFET device comprises a plurality of MOS cells which are parallel to one another, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell, side symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, the side symmetric P-layers are of rectangular outlines, and the top ends of the side symmetric P-layers make contact with the grid electrode; in the first embodiment, the laterally symmetrical P-layer and the N drift layer form a PN junction, a transverse depletion region is generated during reverse bias, the transverse electric field range is expanded, and local electric field concentration is avoided.

The utility model belongs to the technical field of reverse bias tests, and particularly relates to an advanced high-performance high-temperature high-humidity intelligent reverse bias test device which comprises a test box, a heating module and a humidifying module are installed on the test box, the heating module comprises a heat supply pipeline and two extension pipes integrally formed on the two sides of the heat supply pipeline, and the humidifying module is installed on the test box. The extension pipe is rotationally connected to the test box, the heat supply pipeline communicates with a first nozzle and a second nozzle which are distributed at equal intervals in the length direction of the heat supply pipeline, and the first nozzle and the second nozzle are each provided with a first valve; the aging test board is fixed at the bottom of the inner side of the test box. According to the utility model, the rotatable heat supply pipeline is arranged in the heating module, the heat supply pipeline is communicated with the nozzle, and the nozzle can realize direct heating of the semiconductor device, so that the internal environment of the test box does not need to be preheated, the speed is high, the heat supply temperature can be adjusted, and the problem of low test speed of the device at the present stage is solved.

The invention relates to the technical field of wafer testing, and discloses a wafer aging test system and method with a dynamic gate bias and reverse bias test function, and the system comprises a main control board, an industrial control computer, a high-voltage source, a source meter, a high-voltage switching board, a test switching board, and a needle card board. Dynamic high-temperature reverse bias and dynamic high-temperature gate bias tests can be added on the basis of static high-temperature reverse bias and reverse bias tests, higher requirements for SiC power device reliability testing equipment in the industry are met, stress borne by a chip under the actual working condition can be simulated, and the reliability of the SiC power device is improved. And the threshold voltage is monitored on line in real time while the pulse voltage is implemented, so that the reliability of the chip can be better evaluated.

The invention provides a silicon substrate gallium nitride power semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The device comprises a first silicon substrate layer, a second substrate layer, a substrate electrode and a gallium nitride device layer, the second substrate layer comprises a laminated structure which is periodically arranged; the laminated structure sequentially comprises a substrate functional layer and a second silicon substrate layer from bottom to top; wherein the first silicon substrate layer and the second silicon substrate layer adopt a first type of doping, and the substrate functional layer adopts a second type of doping, so that a bipolar doped substrate structure is formed. Based on this, when the silicon substrate gallium nitride power semiconductor device is in a high-voltage reverse bias state, at least one PN junction in the bipolar doped substrate structure can be in a reverse bias state due to the potential difference between the lower substrate electrode and the drain electrode of the silicon substrate gallium nitride power semiconductor device; and the breakdown voltage of the silicon substrate gallium nitride power semiconductor device in the vertical direction is further improved.

The invention provides a thin film photovoltaic module, a laminated photovoltaic module and power generation equipment, and relates to the field of photovoltaic technology. The thin film photovoltaic module comprises a substrate, a battery pack and a bypass structure, the battery pack is arranged on the substrate, and the battery pack comprises a plurality of sub-batteries which are sequentially connected in series. The sub-battery comprises a first electrode, a battery layer and a second electrode which are sequentially stacked, the first electrode is in contact with the substrate, the first electrode comprises a first sub-electrode and a second sub-electrode which are arranged at an interval, and the second electrode is in contact with the first sub-electrode. The bypass structure is used for being connected with the battery pack in parallel, in the bypass structure and the battery pack which are connected in parallel, the bypass structure is electrically connected with the second electrode of the sub-battery located at one end of the battery pack and the second sub-electrode of the sub-battery located at the other end of the battery pack, and the bypass structure is conducted under the condition that one sub-battery in the battery pack is shielded. And reverse bias protection can be realized for a plurality of sub-batteries in the battery pack through the bypass structure, so that the processing cost can be reduced.

The invention discloses a semiconductor device power cycle and high-temperature reverse bias coupling test method and system, and relates to the field of semiconductor device tests.The method comprises the steps that test conditions are set, and a first parameter is obtained; based on the first parameter, setting a switching period of the high-temperature reverse bias test and the power cycle test, and setting an initial state; performing first judgment on the cycle index of the to-be-tested device based on the initial state; selecting to carry out a power cycle test or a high-temperature reverse bias test based on a result of the first judgment; after aging failure of the device is detected in the power cycle test or the high-temperature reverse bias test or all preset test periods are completed, the test is ended; according to the invention, a complete power cycle test can be carried out on the device, a high-temperature reverse bias test can be carried out on the tested device while the power cycle test is carried out on other test branches, and the coupling test of power cycle and high-temperature reverse bias of the semiconductor device is realized.

The present invention relates to the field of optical components, and in particular to a multi-wavelength silicon optical transmitter chip, whose input waveguide is used to input dual-band optical signals. A first multimode interference coupler is connected to the input waveguide and is used to distribute the dual-band optical signals from the input waveguide to two transmission paths. Each transmission path includes a silicon optical modulator and two second multimode interference couplers. The silicon optical modulator is connected between the two second multimode interference couplers via a waveguide. The silicon optical modulator includes a reverse bias electrode and two high-frequency electrodes, the two high-frequency electrodes being located on opposite sides of the waveguide and connected to the waveguide, and the reverse bias electrode being located in the middle of the waveguide. The high-frequency electrode includes multiple sub-electrodes arranged along a first direction, each of the multiple sub-electrodes including a main body, a connecting portion, and an end portion. The connecting portion and the end portion are connected to one side of the main body along a second direction, and the connecting portion and the end portion form a T-shaped structure. The end portion extends toward the waveguide and is connected to the waveguide. High-speed signal modulation is achieved.

The invention provides a preparation method of a solar cell and the solar cell, and relates to the technical field of solar cells, and the method comprises the steps: firstly obtaining a cell main body sheet, then forming a passivation protection layer on the surface of the cell main body sheet, and then printing on the passivation protection layer to form a grid line. After the grid lines are formed, a first preset reverse bias voltage can be applied to the edge grid lines, a second preset reverse bias voltage can be applied to the middle grid lines, and then laser scanning is carried out. Compared with the prior art, the embodiment of the invention has the advantages that different preset reverse bias voltages are applied to different probe rows, a row of probe rows is newly added at the edge and smaller bias voltage is applied, so that the actual potential at the pressing point can be reduced, and the pressing point is not influenced by the reverse bias voltage applied to the middle probe row. The voltage of the edge area is small, the high temperature problem caused by scanning after bias voltage is applied can be effectively relieved, the abnormal phenomenon of black edges is effectively reduced, and the product yield and quality are improved.

The invention discloses an APD epitaxial wafer breakdown voltage testing method, which comprises the following steps of: (1) selectively corroding an APD epitaxial wafer, and ensuring that an uncorroded layer is a to-be-tested epitaxial layer (the upper surface is a P-type semiconductor region) and a corroded layer is a residual layer (the upper surface is an N-type semiconductor region); (2) dotting indium in the P-type semiconductor region to form an upper electrode, and dotting indium in the N-type semiconductor region to form a lower electrode; (3) connecting a positive electrode probe of a parameter analyzer with a lower electrode, connecting a negative electrode probe with an upper electrode, gradually applying reverse bias voltage from zero, and monitoring and recording a reverse bias voltage value, namely breakdown voltage Vbr, in real time when the current is subjected to avalanche increase; and (4) carrying out statistical analysis on all the breakdown voltage values on the same APD epitaxial wafer to obtain a final breakdown voltage value. The method effectively overcomes the problems of large test result deviation, low accuracy, long period and high cost in the traditional technology, can quickly evaluate the quality of the epitaxial wafer material, and is mainly used for process monitoring and material screening.

The invention discloses an optimal linear point searching method for a silicon-based Mach-Zehnder modulator. According to the method, the linearity of a corresponding working point is estimated according to the power of a fundamental component and a third-order intermodulation component of an output signal of the modulator, and the optimal linear point of the modulator can be obtained based on the maximum estimated value of the linearity. According to the method, a maximum entropy spectral subtraction method is adopted to reduce a signal noise floor, and a violent search method is adopted to retrieve an optimal combination of a modulator upper and lower arm phase difference and a reverse bias voltage to obtain an optimal working point. Compared with a conventional linearity test method that the linearity is obtained by testing when the working point of the modulator is set to be an orthogonal point, the optimal linear point searched by the method can obviously improve the linearity of the modulator, and a high-linearity silicon-based integrated microwave photon system can be realized.

The invention provides a laser-induced sintering processing method and a laser-induced sintering processing device, which are used for carrying out partitioned laser-induced sintering on a double-sided electrode photovoltaic cell. Respectively arranging a second electrode and a first electrode on the second surface and the first surface of the battery piece to contact the second surface and the first surface grid line, applying a first reverse bias to the battery piece, enabling the first electrode to contact the edge area, and scanning the middle area by laser; and arranging a second electrode and a third electrode on the second surface and the first surface of the cell to contact the second surface and the first surface grid line, applying a second reverse bias to the cell, enabling the third electrode to contact the middle area, and scanning the edge area by laser. The middle region is the middle region in the extending direction of the fine grid, and the edge regions are regions at two ends. The second reverse bias voltage is smaller than the first reverse bias voltage, higher reverse bias voltage is loaded to the middle area of the photovoltaic cell to promote the laser-induced sintering treatment degree, lower reverse bias voltage is applied to the edge area, reverse breakdown is avoided, and the poor EL black edge caused by over-treatment is prevented.