379 results about "Reverse bias" patented technology

The invention discloses a path planning method and device based on a photon pulse reinforcement learning network, and relates to the field of photon pulse reinforcement learning networks, and the method comprises the steps: adjusting the phase of each phase shifter in an explicit MZI network according to a multi-level pulse neural network, and configuring a weight matrix; carrying out pulse signal loading on the light source by using a light modulator to obtain an input signal; obtaining a plurality of linear calculation results by using the weight matrix and the input signal through an interference effect and a coupling effect; inputting the plurality of linear calculation results into the DFB-SA laser, and obtaining a nonlinear activation result by adjusting the injection current of a gain region of the laser and the reverse bias voltage of a saturation region of the laser; and taking the nonlinear activation result as a new input signal, and returning to the step of obtaining a plurality of linear calculation results by using the weight matrix and the input signal until calculation of all levels in the pulse neural network is completed, so that path planning which is high in speed, low in power consumption and easy to configure is realized.

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

A reconfigurable metasurface sub reflector comprises an array of cell units. Each sub unit is formed of two sub-unit cells formed with at least two conducting layers separated by a dielectric substrate. One conducting layer has, in each of the sub-unit cells, two parallel strips connected by a varactor and the other conducting layer serves as a ground layer. Setting the reverse biasing for each of the varactors controls the azimuth and elevation of reflection from the reconfigurable metasurface sub reflector.

The invention discloses a gallium oxide solar-blind ultraviolet detector based on selective area etching and a preparation method thereof, and belongs to the technical field of semiconductor photoelectric detection. Comprises from bottom to top: a substrate; the first epitaxial layer is located on the substrate, and the first epitaxial layer is a highly doped n-Ga2O3 layer; the second epitaxial layer is located on the first epitaxial layer, and the second epitaxial layer is a lightly doped n-Ga2O3 layer; the third epitaxial layer is located on the second epitaxial layer, the third epitaxial layer is a highly-doped p-NiO layer, and the third epitaxial layer is distributed at intervals through selective area etching; and the first ohmic contact layer is located on the area where the third epitaxial layer is distributed at intervals. The detector adopts a PN junction structure working in a reverse bias state, and compared with a Schottky structure, the detector has the advantages that the built-in electric field intensity and the leakage current level of a device are less affected by high-energy photon irradiation and working environment temperature change, and the anti-irradiation performance of the device and the working capability under an extreme temperature condition are effectively improved.

Embodiments of the present disclosure provide a system for fast impedance tuning. The system includes a radio frequency (RF) generator to generate power, a plasma chamber to receive the power from the RF generator and a RF matching network inserted between the RF generator and the plasma chamber configured to match a plasma load impedance to a RF generator impedance using a solid state based variable capacitor. The RF matching network includes a bias circuit that applies a reverse bias to the solid state based variable capacitor to control a capacitance value of the solid state based variable capacitor. The plasma load impedance is matched with the RF generator impedance when pulsed voltage, multi-level pulsing, or RF match ignition tuning is applied.

The invention belongs to the technical field of semiconductor testing, and discloses a thermistor performance monitoring method and system based on a power module reliability test. The method comprises the following steps: configuring a pin connection structure electrically connected with a thermistor lead on a test burn-in board for a high-temperature, high-humidity and high-voltage reverse bias test; in the process of executing a high-temperature, high-humidity and high-voltage reverse bias test on the power module comprising the thermistor, a lead of the thermistor is electrically connected with a preset current detection loop through the pin connection structure, so that monitoring current flowing through the thermistor is received by the current detection loop, and thermistor performance monitoring is executed. According to the application, the problem that the self degradation risk of the thermistor cannot be monitored in real time in the H3TRB test process to cause a monitoring blind area can be solved, the whole-process monitoring of the performance fluctuation of the thermistor in the strong electric field and high humidity coupling environment is realized, and the integrity of the reliability evaluation of the power module and the safety of the test system are remarkably improved.

According to the multi-beam laser-induced sintering method, a first electrode is arranged on the first surface of a photovoltaic cell to make contact with a first grid line, a second electrode is arranged on the second surface or the first surface of the photovoltaic cell to make contact with a second grid line, and the first electrode and the second electrode are connected with the positive electrode and the negative electrode of a power source respectively to apply reverse bias voltage to the cell; and a plurality of split light spots are adopted to simultaneously scan different scanning areas of the photovoltaic cell for laser-induced sintering. The scanning area is divided into a plurality of strip-shaped blocks in the direction perpendicular to the extending direction of the first electrode, one light splitting light spot corresponds to one scanning area for laser scanning, and different light splitting light spots are different in power density. By means of the method, the laser-induced machining effects of the areas close to and away from the first electrode tend to be consistent; the situation that multiple split light irradiates the same grid line at the same time to reduce the influence of generated large current on the grid line and a cell substrate is avoided, and the laser-induced sintering effect is improved; and the bad EL black edge caused by reverse breakdown and over-processing of the edge area of the battery piece is avoided.

The invention discloses a multi-dimensional doped profile optimized ultrathin body MOSFET device and a preparation process thereof, and belongs to the technical field of semiconductor devices, the multi-dimensional doped profile optimized ultrathin body MOSFET device comprises a plurality of MOS cells which are parallel to one another, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell, side symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, the side symmetric P-layers are of rectangular outlines, and the top ends of the side symmetric P-layers make contact with the grid electrode; in the first embodiment, the laterally symmetrical P-layer and the N drift layer form a PN junction, a transverse depletion region is generated during reverse bias, the transverse electric field range is expanded, and local electric field concentration is avoided.

The invention relates to the technical field of wafer testing, and discloses a wafer aging test system and method with a dynamic gate bias and reverse bias test function, and the system comprises a main control board, an industrial control computer, a high-voltage source, a source meter, a high-voltage switching board, a test switching board, and a needle card board. Dynamic high-temperature reverse bias and dynamic high-temperature gate bias tests can be added on the basis of static high-temperature reverse bias and reverse bias tests, higher requirements for SiC power device reliability testing equipment in the industry are met, stress borne by a chip under the actual working condition can be simulated, and the reliability of the SiC power device is improved. And the threshold voltage is monitored on line in real time while the pulse voltage is implemented, so that the reliability of the chip can be better evaluated.

The invention provides a silicon substrate gallium nitride power semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The device comprises a first silicon substrate layer, a second substrate layer, a substrate electrode and a gallium nitride device layer, the second substrate layer comprises a laminated structure which is periodically arranged; the laminated structure sequentially comprises a substrate functional layer and a second silicon substrate layer from bottom to top; wherein the first silicon substrate layer and the second silicon substrate layer adopt a first type of doping, and the substrate functional layer adopts a second type of doping, so that a bipolar doped substrate structure is formed. Based on this, when the silicon substrate gallium nitride power semiconductor device is in a high-voltage reverse bias state, at least one PN junction in the bipolar doped substrate structure can be in a reverse bias state due to the potential difference between the lower substrate electrode and the drain electrode of the silicon substrate gallium nitride power semiconductor device; and the breakdown voltage of the silicon substrate gallium nitride power semiconductor device in the vertical direction is further improved.

The invention provides a thin film photovoltaic module, a laminated photovoltaic module and power generation equipment, and relates to the field of photovoltaic technology. The thin film photovoltaic module comprises a substrate, a battery pack and a bypass structure, the battery pack is arranged on the substrate, and the battery pack comprises a plurality of sub-batteries which are sequentially connected in series. The sub-battery comprises a first electrode, a battery layer and a second electrode which are sequentially stacked, the first electrode is in contact with the substrate, the first electrode comprises a first sub-electrode and a second sub-electrode which are arranged at an interval, and the second electrode is in contact with the first sub-electrode. The bypass structure is used for being connected with the battery pack in parallel, in the bypass structure and the battery pack which are connected in parallel, the bypass structure is electrically connected with the second electrode of the sub-battery located at one end of the battery pack and the second sub-electrode of the sub-battery located at the other end of the battery pack, and the bypass structure is conducted under the condition that one sub-battery in the battery pack is shielded. And reverse bias protection can be realized for a plurality of sub-batteries in the battery pack through the bypass structure, so that the processing cost can be reduced.

The invention provides a preparation method of a solar cell and the solar cell, and relates to the technical field of solar cells, and the method comprises the steps: firstly obtaining a cell main body sheet, then forming a passivation protection layer on the surface of the cell main body sheet, and then printing on the passivation protection layer to form a grid line. After the grid lines are formed, a first preset reverse bias voltage can be applied to the edge grid lines, a second preset reverse bias voltage can be applied to the middle grid lines, and then laser scanning is carried out. Compared with the prior art, the embodiment of the invention has the advantages that different preset reverse bias voltages are applied to different probe rows, a row of probe rows is newly added at the edge and smaller bias voltage is applied, so that the actual potential at the pressing point can be reduced, and the pressing point is not influenced by the reverse bias voltage applied to the middle probe row. The voltage of the edge area is small, the high temperature problem caused by scanning after bias voltage is applied can be effectively relieved, the abnormal phenomenon of black edges is effectively reduced, and the product yield and quality are improved.

The invention discloses an APD epitaxial wafer breakdown voltage testing method, which comprises the following steps of: (1) selectively corroding an APD epitaxial wafer, and ensuring that an uncorroded layer is a to-be-tested epitaxial layer (the upper surface is a P-type semiconductor region) and a corroded layer is a residual layer (the upper surface is an N-type semiconductor region); (2) dotting indium in the P-type semiconductor region to form an upper electrode, and dotting indium in the N-type semiconductor region to form a lower electrode; (3) connecting a positive electrode probe of a parameter analyzer with a lower electrode, connecting a negative electrode probe with an upper electrode, gradually applying reverse bias voltage from zero, and monitoring and recording a reverse bias voltage value, namely breakdown voltage Vbr, in real time when the current is subjected to avalanche increase; and (4) carrying out statistical analysis on all the breakdown voltage values on the same APD epitaxial wafer to obtain a final breakdown voltage value. The method effectively overcomes the problems of large test result deviation, low accuracy, long period and high cost in the traditional technology, can quickly evaluate the quality of the epitaxial wafer material, and is mainly used for process monitoring and material screening.

The invention provides a laser-induced sintering processing method and a laser-induced sintering processing device, which are used for carrying out partitioned laser-induced sintering on a double-sided electrode photovoltaic cell. Respectively arranging a second electrode and a first electrode on the second surface and the first surface of the battery piece to contact the second surface and the first surface grid line, applying a first reverse bias to the battery piece, enabling the first electrode to contact the edge area, and scanning the middle area by laser; and arranging a second electrode and a third electrode on the second surface and the first surface of the cell to contact the second surface and the first surface grid line, applying a second reverse bias to the cell, enabling the third electrode to contact the middle area, and scanning the edge area by laser. The middle region is the middle region in the extending direction of the fine grid, and the edge regions are regions at two ends. The second reverse bias voltage is smaller than the first reverse bias voltage, higher reverse bias voltage is loaded to the middle area of the photovoltaic cell to promote the laser-induced sintering treatment degree, lower reverse bias voltage is applied to the edge area, reverse breakdown is avoided, and the poor EL black edge caused by over-treatment is prevented.

The utility model provides a single-photon avalanche diode, a photoelectric detection device and electronic equipment. The single-photon avalanche diode comprises a substrate layer, a first doped region, a second doped region, an isolation region, a first electrode and a second electrode, the first doped region is located above the substrate layer, the second doped region is located above the first doped region, and the net doping type of the first doped region is opposite to that of the second doped region, so that a PN junction is formed between the first doped region and the second doped region, and depletion regions are formed on two sides of an interface of the PN junction; the isolation region is attached to the outer sides of the first doped region and the second doped region in the horizontal direction, and is constructed to at least cover the region between the upper interface of the second doped region and the lower interface of the first doped region in the height direction; the first electrode and the second electrode are configured to apply a reverse bias voltage to the PN junction to form an avalanche region in the depletion region. According to the single-photon avalanche diode, the size of a middle strong longitudinal electric field region cannot be affected when the overall size is reduced.

The application belongs to the technical field of semiconductor devices, and provides a vertical structure power device, a preparation method and electronic equipment. The vertical structure power device comprises a drain doped layer, a drift layer, a reverse type super junction, a doped semiconductor column, a surface work function metal, a dielectric layer and a source doped layer. The reverse withstand voltage of the power device is improved by the lower doped drift layer, then the reverse type super junction is arranged in the drift layer to change the electric field distribution in the drift layer, reduce the maximum electric field at the channel and the drift layer interface, and avoid the problem that the device reliability is reduced due to the avalanche effect caused by the high electric field when the reverse bias voltage is connected.

The invention belongs to the technical field of semiconductor optoelectronic devices, and particularly relates to an optical computing array based on a reverse bias germanium modulator, which comprises a cross matrix formed by crossing a plurality of rows of mutually parallel input optical waveguides and a plurality of columns of mutually parallel output optical waveguides, a photoelectric detector is arranged at the output end of each row of output optical waveguides; a plurality of optical splitters; each germanium modulator corresponds to one crossed waveguide, and the first input end of each germanium modulator is connected with the output end of the optical splitter through a transmission optical waveguide; each light combiner is connected with the output end of the germanium modulator and the output optical waveguide, through the above structure, the computing array which has a thermal compensation mechanism, can reduce light reflection and is high in responsivity is comprehensively provided, and therefore under the condition that frequent switching is met, the computing array has the advantages that the computing efficiency is improved, and the computing efficiency is improved. And a low-power-consumption large-scale integrated calculation array scheme is realized.

The invention discloses a power diode based on an MOF, a preparation method, a 3D chip packaging method and application, belongs to the technical field of electronic materials and power devices, and particularly relates to a composite structure based on an n-Si substrate / an (n-Si)-(ZIF-8) composite layer / an Ag layer, preparation, a 3D chip packaging method and application of the composite structure in the field of power devices. The reverse withstand voltage of the power diode based on the n-Si substrate / ''(n-Si)-(ZIF-8) composite layer'' / Ag layer composite structure exceeds 200V, the forward conduction voltage of the power diode is 0.25-1.5 V, the reverse bias voltage applied to the power diode is 0-200V, the reverse leakage current is basically not increased along with the increase of the reverse bias voltage, and the reverse leakage current is 0.2-2.1 mA (at the reverse voltage-100V). Compared with a conventional power diode based on an n-Si substrate / Ag layer Schottky structure, the performance of the power diode provided by the invention has the advantages that although the forward voltage is basically unchanged, the reverse voltage is increased by 80-400%, the reverse saturation current is reduced by 50-800%, and the highest yield reaches 95%.

In a signal processing circuit, an input terminal is configured to receive an analog signal output from an avalanche photodiode operating in Geiger mode. A comparison circuit outputs a signal based on a component exceeding a threshold among components a signal input to the comparison circuit. The adjustment circuit includes an AC coupling unit, a level shifter unit, and a reference value adjustment unit. The AC coupling unit establishes AC coupling between the input terminal and the comparison circuit. The level shifter unit adjusts the voltage of the signal input to the comparison circuit to a value lower than a reverse bias voltage applied to the avalanche photodiode. The reference value adjustment unit adjusts the reference value of the signal input to the comparison circuit.

Embodiments of the present disclosure provide a system for fast impedance tuning. The system includes a radio frequency (RF) generator to generate power, a plasma chamber to receive the power from the RF generator and a RF matching network inserted between the RF generator and the plasma chamber configured to match a plasma load impedance to a RF generator impedance using a solid state based variable capacitor. The RF matching network includes a bias circuit that applies a reverse bias to the solid state based variable capacitor to control a capacitance value of the solid state based variable capacitor. The plasma load impedance is matched with the RF generator impedance when pulsed voltage, multi-level pulsing, or RF match ignition tuning is applied.

A dual-mode asymmetric P-I-N perovskite radiation detector and its fabrication method are disclosed, belonging to the field of radiation detector technology. The method first involves preparing a perovskite single-crystal precursor solution. A small amount of this solution is used for seed crystal growth at a constant temperature, with the seed crystal serving as the seed for CsPbBr3 single-crystal growth on a P-type substrate. Next, a MAPbBr3 solution is prepared, and MAPbBr3 single crystals are grown to form the I layer. Finally, MAPbBr3 (Bi) is prepared... 3+ A doped solution was used to grow MAPbBr3 (Bi) as the N-layer. 3+ A dual-mode asymmetric P-I-N perovskite radiation detector is obtained by fabricating top and bottom electrodes using a doped single crystal. This invention utilizes the forward conduction and reverse cutoff characteristics of the P-I-N structure. When a negative voltage is applied to the N layer for forward bias, X-rays incident on the P layer are used for radiation detection, exciting the photoconductivity gain and achieving a sensitivity far exceeding that of CsPbBr3 single crystals; simultaneously, MAPbBr3 (Bi 3+ The doped single crystal has a natural shielding effect on soft X-rays, enabling high-sensitivity detection of hard X-rays in the I layer when X-rays are incident on the N layer with positive pressure and reverse P-I-N bias.

A direct current (DC) hybrid circuit breaker (HCB) includes a current sensor and a variable inductor. In the event of a short circuit fault current reaches a preset threshold, the current sensor will send a tripping signal to a controller, and the controller will command the gate drivers to conduct all the switches in the semiconductor switch path. This action will allow the fault current to be commuted to the power stack. When the current in a fast mechanical switch branch drops to near zero, the variable inductor will be driven out of the saturation and the secondary winding will send out a “safe-to-open” signal to the controller. After receiving the “safe-to-open” signal, the controller will initiate the turn off sequence of the fast mechanical switch path.

Disclosed is a system and method for solid-state 2D optical phased arrays (OPAs), which are fabricated from InGaN / AlGaN multiple quantum wells (MQWs) and AlyGa1-yN / AlxGa1-xN (y<x) MQWs. The InGaN / AlGaN MQWs and AlyGa1-yN / AlxGa1-xN (y<x) MQWs include alternating p-type and n-type layers to form p-n-p-n MQW structures to allow the OPA to operate in the reversed biased configuration to further minimize the operating current and heat generation. The phase in each pixel within the OPA will be controlled independently via electro-optic effect in III-nitride MQWs by varying the voltage in each pixel by a Si CMOS array to achieve the manipulation of the distribution of optical power in the far field and steering of the main laser beam. The present disclosure is applicable to a wide range of applications, including the operation of LIDAR systems, laser weapons, laser illuminators, and laser imaging systems.

To provide a technique of photon detection efficiency (PDE) modulation with multi-junction single-photon avalanche diode (SPAD) pixels.SOLUTION: A sensing device includes an array of sensing elements and a bias control circuit. Each sensing element of the array of sensing elements includes (i) a photosensitive material, which is configured to generate photoelectrons in response to incident optical radiation, and (ii) a plurality of avalanche diodes, which are disposed at different, respective locations within the sensing element in electrical communication with the photosensitive material and are configured, when reverse-biased, to generate electrical avalanches in response to the generated photoelectrons. The bias control circuit is configured to selectively set respective reverse-bias voltage levels of the avalanche diodes within each sensing element to different, respective values.SELECTED DRAWING: Figure 1

This disclosure provides an electro-optic modulator, including a modulator body and an equalization circuit. The equalization circuit includes: a first doped semiconductor, including a first N-type doped region and a first P-type doped region, the first N-type doped region being connected to a first electrode and a signal input terminal, the first P-type doped region being connected to a second electrode and an electrode arm, the first electrode and the second electrode being used to receive a first control voltage with reverse bias; and a second doped semiconductor, including a second N-type doped region and a second P-type doped region, the first end of the second N-type doped region and the first end of the second P-type doped region being both connected to the signal input terminal, the second end of the second N-type doped region and the second end of the second P-type doped region being both connected to the electrode arm, the first end of the second P-type doped region being further connected to a third electrode, the second end of the second N-type doped region being further connected to a fourth electrode, the third electrode and the fourth electrode being used to receive a second control voltage.

The present invention relates to a broad-area diode laser (BAL) comprising an integrated p-n tunnel junction. The present invention in particular relates to a high-performance broad-area diode laser in which, in order to improve the beam quality and to reduce the thermal resistance, a p-n tunnel junction, biased in the reverse direction, is integrated in the layer system of the diode laser.A laser diode according to the invention comprises an active layer (20) formed between an n-doped semiconductor material (10, 12, 14) and a p-doped semiconductor material (30, 32, 34), the active layer (20) forming, along a longitudinal axis, an active zone for generating electromagnetic radiation; wherein at least one n-doped intermediate layer (50, 54) is arranged between an overlying p-side metal contact (52) and the p-doped semiconductor material (30, 32, 34), and, in the at least one n-doped intermediate layer (50, 54) in the region above the active zone, a p-n tunnel junction (40) being formed which is directly adjacent to the p-doped semiconductor material (30, 32, 34).

The present application belongs to the field of display drive technology, and specifically relates to a noise reduction circuit and a gate drive circuit, wherein the noise reduction circuit includes: a noise reduction control unit, which is used to output a noise reduction signal during the non-scanning time of the scanning phase of the current-stage gate drive module under the action of a noise reduction control signal output from a noise reduction control end and a voltage on a drive control node; a noise reduction execution unit, which is used to perform noise reduction processing on the voltages on the drive control node, the drive output end, and the stage transmission output end according to the noise reduction signal; and a threshold correction unit, which is used to place the transistors in the noise reduction execution unit in a reverse bias state during the blanking phase. The present application uses the threshold correction unit to place the transistors in the noise reduction execution unit in a reverse bias state during the blanking phase to offset the forward bias state of the transistors in the noise reduction execution unit during noise reduction, thereby improving the problem of threshold voltage drift of the noise reduction transistor and improving the noise reduction stability of the noise reduction circuit.

The present invention relates to a control system (20) and method for controlling the flow of current between a voltage source (22) and a multiphase motor or other application / load for controlling a multiphase motor (28). The control system includes, between each phase of the multiphase motor and the voltage source: a high-side diode (30A-C) and a high-side switch (34A-C) positioned in parallel between a positive terminal of the voltage source and the motor, wherein the high-side diode is reverse biased with respect to the positive terminal; and a low-side diode (32A-C) and a low-side switch (36A-C) positioned in parallel between a negative terminal of the voltage source and the motor, wherein the low-side diode is reverse biased with respect to the motor. The control system operates the high-side and low-side switches to provide efficient operation of the motor.

According to an aspect, a detection device includes: a substrate; photodiodes in each of which a lower electrode, a lower buffer layer, an active layer, an upper buffer layer, and an upper electrode are stacked; drive transistors corresponding to the photodiodes; and a gate line coupled to gates of the drive transistors. The photodiodes includes a first photodiode and a second photodiode arranged in the first direction. The first photodiode is configured to be driven in a reverse bias state and the second photodiode is configured to be driven in a forward bias state during a first period in which an output of the first photodiode is detected. The second photodiode is configured to be driven in the reverse bias state and the first photodiode is configured to be driven in the forward bias state during a second period in which an output of the second photodiode is detected.