218 results about "Reverse bias" patented technology

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

The invention discloses a gallium oxide solar-blind ultraviolet detector based on selective area etching and a preparation method thereof, and belongs to the technical field of semiconductor photoelectric detection. Comprises from bottom to top: a substrate; the first epitaxial layer is located on the substrate, and the first epitaxial layer is a highly doped n-Ga2O3 layer; the second epitaxial layer is located on the first epitaxial layer, and the second epitaxial layer is a lightly doped n-Ga2O3 layer; the third epitaxial layer is located on the second epitaxial layer, the third epitaxial layer is a highly-doped p-NiO layer, and the third epitaxial layer is distributed at intervals through selective area etching; and the first ohmic contact layer is located on the area where the third epitaxial layer is distributed at intervals. The detector adopts a PN junction structure working in a reverse bias state, and compared with a Schottky structure, the detector has the advantages that the built-in electric field intensity and the leakage current level of a device are less affected by high-energy photon irradiation and working environment temperature change, and the anti-irradiation performance of the device and the working capability under an extreme temperature condition are effectively improved.

The invention belongs to the technical field of semiconductor testing, and discloses a thermistor performance monitoring method and system based on a power module reliability test. The method comprises the following steps: configuring a pin connection structure electrically connected with a thermistor lead on a test burn-in board for a high-temperature, high-humidity and high-voltage reverse bias test; in the process of executing a high-temperature, high-humidity and high-voltage reverse bias test on the power module comprising the thermistor, a lead of the thermistor is electrically connected with a preset current detection loop through the pin connection structure, so that monitoring current flowing through the thermistor is received by the current detection loop, and thermistor performance monitoring is executed. According to the application, the problem that the self degradation risk of the thermistor cannot be monitored in real time in the H3TRB test process to cause a monitoring blind area can be solved, the whole-process monitoring of the performance fluctuation of the thermistor in the strong electric field and high humidity coupling environment is realized, and the integrity of the reliability evaluation of the power module and the safety of the test system are remarkably improved.

The invention discloses a multi-dimensional doped profile optimized ultrathin body MOSFET device and a preparation process thereof, and belongs to the technical field of semiconductor devices, the multi-dimensional doped profile optimized ultrathin body MOSFET device comprises a plurality of MOS cells which are parallel to one another, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell, side symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, the side symmetric P-layers are of rectangular outlines, and the top ends of the side symmetric P-layers make contact with the grid electrode; in the first embodiment, the laterally symmetrical P-layer and the N drift layer form a PN junction, a transverse depletion region is generated during reverse bias, the transverse electric field range is expanded, and local electric field concentration is avoided.

The invention discloses an APD epitaxial wafer breakdown voltage testing method, which comprises the following steps of: (1) selectively corroding an APD epitaxial wafer, and ensuring that an uncorroded layer is a to-be-tested epitaxial layer (the upper surface is a P-type semiconductor region) and a corroded layer is a residual layer (the upper surface is an N-type semiconductor region); (2) dotting indium in the P-type semiconductor region to form an upper electrode, and dotting indium in the N-type semiconductor region to form a lower electrode; (3) connecting a positive electrode probe of a parameter analyzer with a lower electrode, connecting a negative electrode probe with an upper electrode, gradually applying reverse bias voltage from zero, and monitoring and recording a reverse bias voltage value, namely breakdown voltage Vbr, in real time when the current is subjected to avalanche increase; and (4) carrying out statistical analysis on all the breakdown voltage values on the same APD epitaxial wafer to obtain a final breakdown voltage value. The method effectively overcomes the problems of large test result deviation, low accuracy, long period and high cost in the traditional technology, can quickly evaluate the quality of the epitaxial wafer material, and is mainly used for process monitoring and material screening.

The invention discloses a power diode based on an MOF, a preparation method, a 3D chip packaging method and application, belongs to the technical field of electronic materials and power devices, and particularly relates to a composite structure based on an n-Si substrate / an (n-Si)-(ZIF-8) composite layer / an Ag layer, preparation, a 3D chip packaging method and application of the composite structure in the field of power devices. The reverse withstand voltage of the power diode based on the n-Si substrate / ''(n-Si)-(ZIF-8) composite layer'' / Ag layer composite structure exceeds 200V, the forward conduction voltage of the power diode is 0.25-1.5 V, the reverse bias voltage applied to the power diode is 0-200V, the reverse leakage current is basically not increased along with the increase of the reverse bias voltage, and the reverse leakage current is 0.2-2.1 mA (at the reverse voltage-100V). Compared with a conventional power diode based on an n-Si substrate / Ag layer Schottky structure, the performance of the power diode provided by the invention has the advantages that although the forward voltage is basically unchanged, the reverse voltage is increased by 80-400%, the reverse saturation current is reduced by 50-800%, and the highest yield reaches 95%.

In a signal processing circuit, an input terminal is configured to receive an analog signal output from an avalanche photodiode operating in Geiger mode. A comparison circuit outputs a signal based on a component exceeding a threshold among components a signal input to the comparison circuit. The adjustment circuit includes an AC coupling unit, a level shifter unit, and a reference value adjustment unit. The AC coupling unit establishes AC coupling between the input terminal and the comparison circuit. The level shifter unit adjusts the voltage of the signal input to the comparison circuit to a value lower than a reverse bias voltage applied to the avalanche photodiode. The reference value adjustment unit adjusts the reference value of the signal input to the comparison circuit.

A dual-mode asymmetric P-I-N perovskite radiation detector and its fabrication method are disclosed, belonging to the field of radiation detector technology. The method first involves preparing a perovskite single-crystal precursor solution. A small amount of this solution is used for seed crystal growth at a constant temperature, with the seed crystal serving as the seed for CsPbBr3 single-crystal growth on a P-type substrate. Next, a MAPbBr3 solution is prepared, and MAPbBr3 single crystals are grown to form the I layer. Finally, MAPbBr3 (Bi) is prepared... 3+ A doped solution was used to grow MAPbBr3 (Bi) as the N-layer. 3+ A dual-mode asymmetric P-I-N perovskite radiation detector is obtained by fabricating top and bottom electrodes using a doped single crystal. This invention utilizes the forward conduction and reverse cutoff characteristics of the P-I-N structure. When a negative voltage is applied to the N layer for forward bias, X-rays incident on the P layer are used for radiation detection, exciting the photoconductivity gain and achieving a sensitivity far exceeding that of CsPbBr3 single crystals; simultaneously, MAPbBr3 (Bi 3+ The doped single crystal has a natural shielding effect on soft X-rays, enabling high-sensitivity detection of hard X-rays in the I layer when X-rays are incident on the N layer with positive pressure and reverse P-I-N bias.

Disclosed is a system and method for solid-state 2D optical phased arrays (OPAs), which are fabricated from InGaN / AlGaN multiple quantum wells (MQWs) and AlyGa1-yN / AlxGa1-xN (y<x) MQWs. The InGaN / AlGaN MQWs and AlyGa1-yN / AlxGa1-xN (y<x) MQWs include alternating p-type and n-type layers to form p-n-p-n MQW structures to allow the OPA to operate in the reversed biased configuration to further minimize the operating current and heat generation. The phase in each pixel within the OPA will be controlled independently via electro-optic effect in III-nitride MQWs by varying the voltage in each pixel by a Si CMOS array to achieve the manipulation of the distribution of optical power in the far field and steering of the main laser beam. The present disclosure is applicable to a wide range of applications, including the operation of LIDAR systems, laser weapons, laser illuminators, and laser imaging systems.

This disclosure provides an electro-optic modulator, including a modulator body and an equalization circuit. The equalization circuit includes: a first doped semiconductor, including a first N-type doped region and a first P-type doped region, the first N-type doped region being connected to a first electrode and a signal input terminal, the first P-type doped region being connected to a second electrode and an electrode arm, the first electrode and the second electrode being used to receive a first control voltage with reverse bias; and a second doped semiconductor, including a second N-type doped region and a second P-type doped region, the first end of the second N-type doped region and the first end of the second P-type doped region being both connected to the signal input terminal, the second end of the second N-type doped region and the second end of the second P-type doped region being both connected to the electrode arm, the first end of the second P-type doped region being further connected to a third electrode, the second end of the second N-type doped region being further connected to a fourth electrode, the third electrode and the fourth electrode being used to receive a second control voltage.

The present invention relates to a control system (20) and method for controlling the flow of current between a voltage source (22) and a multiphase motor or other application / load for controlling a multiphase motor (28). The control system includes, between each phase of the multiphase motor and the voltage source: a high-side diode (30A-C) and a high-side switch (34A-C) positioned in parallel between a positive terminal of the voltage source and the motor, wherein the high-side diode is reverse biased with respect to the positive terminal; and a low-side diode (32A-C) and a low-side switch (36A-C) positioned in parallel between a negative terminal of the voltage source and the motor, wherein the low-side diode is reverse biased with respect to the motor. The control system operates the high-side and low-side switches to provide efficient operation of the motor.

A manufacturing method of an electronic device is provided. The manufacturing method of the electronic device includes the following steps: providing a substrate; bonding an electronic component on the substrate, wherein the electronic component is mainly driven by a reverse bias in an operating mode; applying a forward bias to the electronic component, and determining whether the electronic component is normal or damaged; and transporting the substrate provided with the electronic component determined as normal to a next production station, or repairing the electronic component determined as damaged. Therefore, the manufacturing method of the electronic device of the present disclosure can effectively test whether the electronic component formed in the electronic device is normal or damaged during the manufacturing process.

A varactor-tunable radio frequency (RF) resonant circuit is disclosed. The circuit includes a planar impedance-controlled transmission line disposed on a dielectric substrate, and a voltage-controlled varactor diode, or an arrangement of parallel varactor diodes, electrically connecting a resonator of the planar transmission line to a reference node. The resonator can have a stepped impedance. A frequency of the resonator is tunable by configuration of a reverse bias voltage applied to the first plurality of voltage-controlled varactor diodes.

The invention relates to the field of photovoltaic technology, in particular to a back contact solar cell and a photovoltaic module. The back contact solar cell comprises a substrate, first areas and second areas which are alternately arranged at intervals in the X direction are formed on the backlight face of the substrate, gaps between the adjacent first areas and second areas form third areas, a first doping layer is formed in each first area, a second doping layer is formed in each second area, and a second doping layer is formed in each second area. A third doping layer is formed in each third region; the doping concentration of the third doping layer is greater than the doping concentration of the first doping layer and the doping concentration of the second doping layer; the third doped layer is electrically connected with the adjacent first doped layer and the adjacent second doped layer. Compared with the prior art, the arrangement of the third doping layer is beneficial to generating leakage current under relatively low reverse bias voltage, so that the hot spot temperature of the assembly is remarkably reduced, the reliability of a single battery and the assembly is improved, and the phenomenon of abnormal concentration of reverse leakage current can be avoided.

The present application relates to the technical fields of dynamic reverse bias test, and relates to a circuit and a method for detecting dynamic leakage current in dynamic reverse bias of silicon carbide power devices, the circuit comprises a circuit for detecting dynamic leakage current in dynamic reverse bias of silicon carbide power devices, including a gate resistor, a half-bridge topology circuit, a Schottky barrier diode, a differential amplifier and a direct current power supply, the half-bridge topology circuit comprises an upper bridge auxiliary measurement silicon carbide power device, a lower bridge measured sample and a lower bridge sampling resistor, the gate of the auxiliary measurement silicon carbide power device and the gate of the measured sample are respectively connected with a gate drive input signal through the gate resistor; a plurality of Schottky barrier diodes are connected in parallel with the lower bridge sampling resistor to form an active low-pass filter, the non-inverting input and the inverting input of the differential amplifier are respectively connected with the anode and the cathode of the Schottky barrier diode; the present application can effectively filter out current spikes, solve the problem of related high dV / dt current spikes, and ensure the high precision of the leakage current monitoring signal.

The invention relates to the technical field of motion detection, and discloses a primary motion detector based on a PN junction channel, a preparation method and a sensor, the primary motion detector comprises a first photoelectric transistor and a second photoelectric transistor; the first phototransistor is configured to work under source-drain positive bias voltage, and the attenuation process of light current during turn-off has a first fast attenuation time constant and a first slow attenuation time constant; the second phototransistor is configured to work under the source-drain reverse bias voltage, the photocurrent of the second phototransistor when the second phototransistor is turned off has a second fast decay time constant and a second slow decay time constant, and the first fast decay time constant is larger than the second fast decay time constant; a directional current pulse can be detected at the output of the primary motion detector when the light pulse moves in the direction from the first phototransistor to the second phototransistor. According to the invention, high-efficiency and low-power-consumption discrimination of the optical signal direction is realized.

Method for detecting a single permanently conductive defective semiconductor switch of the semiconductor switches (210, 340) of a semi-controlled H-bridge (100) for setting an excitation current of a separately excited synchronous machine, wherein the semi-controlled H-bridge (100) a bridge branch (200) with one of the semiconductor switches T1 (210) and a diode D3 (230) connected in series in reverse bias and a further bridge branch (300) comprising a further diode D2 (320) in reverse bias in series with a further semiconductor switch T4 (340) and a load branch (400) comprising an excitation winding (460) of the separately excited synchronous machine, wherein the load branch (400) connects a connection point (250) from one of the semiconductor switches T1 (210) and the diode D3 (230) in the first bridge branch (200) and with a further connection point (350) between the further diode D2 (320) and the further semiconductor switch T4 (340) in the further bridge branch (300), and wherein a current measuring device (480) for measuring the current excitation current is arranged in the load branch (400); wherein the semi-controlled H-bridge (100) is coupled to a control device (1200) comprising an excitation current control (1220) which generates two pulse-width modulated control signals (611, 621) of the same frequency, phase-shifted by half a period, for controlling one of the semiconductor switches T1 (210) and the other of the semiconductor switches T4 (340), such that the excitation current flowing through the load branch (400) can be controlled via the pulse-width modulation of the control signals (611, 621) according to a requirement, wherein a duty cycle in normal operation is limited to a range of 50% to 100%, wherein the duty cycle is a ratio of the temporal pulse width of a signal level (612, 622), which puts the correspondingly controlled semiconductor switch (210, 340) into a conducting state, to the period of the control signal (611, 621) and wherein the load branch (400) comprises a current measuring device (480) to measure the excitation current,which is used as a feedback signal by the excitation current control (1220), , the procedure includes the following steps: Detection of the excitation current and a target excitation current, Comparing the target excitation current according to the requirement with the excitation current measured and recorded by the current measuring device to determine a control deviation and Comparing the control deviation with a control deviation threshold and outputting an error signal if the control deviation exceeds the control deviation threshold. where a supply voltage U DC is detected, which is located at the semi-controlled H-bridge (100), and for this supply voltage U DC a standard duty cycle for a The target excitation current value is determined corresponding to the currently recorded measured excitation current value for a minimum possible load branch resistance value of the load branch (400), and an error signal is output if the currently set duty cycle is smaller than the determined standard duty cycle. or for the excitation current value measured at the currently set duty cycle and the A standard duty cycle range (1080) is determined from the measured supply voltage, which includes duty cycles that correspond to the currently measured excitation current value for various possible load branch resistances, and it is checked whether the currently set duty cycle is within the standard duty cycle range (1080), and a short-circuited semiconductor switch is detected if the currently set duty cycle is not within the determined standard duty cycle range (1080).

Complementary metal-oxide-semiconductor (CMOS) image sensor, comprising: i) a bias junction consisting of a first semiconductor material type and electrically coupled to a voltage source to apply a reverse bias of opposite polarity to a polarity of the first semiconductor material type to the bias junction; ii) a pixel in a pixel array, comprising: a photosensitive element, a first well consisting of a second semiconductor material type, and a second well consisting of the first semiconductor material type, and active CMOS elements used for at least one of 1) reading and 2) resetting the image data acquired by the photosensitive element; and iii) an implanted, buried layer consisting of the second semiconductor material type, extending over a region representing the pixel array below the second well consisting of the first semiconductor material type;wherein the implanted, buried layer, which consists of the second semiconductor material type, is arranged to interact with the blocking bias applied by the voltage source to the bias junction to reduce a parasitic current path between the second well, which consists of the first semiconductor material type and is used by the active CMOS elements, and a substrate, resulting in more uniform pixel-to-pixel performance in an image sensor with two or more pixels.

The application belongs to the technical field of semiconductor optoelectronic devices, and particularly relates to a light computing array based on a reverse bias germanium modulator, which comprises a cross matrix formed by multiple rows of parallel input light waveguides and multiple columns of parallel output light waveguides; an optical detector is arranged at the output end of each column of the output light waveguides; multiple light splitters; multiple germanium modulators, each corresponding to one cross waveguide, and the first input end of the germanium modulator being connected with the output end of the light splitter through a transmission light waveguide; and multiple light combiners, each being connected with the output end of the germanium modulator and the output light waveguide. Through the above structure, the application comprehensively provides a high-response computing array with a thermal compensation mechanism and capable of reducing light reflection, so as to realize a scheme of a large-scale integrated computing array with low power consumption under the condition of meeting frequent switching.

The application discloses a kind of shielded gate trench MOSFET cell structure and its manufacturing method, shielded gate trench MOSFET cell structure includes substrate, drift region and interlayer dielectric layer, the drift region is provided with deep groove, the deep groove is provided with shielded gate, intermediate oxide layer and control gate;The upper portion of the drift region is formed with body region and source region by injection, the interlayer dielectric is provided with source contact hole that is through source region and extends into body region, the sidewall and bottom of the source contact hole are formed with high-doped contact region by injection;The lower of the source contact hole is formed with charge balance region by high-energy ion injection.In the application, by setting charge balance region, the lateral depletion of adjacent drift region by shielded gate can be enhanced when shielded gate trench MOSFET device is in reverse bias state, the specific on-resistance of the device is reduced, the epitaxial layer drift region is accelerated, and the reliability and radiation resistance of the device are improved.

The invention discloses an ultrahigh-voltage isolating ring structure. The structure includes a laterally diffused metal oxide semiconductor structure and a floating metal field plate formed on a semiconductor substrate. The laterally diffused metal oxide semiconductor structure includes a drift region. The floating metal field plate is formed on the dielectric layer above the drift region and is electrically isolated from the drift region through the dielectric layer. By arranging the floating metal field plate, electric field distribution on the surface of the drift region can be homogenized by utilizing a capacitance coupling effect, and electric field concentration caused by charge accumulation under high-temperature reverse bias stress is inhibited, so that the long-term working reliability and the service life of the ultrahigh-voltage isolating ring structure are remarkably improved; and meanwhile, the original breakdown voltage performance is not influenced.

The invention provides a method for defect detection of a power semiconductor device, which belongs to the technical field of defect detection of semiconductor devices and comprises the following steps: preparing a cathode electrode on the back surface of a semiconductor layer test substrate; preparing an anode electrode on the front surface of the semiconductor layer test substrate, wherein the anode electrode comprises a transparent electrode and a metal frame; the metal frame surrounds and contacts the edge area of the transparent electrode; applying a reverse bias voltage between the cathode electrode and the transparent electrode; collecting an electroluminescent signal generated by the semiconductor layer test substrate under the reverse bias voltage through a low-light microscope located above the transparent electrode; the transparent electrode is configured to allow an electroluminescent signal to penetrate upwards; and determining the defect position of the semiconductor layer test substrate according to the electroluminescent signal. According to the method, non-destructive failure analysis can be carried out on the vertical structure device by utilizing the EMMI technology.

The invention discloses a BC battery contact resistance measuring method based on a selective transmission line model (TLM), which comprises the following steps of: selecting n grid lines, numbering the grid lines in sequence from left to right, enabling the grid lines with odd numbers to be P-type, and enabling the grid lines with even numbers to be N-type; when the contact resistance of the P-type grid lines of the BC battery is measured, a P-N measuring method is adopted for measuring the P-type grid lines and the N-type grid lines at different intervals, and when the contact resistance of the N-type grid lines of the BC battery is measured, an N-N measuring method is adopted for measuring the N-type grid lines at different intervals. According to the invention, a reasonable measurement path is selected according to the doping type of the grid line, errors caused by reverse bias of PN junctions are avoided, and accurate and stable measurement of the contact resistance is realized.

The invention provides a micro current and voltage measuring device, which belongs to the field of semiconductor devices, and comprises a collector region, a base region, a central emitter region, a protection ring surrounding the central emitter region, a high-resistance region positioned between the central emitter region and the protection ring, and a quenching resistor, the central emitter region and the collector region can be made of silicon materials, and the base region can be made of germanium-silicon materials; the central emitter region and the base region form an emitter junction, the protection ring and the base region form a protection ring junction, and the collector region and the base region form a collector junction; the center emitter region and the protection ring are heavily doped in the same type, the high-resistance region is a lightly doped region in the same type as the center emitter region, or the high-resistance region is a heavily doped region in the same type as the center emitter region, and the thickness is relatively thin; when the device works, the emitter junction is positively biased, the protection ring junction is reversely biased, and the base region under the protection ring is partially or completely exhausted; the collector junction is reverse biased, and the collector junction operating voltage is greater than its avalanche breakdown voltage. Compared with an existing device, the device can accurately measure smaller electric signals.

This disclosure relates generally to metasurface beam steering antenna and method of setting antenna beam angle. Conventional approaches perform electronically beam steering using phase array which requires bandwidth with higher data rates. The present disclosure enables metasurface antennas tilt antenna beam in a given direction, where the varactor diodes are operated in reverse bias so that different values of capacitors combination lead to electronic beam scanning. The processor of the metasurface beam steering antenna receives a command having an input angle to tilt the angle beam position. The processor processes the command by mapping the input angle with the set of c-shaped copper patch combination having the capacitor values using a predefined lookup table for setting the antenna beam angle based on a reference voltage generated by the varactor diode. The lookup table is iteratively updated with the capacitor values of the c-shaped copper patches.

The invention relates to a high-temperature reverse bias test method and a cooling method, and relates to the technical field of semiconductors. The high-temperature reverse bias test method comprises the following steps: firstly, heating a to-be-tested module to a preset temperature T, keeping the temperature for a preset time, enabling the junction temperature Tj to be the same as the shell temperature Tc, applying a preset pulse voltage to the to-be-tested module, and collecting leakage current IR data at different temperatures T; performing linear fitting on the obtained leakage current IR and temperature T data to obtain a function relationship between ln (IR) and 1 / T; heating the to-be-tested module to a temperature close to a target test temperature, applying a test voltage VR to the to-be-tested module, collecting leakage current IR data and a reference point temperature Tref, and after the leakage current IR is stable, calculating a junction temperature Tj according to the fitting curve so as to obtain a thermal resistance value Rth of the system; and finally starting the test, and adjusting the temperature of the to-be-tested module by using the temperature control device, so that the junction temperature Tj of the to-be-tested module reaches the highest junction temperature and is kept constant. Thermal resistance calibration is carried out based on a temperature-sensitive electrical parameter method, the problem of thermal resistance calibration is solved, and accurate measurement of junction temperature is realized.

This invention discloses a gallium nitride Schottky diode with a quasi-depletion layer, the structure of which, from bottom to top, comprises: a substrate layer, a buffer layer, and an N-type diode. + -GaN contact layer, N ‑ -GaN drift layer, quasi-depletion layer, and anode Schottky contact layer disposed on the quasi-depletion layer and disposed on N + A cathode ohmic contact layer above a GaN contact layer; wherein the doping concentration and thickness of the quasi-depletion layer must satisfy the following: the thickness of the quasi-depletion layer is less than the width of the depletion layer of the diode at zero bias voltage. This invention significantly reduces the turn-on voltage of the diode by setting a highly doped quasi-depletion layer on the surface of the drift layer. With the combination of doping concentration and quasi-depletion layer thickness, the quasi-depletion layer is in a fully depleted state under zero bias voltage, while under reverse bias voltage, based on the characteristic that the quasi-depletion layer is already depleted at zero bias voltage, the reverse voltage is mainly due to the N-type cathode ohmic contact layer below. ‑ The GaN drift layer effectively reduces reverse leakage current.

The application belongs to the technical field of random number generation, and particularly relates to a random signal generation device based on a saturable absorber semiconductor laser. The device comprises a random self-pulsation entropy source, a photodetector and a pulse amplitude quantization module. The random self-pulsation entropy source adopts a saturable absorber semiconductor laser (preferably a DFB-SA structure), generates optical pulses with random amplitudes and stable repetition periods by injecting a driving current in a gain region and applying a reverse bias voltage in an absorption region; the photodetector adopts a PIN photodiode or an avalanche photodiode to convert the optical pulses into corresponding electrical pulses; and the pulse amplitude quantization module comprises a differential comparator and a peak detection circuit, which quantizes the peak value of the electrical pulses in each pulse period by using a fixed threshold or an adaptive threshold to generate a random bit sequence. The application realizes high-speed and high-stability random signal generation without an external electric clock, an ADC and digital post-processing, and has a simple device structure, low power consumption and high integration.

A light emitting display device includes a display panel including pixels, each pixel including a light emitting diode, a driving transistor, and a first capacitor connected between a source electrode and a gate electrode of the driving transistor; a timing control section including a stress calculation section configured to calculate stress data representing an amount of stress accumulated in the driving transistor of the pixel using input image data in display driving, and a recovery data generation section configured to generate recovery data corresponding to the calculated stress data in recovery driving; and a data driving section configured to output a recovery voltage corresponding to the recovery data to a data line, wherein the recovery voltage is configured to be applied to the driving transistor of the pixel so that a gate-source voltage of the driving transistor is in a reverse bias state.

This invention provides a trench-type gallium oxide radiation detector and its manufacturing method, belonging to the field of semiconductor device technology. The detector, by designing a rectangular trench structure on the Ga2O3 epitaxial layer of an epitaxial wafer, achieves a more uniform electric field distribution under high reverse bias, effectively avoiding the electric field accumulation effect at the electrode edges and significantly improving the device's breakdown voltage. Simultaneously, the trench structure increases the effective area of ​​the heterojunction, enabling the device to obtain a wider longitudinal depletion region under the same reverse bias, making it easier to achieve full-energy alpha particle deposition, thereby improving the efficiency and energy resolution of radiation detection.