693 results about "Reverse bias" patented technology

The invention discloses a silicon carbide TrenchMOS device and a manufacturing method thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the arc-shaped lightly-doped N layer is additionally arranged in the middle of the arc-shaped heavily-doped N layer, electric field distribution under reverse bias is smoothed through the doping concentration lower than that of the heavily-doped N layer, the interface electric field sudden change risk is reduced, dynamic loss is reduced, meanwhile, the doping concentration of the central area is diluted through the arc-shaped inner side lightly-doped N layer, a depletion area is promoted to be expanded, and the performance of the device is improved. Electric field distribution between drain gates is optimized, and stray capacitance is reduced to improve high-frequency performance.

The invention relates to the technical field of photovoltaic cells, and discloses a method for improving laser-assisted sintering contact uniformity and a processing device. The method comprises the steps that a probe presses a main grid of a first area on the front face of a battery piece, first laser power is used for scanning a second area on the front face of the battery piece in a laser scanning mode in the fine grid direction, first reverse bias voltage is applied to the battery piece, and a variable resistor adjusts the resistance value of the variable resistor according to the distance between scanning point positions and the probe so as to balance the bias voltage difference of different scanning point positions; performing laser-assisted sintering on the second area; the probe presses a main grid of a second area on the front face of the battery piece, laser scanning is conducted on a first area on the front face of the battery piece in the fine grid direction through second laser power, second reverse bias voltage is applied to the battery piece, the resistance value of the variable resistance piece is adjusted according to the distance between the scanning point position and the probe, and laser-assisted sintering of the first area is completed. According to the method, the bias voltage difference of different scanning point positions can be balanced, the interface contact difference of different areas can be balanced, and the battery performance and effect can be improved.

The invention relates to the technical field of semiconductor power device testing, in particular to a dynamic reverse bias testing method and system for a semiconductor power device, which can accurately evaluate the performance of the device under a dynamic reverse bias condition and improve the testing efficiency and accuracy. The method comprises the following steps: acquiring a plurality of electrical characteristic data of a to-be-detected semiconductor power device to obtain an electrical characteristic data set; inputting the electrical characteristic data set into a dynamic reverse bias test model to obtain a first dynamic reverse bias test result; transmitting a fast changing backward voltage pulse signal to the to-be-detected semiconductor power device to obtain an output signal after the backward voltage pulse signal passes through the to-be-detected semiconductor power device; judging whether the output signal exceeds a preset abnormal threshold value or not; if not, outputting the first dynamic reverse bias test result as a dynamic reverse bias test result of the semiconductor power device; and if yes, extracting the obtained abnormal output signal, and inputting the abnormal output signal into the dynamic reverse bias failure analysis model.

The invention discloses a cellular structure of a shield gate trench MOSFET and a manufacturing method thereof, the cellular structure of the shield gate trench MOSFET comprises a substrate, a drift region and an interlayer dielectric layer, the drift region is provided with a deep trench, and the deep trench is internally provided with a shield gate, an intermediate oxide layer and a control gate; a body region and a source region are formed at the upper part of the drift region through injection, the interlayer dielectric is provided with a source electrode contact hole which penetrates through the source region and extends into the body region, and highly doped contact regions are formed on the side wall and the bottom of the source electrode contact hole through injection; and a charge balance region is formed below the source electrode contact hole through high-energy ion implantation. According to the invention, by arranging the charge balance region, the lateral depletion of the shield gate to the adjacent drift region can be enhanced when the shield gate trench MOSFET device is in a reverse bias state, the specific on-resistance of the device is reduced, the depletion of the drift region of the epitaxial layer is accelerated, and the reliability and radiation resistance of the device are improved.

The invention belongs to the technical field of display driving, and particularly relates to a noise reduction circuit and a gate driving circuit, and the noise reduction circuit comprises a first noise reduction module which is used for carrying out the noise reduction processing of the voltage of a driving control node, a driving output end and a stage transmission output end; the first noise reduction module is also used for enabling a noise reduction transistor in the first noise reduction module to be in a reverse bias state under the action of a second noise reduction control signal; the second noise reduction module is used for carrying out noise reduction processing on voltage on the driving control node, the driving output end and the stage transmission output end; the second noise reduction module is also used for enabling a noise reduction transistor in the second noise reduction module to be in a reverse bias state under the action of the first noise reduction control signal; according to the noise reduction circuit, the noise reduction transistors in the two groups of noise reduction modules are in the reverse bias state when not working, so that the forward bias state of the noise reduction transistors in alternate working is counteracted, the problem that the threshold voltage of the noise reduction transistors drifts is solved, and the noise reduction stability of the noise reduction circuit is improved.

The embodiment of the invention provides a preparation method of a solar cell and the solar cell, and the method comprises the steps: firstly obtaining a substrate cell piece, forming a passive film layer on the substrate cell piece, then forming a grid line on the passive film layer, and then carrying out the sintering. When the grid line is subjected to laser scanning, reverse bias voltage is applied to the grid line, meanwhile, laser scanning is carried out from the middle area of the passive film layer to the edge area, and the laser power when laser scanning is carried out on the middle area is larger than the laser power when laser scanning is carried out on the edge area. When a passive film is formed, due to the influence of a winding plating phenomenon, the passive film has the characteristics that the middle is thin and the edge is thick. The laser power of the edge area is lower, so that the process strength of the edge area can be reduced, and the temperature generated by the edge area can be reduced. Compared with the prior art, the method has the advantages that the high-temperature phenomenon of the edge area can be relieved, the abnormal black edge phenomenon caused by high process strength at the edge is effectively reduced, and the product yield and quality are improved.

Polymers synthesized by solid-phase synthesis are selectively released from a solid support by reversing the bias of spatially addressable electrodes. Change in the current and voltage direction at one or more of the spatially addressable electrodes changes the ionic environment which triggers cleavage of linkers that leads to release of the attached polymers. The spatially addressable electrodes may be implemented as CMOS inverters embedded in an integrated circuit (IC). The IC may contain an array of many thousands of spatially addressable electrodes. Control circuity may independently reverse the bias on any of the individual electrodes in the array. This provides fine-grained control of which polymers are released from the solid support. Examples of polymers that may be synthesized on this type of array include oligonucleotides and peptides.

The invention discloses a preparation method of a solar cell, which belongs to the technical field of solar cells and comprises the following steps of: selecting an N-type silicon substrate and performing double-sided texturing; performing boron diffusion doping on the front surface of the silicon substrate to form a P + doping layer and a borosilicate glass layer on the front surface, and forming a borosilicate glass layer on the back surface; removing the borosilicate glass layer on the back surface of the N-type silicon substrate, and carrying out alkali washing and polishing on the back surface of the N-type silicon substrate; forming a polycrystalline silicon layer and a polycrystalline silicon layer on the back and the front of the substrate; performing phosphorus diffusion on the polycrystalline silicon layer on the substrate; removing the phosphorosilicate glass layer on the front side, the borosilicate glass layer, the N + polycrystalline silicon layer and the borosilicate glass layer and the phosphorosilicate glass layer on the back side; depositing a front passivation layer and a front antireflection layer on the P + doping layer on the front of the substrate; electrode printing sintering is carried out on the front and back of the substrate; the reverse bias voltage applied by the first LECO process is 3-10V, and the reverse bias voltage applied by the second LECO process is 11-20V. And the black edge problem caused by overburning is reduced by increasing the LECO for the second time.

The invention discloses a path planning method and device based on a photon pulse reinforcement learning network, and relates to the field of photon pulse reinforcement learning networks, and the method comprises the steps: adjusting the phase of each phase shifter in an explicit MZI network according to a multi-level pulse neural network, and configuring a weight matrix; carrying out pulse signal loading on the light source by using a light modulator to obtain an input signal; obtaining a plurality of linear calculation results by using the weight matrix and the input signal through an interference effect and a coupling effect; inputting the plurality of linear calculation results into the DFB-SA laser, and obtaining a nonlinear activation result by adjusting the injection current of a gain region of the laser and the reverse bias voltage of a saturation region of the laser; and taking the nonlinear activation result as a new input signal, and returning to the step of obtaining a plurality of linear calculation results by using the weight matrix and the input signal until calculation of all levels in the pulse neural network is completed, so that path planning which is high in speed, low in power consumption and easy to configure is realized.

The invention discloses a microstructure silicon carbide ultraviolet photoelectric detector with high quantum efficiency and a preparation method thereof, and belongs to the technical field of ultraviolet photoelectric detection. The detector adopts a bottom-to-top structural design and comprises a silicon carbide highly-doped n + type substrate, an n type buffer layer, a low-doped n-type absorption layer, a low-doped p-type absorption layer (containing a microstructure), an annular highly-doped p + type ohmic contact layer and a passivation isolation layer. Reverse bias voltage is applied to the p + type ohmic contact electrode to form a depletion electric field, and the microstructure promotes the p-i-n structure electric fields to be mutually connected and coupled, so that the photon-generated carrier depletion efficiency is improved, and the responsivity of the device and the external quantum efficiency are enhanced. And meanwhile, the microstructure enables a short-wave ultraviolet signal to directly penetrate through the p-type absorption layer to enter the internal absorption layer, so that photon-generated carrier recombination caused by surface defects of the p + type ohmic contact layer is avoided, the collection efficiency of photon-generated carriers is improved, and ultraviolet full-band detection is realized.

Unidirectional hybrid switch. At least one example is a method operating a hybrid switch, the method comprising: sensing a voltage across an upper terminal and a lower terminal of the hybrid switch, the hybrid switch is forward biased when the upper terminal has higher voltage, and the hybrid switch is reverse biased when the lower terminal has higher voltage; when the hybrid switch is forward biased, selectively conducting a forward current from the upper terminal to the lower terminal by sharing the forward current between a FET switch and a BJT switch, the selectively conducting when a control terminal is asserted; and when the hybrid switch is reversed biased, non-selectively conducting a reverse current from the lower terminal to the upper terminal.

The invention provides a reliability test system and method, and relates to the field of power devices, the reliability test system can carry out a high-temperature gate bias test and a high-temperature reverse bias test, multiple test modes are realized in one reliability test system, and the test efficiency is improved. Moreover, the reliability test system can apply an alternating signal to the to-be-tested device, thereby truly restoring an actual application scene, and enabling the reliability test system provided by the invention to accurately test the reliability of the power device. After the stress is applied, detection can be carried out immediately, and the relaxation effect of the power device is prevented from influencing the test result. Besides, in the high-temperature gate offset test, the pulse frequency or duty ratio of the electric stress pulse signal can be controlled through the half-bridge circuit, the parameters of the pulse signal can be flexibly changed by the reliability test system for different power devices, and the test applicability is improved.

A photodetection device according to one embodiment of the present disclosure includes: a semiconductor substrate having a first surface and a second surface that are opposed to each other and including a plurality of pixels arranged in an array in an in-plane direction; a first trench extending between the first surface and the second surface in an approximate middle of each of the plurality of pixels; a first semiconductor layer of a first conductivity type, the first semiconductor layer being provided in each of the plurality of pixels and extending between the first surface and the second surface; and a second semiconductor layer of a second conductivity type that is opposite to the first conductivity type, the second semiconductor layer being provided in each of the plurality of pixels and extending between the first surface and the second surface. When a reverse bias voltage is applied, a high electric field region is formed between the first semiconductor layer and the second semiconductor layer throughout between the first surface and the second surface.

The invention discloses a dynamic reverse bias test method and system for a power semiconductor device, and relates to the technical field of power semiconductor device testing, and the method comprises the steps: obtaining a test parameter of a tested device, and carrying out the test circuit configuration based on the test parameter of the tested device; performing a dynamic reverse bias test based on the configured test circuit to obtain a test result; and analyzing and evaluating a test result. According to the method, the accuracy and reliability of a test result are improved, a solid foundation is provided for a subsequent dynamic reverse bias test, potential problems of the device can be found in time, it is ensured that the test result has an actual reference value, real-time data support is provided for subsequent evaluation and analysis, the performance state of the device can be accurately judged, and the reliability of the device is improved. The safety of the test process is ensured, the integrity and sufficiency of the test are ensured, and misjudgment caused by insufficient test is avoided.

The invention discloses a band-pass type active frequency selective surface based on double-element composite loading. The band-pass type active frequency selective surface comprises at least one resonance unit which is periodically arranged, the resonance unit sequentially comprises a top metal frequency selection surface layer, a first dielectric structure layer, a middle metal feed layer, a second dielectric structure layer and a bottom metal frequency selection surface layer from top to bottom; the top metal layer and the bottom metal layer are composed of square ring aperture grooves subjected to deformation processing, and the middle feed layer is of a cross zigzag metal structure, plays a role in coupling an electromagnetic field and serves as a bias network of the AFSS. And the metal through holes penetrate through the resonance units in the vertical direction, so that the middle layer feeder line can respectively provide reverse bias voltage for independently regulating and controlling the resonance frequency for the PINs and the variable capacitance diodes on the top layer and the bottom layer. According to the invention, the functions of band switching and wide-range frequency tuning can be met, so that the problem of insertion loss increase caused by limited design frequency regulation and control range and element loading of the AFSS in the prior art can be solved.

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and aims to solve a reverse bias problem and / or a dynamic resistance problem caused by a bulk electron trap or an interface state trap. The semiconductor device includes a substrate, an epitaxial layer, a barrier layer, a gate, a cap layer, a source, a drain, and a functional layer. An epitaxial layer and a barrier layer are stacked on the substrate, and the barrier layer is farther from the substrate than the epitaxial layer. The grid electrode is located on the side, away from the substrate, of the barrier layer. The cap layer is located between the barrier layer and the gate. The source electrode and the drain electrode are located on the side, away from the substrate, of the barrier layer and located on the two opposite sides of the grid electrode respectively. And the functional layer is positioned on one side, far away from the substrate, of the barrier layer. The functional layer and the drain electrode are located on the same side of the grid electrode, and the functional layer is connected with the drain electrode. And the thickness of the functional layer is smaller than that of the cap layer.

A power control device for providing variable power to a load. The power control device including a single FET employed in conjunction with a bridge rectifier to reverse bias the body diode of the FET except for when a sufficient voltage is provided to the gate of the FET. A temperature compensation circuit reduces the on-time of the bridge rectifier when a thermally sensitive component indicates that the temperature of the bridge rectifier has exceeded a threshold.

The present disclosure provides an optical module, comprising a light source comprising a laser assembly. The laser assembly comprises a semiconductor gain chip and a wavelength tuning chip which form a resonant cavity; the wavelength tuning chip comprises at least one micro-ring filter; the at least one micro-ring filter is used for screening for a beam of a specific wavelength from among beams emitted by the semiconductor gain chip; the micro-ring filter comprises a first slab region and a second slab region which are located on two sides of a silicon waveguide ridge region, and a contact electrode; an N-type doped region is provided in the first slab region, and a P-type doped region is provided in the second slab region; the P-type doped region and the N-type doped region form a PN junction electrically connected to the contact electrode; and electron-hole pairs in the silicon waveguide ridge region and the first and second slab regions can be absorbed by applying a reverse bias to the PN junction.

A reconfigurable metasurface sub reflector comprises an array of cell units. Each sub unit is formed of two sub-unit cells formed with at least two conducting layers separated by a dielectric substrate. One conducting layer has, in each of the sub-unit cells, two parallel strips connected by a varactor and the other conducting layer serves as a ground layer. Setting the reverse biasing for each of the varactors controls the azimuth and elevation of reflection from the reconfigurable metasurface sub reflector.

The invention discloses a gallium oxide solar-blind ultraviolet detector based on selective area etching and a preparation method thereof, and belongs to the technical field of semiconductor photoelectric detection. Comprises from bottom to top: a substrate; the first epitaxial layer is located on the substrate, and the first epitaxial layer is a highly doped n-Ga2O3 layer; the second epitaxial layer is located on the first epitaxial layer, and the second epitaxial layer is a lightly doped n-Ga2O3 layer; the third epitaxial layer is located on the second epitaxial layer, the third epitaxial layer is a highly-doped p-NiO layer, and the third epitaxial layer is distributed at intervals through selective area etching; and the first ohmic contact layer is located on the area where the third epitaxial layer is distributed at intervals. The detector adopts a PN junction structure working in a reverse bias state, and compared with a Schottky structure, the detector has the advantages that the built-in electric field intensity and the leakage current level of a device are less affected by high-energy photon irradiation and working environment temperature change, and the anti-irradiation performance of the device and the working capability under an extreme temperature condition are effectively improved.

The present application relates to a cell string fabrication method, a cell string, and a photovoltaic module. The cell string fabrication method comprises the following steps: providing a semiconductor substrate; performing metallization on the semiconductor substrate, so as to obtain cells; connecting the cells to a connecting member, so as to obtain a cell string precursor; and performing an illumination treatment on the cell string precursor and simultaneously applying a reverse bias voltage to the cell string precursor. By adding a target photoelectric treatment step, electric current conduction paths can be increased, and the contact between a metal and a semiconductor substrate can be improved, thereby reducing the series resistance of cells, increasing a fill factor of the cells, and improving the photoelectric conversion efficiency.

The invention relates to the technical field of solar cells, and particularly discloses a method for improving conductive contact of a micro-area of an N-type cell, which comprises the following steps of: (1) performing first micro-area conductive treatment on one side of a cell grid line of the N-type cell: scanning a first side edge of the cell grid line through a first pulse laser beam, and applying a first reverse bias voltage to the cell at the same time; and (2) performing second micro-area conductive treatment on the other side of the cell grid line of the N-type cell: scanning a second side edge, opposite to the first side edge, of the cell grid line through a second pulse laser beam, and applying second reverse bias voltage to the cell at the same time. According to the method, the pulse laser beams with more concentrated energy are used for carrying out single-side scanning on the two side edges of the grid line of the battery piece respectively, and precise treatment on the metal electrode on the basis of not damaging the passivation layer of the battery can be realized, so that the contact performance of the battery is optimized, the contact resistance of the battery is greatly reduced, and the performance of the battery piece is improved.

Embodiments of the present disclosure provide a system for fast impedance tuning. The system includes a radio frequency (RF) generator to generate power, a plasma chamber to receive the power from the RF generator and a RF matching network inserted between the RF generator and the plasma chamber configured to match a plasma load impedance to a RF generator impedance using a solid state based variable capacitor. The RF matching network includes a bias circuit that applies a reverse bias to the solid state based variable capacitor to control a capacitance value of the solid state based variable capacitor. The plasma load impedance is matched with the RF generator impedance when pulsed voltage, multi-level pulsing, or RF match ignition tuning is applied.

The invention discloses a tunable laser, a photoelectric conversion module and a communication system, which are used for suppressing the concentration of photon-generated carriers in the tunable laser so as to effectively suppress phase noise. The tunable laser includes a gain module, a first waveguide module, a gain electrode, a first waveguide electrode, and a first heating element. The gain electrode applies current to the gain module, the gain module emits an optical signal according to the current, the first heating element applies first heat to the first waveguide module, and the first waveguide module tunes the wavelength of the optical signal under the action of the first heat, so that the tunable laser emits the optical signal tuned by the first waveguide module. The first waveguide electrode applies a first reverse bias voltage to the first PN junction, and the first reverse bias voltage is used for enabling the first PN junction to be in a reverse cut-off state.

The invention belongs to the technical field of semiconductor testing, and discloses a thermistor performance monitoring method and system based on a power module reliability test. The method comprises the following steps: configuring a pin connection structure electrically connected with a thermistor lead on a test burn-in board for a high-temperature, high-humidity and high-voltage reverse bias test; in the process of executing a high-temperature, high-humidity and high-voltage reverse bias test on the power module comprising the thermistor, a lead of the thermistor is electrically connected with a preset current detection loop through the pin connection structure, so that monitoring current flowing through the thermistor is received by the current detection loop, and thermistor performance monitoring is executed. According to the application, the problem that the self degradation risk of the thermistor cannot be monitored in real time in the H3TRB test process to cause a monitoring blind area can be solved, the whole-process monitoring of the performance fluctuation of the thermistor in the strong electric field and high humidity coupling environment is realized, and the integrity of the reliability evaluation of the power module and the safety of the test system are remarkably improved.

The invention discloses an integrated high-performance LDMOS device and a preparation method thereof, and the method comprises the steps: forming a first polysilicon layer at one side of a second well region, a third well region and an oxide layer, forming a second polysilicon layer at the other side of the oxide layer, and forming resistive field plates which are located between the first polysilicon layer and the second polysilicon layer and are arranged on the oxide layer at intervals, resistive field plates are arranged in the LDMOS device, an equipotential ring is formed between the resistive field plates, the resistive field plates and the equipotential ring are arranged between a gate and a drain of the LDMOS device at intervals, only a thin silicon dioxide film layer is arranged between the surface of a drift region of the device and the resistive field plates at intervals, one side of each resistive field plate is connected with a drain electrode high potential, and a source electrode is connected with a lowest potential. A weak leakage current passing through the resistive field plate exists between the source electrode and the drain electrode, so that the surface electric field distribution between the grid electrode and the drain electrode of the device is more uniform, the peak electric fields near the grid electrode and the drain electrode are greatly weakened, the voltage resistance of the device is improved, and the HTRB reliability of the device is improved.

A method for simulating a photodetector behavior includes: receiving an input waveform for an photodetector; receiving an input optical power and a reverse bias voltage for the photodetector; searching for, in a lookup-table library, model parameters for a photodetector behavior model based on the input optical power and the reverse bias voltage; and outputting a second waveform from the photodetector behavior model, where the second waveform is indicative of an electrical response of the photodetector receiving the input waveform.

The invention provides a leakage current detection circuit and detection equipment, and belongs to the technical field of semiconductor testing, and the leakage current detection circuit comprises a pulse output circuit, a power supply circuit, a detection circuit and a protection circuit. Wherein the output end of the pulse output circuit is used for connecting the control end of a to-be-tested power semiconductor, the first voltage end of the power supply circuit is used for connecting the first controlled end of the to-be-tested power semiconductor, and the second voltage end of the power supply circuit is connected with the first end of the detection circuit; the second end of the detection circuit is used for connecting a second controlled end of the to-be-detected power semiconductor, the first end of the protection circuit is connected with the first end of the detection circuit, and the second end of the protection circuit is connected with the second end of the detection circuit. According to the embodiment of the invention, the protection circuit provides a low-impedance path for the current peak generated by the high-speed switch of the power semiconductor to be tested, so that the dynamic change data of the leakage current can be accurately and completely obtained during the dynamic reverse bias stress test.

The invention discloses an amorphous silicon passivation layer, a preparation method thereof and a heterojunction battery, and relates to the technical field of batteries, the preparation method comprises the following steps: depositing a first passivation layer on a crystalline silicon substrate by using a first reaction gas, the first reaction gas comprising hydrogen and silane, the flow ratio of hydrogen to silane being (1: 10)-(20: 1); a second reaction gas is adopted to deposit a second passivation layer on the first passivation layer, the second reaction gas comprises hydrogen and silane, and the flow ratio of the hydrogen to the silane is larger than 3: 1 and larger than the flow ratio of the hydrogen to the silane in the first reaction gas; in the step S1, reverse bias voltage is applied to the crystalline silicon substrate, so that the surface potential of the crystalline silicon substrate is below 0.5 eV; in the step S2, bias voltage is applied to the crystalline silicon substrate so as to increase the surface potential of the crystalline silicon substrate. According to the crystalline silicon substrate passivation film prepared by the preparation method, the stability, the electrical performance and the heterogeneous interface passivation performance of a material are improved, and the efficiency and the long-term stability of a heterojunction battery are improved.