Multi-use memory cell and memory array

Abstract

A multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein a first resistivity state is used to represent a data state of the memory cell when the memory cell operates as a one-time programmable memory cell but not when the memory cell operates as a rewritable memory cell. A memory array with such memory cells is also disclosed. In another preferred embodiment, a memory cell is provided comprising a switchable resistance material, wherein the memory cell is operable in a first mode in which the memory cell is programmed with a forward bias and a second mode in which the memory cell is programmed with a reverse bias.

Description

RELATED APPLICATIONS [0001] This application is a continuation-in-part of Kumar et al., U.S. application Ser. No. 11 / 237,167, “Memory Cell Comprising Switchable Semiconductor Memory Element with Trimmable Resistance,” filed Sep. 28, 2005 and hereinafter the '167 application, which is assigned to the assignee of the present invention and hereby incorporated by reference in its entirety.[0002] This application is related to Kumar et al., U. S. application Ser. No. xx / xxx,xxx, “Method for Using a Memory Cell Comprising Switchable Semiconductor Memory Element with Trimmable Resistance,” (Attorney Docket No. MA-163-1); to Fasoli et al., U.S. application Ser. No. xx / xxx,xxx, “Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders,” (Attorney Docket No. 023-0048); to Fasoli et al., U. S. application Ser. No. xx / xxx,xxx, “Method for Using a Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders,” (Attorney Docke...

AI Technical Summary

Benefits of technology

[0010] The preferred embodiments will now be described with reference to the attached drawings.

Problems solved by technology

Some solutions for achieving erasable or multi-state cells are complex.

These memory cells are three-terminal devices which are relatively difficult to fabricate and operate at the very small dimensions required for competitiveness in modern integrated circuits.

Chalcogenides are difficult to work with and can present challenges in most semiconductor production facilities.

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