321 results about "Cell memory" patented technology

Systems, methods, and apparatus related to memory devices that perform matrix vector multiplication using memory cells. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. A context of memory cells is determined by a controller (e.g., a memory controller internal or external to a memory chip having the array). The context can include, for example, a physical location of memory cells, weight patterns being programmed, and / or neighboring cell interference, etc. Based on the determined context, the controller dynamically determines adjustments (e.g., adjusted target threshold voltages or currents) for programming the memory cells to store weights prior to performing the matrix vector multiplication.

A memory apparatus and method of operation are provided. The apparatus includes memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory cells are disposed in memory holes grouped in blocks. A control means is configured to determine an amount of the memory cells of one of the blocks that are programmed during at least one read operation. The control means adjusts at least one read parameter based on the amount of the memory cells of the one of the blocks that are programmed. The control means is also configured to utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the plurality of data states in the at least one read operation.

The invention relates to an apparatus and method for notifying a predictor with data object range information in a pointer. A processor of an aspect includes a cache hierarchy and a memory access unit coupled with the cache hierarchy. The memory access unit performs a demand load based on the Y-bit pointer such that the first one or more cache lines are loaded from the memory into the cache hierarchy. The Y-bit pointer has an X-bit virtual address field and a data object range field in one or more of the bits [Y-1: X]. A data object range field stores values. The processor also includes a prefetch unit coupled with the cache hierarchy. The prefetch unit determines whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy based at least in part on the value.

This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

A memory cell, a memory and an access method therefor, and an electronic device. The memory comprises: multiple layers of memory arrays stacked in a direction perpendicular to a substrate, and a plurality of first word lines (WL1) in one-to-one correspondence with the multiple layers of memory arrays. The memory arrays comprise a plurality of memory cells distributed along the arrays, and a plurality of second word lines (WL2) corresponding to rows of the multiple layers of memory arrays. Each memory cell comprises a transistor, the transistor comprising a first gate (G1) and a second gate (G2); the first gates (G1) of memory cells of the same layer are connected to first word lines (WL1) corresponding to the layer, and the second gates (G2) of memory cells in the same row of different layers are connected to second word lines (WL2) corresponding to the row.

In some implementations, a memory system may receive a first indication of one or more memory address ranges to be monitored and a second indication of a memory unit size. The memory system may determine one or more memory units associated with the one or more memory address ranges. The memory system may determine, using an access counter for each memory unit, a quantity of accesses to that memory unit during a monitoring period. The memory system may determine that a corresponding access counter for each memory unit, of a subset of the one or more memory units, satisfies an access threshold. The memory system may add an identifier of, and an indication of the corresponding access counter for, each memory unit, of the subset of the one or more memory units, to a data structure based on determining that the corresponding access counter satisfies the access threshold.

A method includes determining an address associated with a data transform command in a container data structure which is in the data transform accelerator. The data transform accelerator is in communication with a host computing unit. In response to a determination that the address is in the container data structure, the method includes accessing the data transform command based on the address. The data transform command is in the host computing unit. The method includes obtaining metadata based on information in the data transform command. The metadata is in the data transform accelerator or spread out in the host computing unit memory and in the memory of data transform accelerator. The method includes configuring a data transform pipeline based on the metadata. The metadata can be shared in its entirety or partially by multiple data transform commands grouped together.

A 3D in-memory computing accelerator system (100) and method for efficiently inferring a hybrid expert (MoE) neural network model. The system includes a plurality of in-memory computing cores (102), each memory core including a plurality of layers of in-memory computing units (106). One or more layers of the in-memory computing unit correspond to expert sub-models of the MoE model. One or more expert sub-models for activation propagation are selected according to a function-based routing (115) based on which a corresponding expert layer is activated. In one embodiment, the function is a hash-based layer selection function for dynamic routing of input and output activation. In an embodiment, the function is applied to select a single expert or multiple experts for single-level activation using input data based or using MoE based on layer activation. Further, the system is configured as a multi-model system with a single expert model selection or a multi-model system with multiple expert selections.

A communication system includes a target unit provided in a vehicle and including at least one target unit processor and at least one target unit memory coupled to each other; and a communication tool coupled to the target unit for bidirectional communication and including at least one communication tool processor and at least one communication tool memory coupled to each other. The communication tool processor transmits certain information including first certain data and a first padding value to the target unit. The target unit processor determines whether the first padding value matches a preset specific padding value, and transmits abnormality information to the communication tool when the first padding value does not match the specific padding value. Upon receiving the abnormality information, the communication tool processor transmits the certain information including the first certain data and a second padding value different from the first padding value to the target unit.

The invention discloses a numerical comparator which comprises a storage unit array, storage units of the storage unit array are connected through word lines and bit lines to form an array, and first numbers participating in comparison are sequentially stored in the storage units of different word lines on the same bit line according to a bit sequence. The different word lines on the same bit line form a first word line group, and a second number participating in comparison is sequentially stored in a memory unit of a word line, which is different from any word line in the first word line group, on the same complementary bit line corresponding to the bit line according to a bit sequence. The word lines different from any word line in the first word line group form a second word line group, and the bit lines and the complementary bit lines are connected to the input ends of the sensing amplifiers corresponding to the bit lines. And the memory unit is a DRAM (Dynamic Random Access Memory) unit storage unit. The first number and the second number are binary numbers.

A user terminal that produces lighting effects for videos provided through a VOD service includes a communication unit for communicating with a server and a receiving device, a memory, and a processor electrically connected to the communication unit and the memory, and the processor is configured to acquire related information and playing time of the video, request and receive at least one piece of metadata from the server based on the related information, identify first metadata corresponding to the playing time from the at least one piece of metadata, generate a lighting control signal based on the first metadata, and transmit the lighting control signal to the receiving device.

The invention provides a standard cell memory and a chip, and the memory comprises an input latch module which carries out the latch output of a source enable signal, an address signal and a data signal; the address decoding control module is used for generating a write-in enable signal and a read-out enable signal based on the source enable signal and the address signal; the data storage module comprises a first storage unit and a second storage unit, the first storage unit and the second storage unit are arranged into a storage array based on a checkerboard pattern, enabling ends of the storage units in the same row are cascaded through an external phase inverter and receive selective writing enabling bits of the corresponding row, and data ends of the storage units in the same column are cascaded through an internal phase inverter and receive corresponding data bits; storing each data bit into each storage unit of the corresponding row based on the corresponding row write selection enabling bit; and the data reading module comprises a column reading unit and is used for reading the data bits in the storage units of the corresponding rows in a layered reading manner. According to the invention, the problem that the dynamic power consumption of the existing standard cell memory is increased along with the increase of the design capacity is solved.

In a data storage device with a multi-level-cell memory, bits of data are stored in different levels of each of the memory cells. In some situations, a quantized version of the stored data (e.g., the most-significant bits) may be requested. Responding to such a request can involve reading all levels of the memory cells to retrieve a full version of the data and then selectively providing only the quantized version. To improve performance, the data is stored in the memory in an interleaved manner in which the quantized version of the data is stored in the same level(s) instead of being spread across all levels of the memory cells. That way, when the quantized version of the data is later requested, only the relevant level(s) are sensed, thereby avoiding the time and resources needed to read memory level(s) that do not store the quantized data.

The invention discloses a cloth folding optimization method and equipment based on deep reinforcement learning. The method comprises the following steps: acquiring a cloth image, a key point and a folding actuator state in a mass point-spring physical simulation environment, and outputting a folding action by utilizing a model comprising a visual encoder, a strategy network and a double-action value network; a task progress is constructed based on a key point distance, sub-rewards such as angular point alignment, flatness, wrinkles and symmetry are dynamically weighted, and a stable folding strategy model is trained in combination with SumTree-based priority experience playback and advantage weighting strategy updating. The equipment comprises a folding actuator, an image acquisition unit, a memory and a processor, and the processor executes the strategy model and generates a control instruction according to an acquired image and an actuator state to drive the folding actuator to complete cloth folding. According to the scheme, the sample utilization rate and stability are improved, and a cloth folding strategy with higher folding quality and better generalization performance is obtained.

An embodiment relates to a robot executing a social-friendly navigation algorithm. The robot may include a communication unit, an input unit, a driving unit configured to move the robot, a memory, and at least one processor connected to the memory and configured to execute computer-readable instructions stored in the memory. By performing neural network computation using a separate processor and utilizing multiple processors in parallel, device efficiency may be improved.

This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

Systems, methods, and apparatus related to memory devices that use multi-pillar memory cells for performing multiplication and other operations. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. The memory cells are arranged in pillars of memory cells connected in series. Each memory cell uses at least one transistor from two or more different pillars. A bitline is formed overlying the pillars. The bitline is electrically connected to the pillars and accumulates output currents from the pillars when performing the matrix vector multiplication.

The embodiment of the invention provides a storage unit, a memory, a manufacturing method of the memory and electronic equipment. The memory cell comprises a read transistor and a write transistor, the read transistor is a double-gate transistor, and the read transistor comprises a first gate, a second gate, a first source / drain and a second source / drain; the first grid electrode is used for being electrically connected with a reading word line; the first source / drain electrode is used for being electrically connected with a reference voltage end; the write transistor comprises a third source / drain electrode and a fourth source / drain electrode; the third source / drain electrode is electrically connected with the second grid electrode; the fourth source / drain electrode and the second source / drain electrode are used for being electrically connected with a bit line. The read transistor is a planar transistor, the write transistor is a vertical transistor, and the read transistor and the write transistor are stacked in the direction vertical to the substrate, so that the integration density of the memory cell can be improved.

The embodiment of the invention discloses a memory device, a semiconductor device and a manufacturing method thereof. A memory device includes a memory cell including a first transistor and a second transistor disposed on a front side of a substrate having a first region and a second region. The memory device includes a first interconnect structure disposed on a backside of a substrate. One S / D terminal of the first transistor is coupled to one S / D terminal of the second transistor, and the other S / D terminal of the second transistor is coupled to the first interconnect structure through a first via structure in the first region. The memory device includes a second via structure and a third via structure, both disposed in the second region and each coupled to the first interconnect structure. The first via structure and the second via structure each have a different cross-sectional area than the third via structure.

A wireless network includes: a mobile device that includes a first central processing unit (CPU), a memory, and a first wireless communication module; a first instrument that includes a second CPU, a physiological sensor, and a second wireless communication module paired with the first wireless communication module; and a second instrument that includes a third CPU, a load sensor, and a third wireless communication module paired with the first wireless communication module. The second CPU is programmed to cause digital physiological variable data derived from analog data output by the physiological sensor to be broadcast by the second wireless communication module. The third central processing unit is programmed to cause digital body weight data derived from analog data output by the load sensor to be broadcast by the third wireless communication module. The first CPU is programmed to convert the digital physiological variable data into digital caloric intake data in accordance with an empirical relationship of a physiological variable to caloric intake stored in the memory and store the digital body weight data in the memory.

A memory apparatus including memory cells connected to one of a plurality of word lines and disposed in memory holes arranged in rows comprising a plurality of strings. The memory cells are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply one of a plurality of program pulses of a program voltage to ones of the plurality of word lines connected to the memory cells of at least two of the plurality of strings in a program operation. The control means is also configured to selectively program the memory cells of a first one of the plurality of strings followed by the memory cells of at least one subsequent one of the plurality of strings during the one of the plurality of program pulses of the program voltage.

Memory circuits with tracking cells are provided. A memory circuit includes a memory array comprising a plurality of first memory cells. The memory circuit includes a tracking column comprising one or more second memory cells. Each of the second memory cells is coupled to a first metallization layer disposed on a first side of a substrate and a second metallization layer disposed on a second side of the substrate, the second side opposite to the first side. The second metallization layer is configured to receive, from the second memory cells, a level of an internal node of a memory node. The first metallization layer is configured to provide, to the second memory cells, at least one supply voltage.

A nonvolatile memory device includes: a memory cell array including a plurality of cell strings, at least one of the cell strings including a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, at least one of the memory cells being a multi-level cell storing at least three bits; and a control logic circuit configured to control a page buffer to read a fast read page of the memory cell using one read voltage and at least two normal read pages of the memory cell using the same number of read voltages.

A memory device of a first array of memory cells configured as quad-level cell (QLC) memory or penta-level cell (PLC) memory and including one or more first planes. A second array of memory cells configured as second memory that is less-densely programmed than the first array, the second array including one or more second planes. Control logic receives a first command to program a first set of memory cells of the first array with a first logical state and a second command to program a second set of memory cells of the second array with a second logical state corresponding in threshold voltage range to the first logical state. The first and second sets of memory cells are associated with a shared wordline. The control logic causes the first and second sets of memory cells to be concurrently programmed with a threshold voltage distribution corresponding to the first logical state.

A memory cell includes a transistor located above a semiconductor substrate. The transistor includes a ferroelectric layer arranged along the sidewall of a word line. The ferroelectric layer includes a substance having a valence of 5, a valence of 7, or a combination thereof. The oxide semiconductor layer is electrically connected to a source line and a bit line. The ferroelectric layer is arranged between the oxide semiconductor layer and the word line. Embodiments of the present application provide a memory cell, a memory device, and a method for forming the same.

The invention relates to an image sensing device and an imaging device including the same. The image sensing apparatus includes: a pixel configured to generate a pixel signal having a single photon avalanche diode (SPAD) pulse by detecting incident light; a time-to-digital converter (TDC) configured to generate time-to-digital converter (TDC) data representative of a time of flight (TOF) of the SPAD pulse; and a TDC memory configured to store TDC data in a cell memory determined from among the plurality of cell memories according to a number of occurrences of the SPAD pulse.

An example two transistor (2T) gain cell memory with indium-gallium-zinc-oxide (IGZO) transistors. Examples include IGZO transistors included in a dynamic random access memory (DRAM) cell. The IGZO transistors included in the DRAM cell are described as being formed or created in a back end (BE) metal process stack of an integrated circuit chip or die.

Approaches presented herein provide for the reduction of workload bottlenecks during processing by offloading workload data to available data processing unit (DPU) memory, such as from graphics processing unit (GPU) memory or central processing unit (CPU) memory. Interfaces may be used to store the workload data to the pool of DPU memory, such as double data rate (DDR) memory, on-board non-volatile memory express (NVMe) devices, or NVMe devices over fabric. Interfaces may also be used to retrieve identified workload data required to complete a workload. The retrieved workload data may be provided to the GPU where the workload is completed. The pool of DPU memory may orchestrate transfers of the workload data. The workload data may be offloaded to the pool of DPU memory for training of a machine learning model. The workload data offloaded to the pool of DPU memory for training of a machine learning model may include model states, activation functions, or model checkpoints.

An example device includes a plurality of processing elements configured to perform a processing operation; memory cells interconnected with the processing elements, the memory cells organized into a plurality of wordlines, each wordline containing a set of columns; a controller interconnected with the processing elements, the controller configured to: for each coefficient vector of a coefficient matrix for the processing operation: assign a wordline identifier to each processing element; assign a column identifier to each processing element; write coefficients from the coefficient vector to the corresponding memory cell defined by the wordline identifier and the column identifier for each processing element; wherein the wordline identifiers and the column identifiers are assigned to the processing elements to load the coefficients of the coefficient vector in a diagonalized pattern in the memory cells.

An electronic device and a method for controlling the electronic device are disclosed. Specifically, the electronic device according to the present disclosure comprises: a communication unit; a memory including information related to a neural network model for predicting a target device for each time slot of the advertisement content; and a processor. In addition, the processor may: acquire usage history data of a user from the plurality of external devices; distributing and acquiring a plurality of feature values corresponding to the plurality of external devices for each time slot in the plurality of time slots based on the use history data; inputting the plurality of feature values into a neural network model so as to divide score information of a plurality of probabilities, related to the tag, of the plurality of external devices for each time slot in the plurality of time slots, and obtaining the score information; identifying a plurality of target devices for providing advertisement content for each of the plurality of time slots based on the score information; and control the communication unit to transmit information about the advertisement content to the plurality of target devices. Various other embodiments are also possible.