252 results about "Cell memory" patented technology

The invention relates to an apparatus and method for notifying a predictor with data object range information in a pointer. A processor of an aspect includes a cache hierarchy and a memory access unit coupled with the cache hierarchy. The memory access unit performs a demand load based on the Y-bit pointer such that the first one or more cache lines are loaded from the memory into the cache hierarchy. The Y-bit pointer has an X-bit virtual address field and a data object range field in one or more of the bits [Y-1: X]. A data object range field stores values. The processor also includes a prefetch unit coupled with the cache hierarchy. The prefetch unit determines whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy based at least in part on the value.

This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

A memory cell, a memory and an access method therefor, and an electronic device. The memory comprises: multiple layers of memory arrays stacked in a direction perpendicular to a substrate, and a plurality of first word lines (WL1) in one-to-one correspondence with the multiple layers of memory arrays. The memory arrays comprise a plurality of memory cells distributed along the arrays, and a plurality of second word lines (WL2) corresponding to rows of the multiple layers of memory arrays. Each memory cell comprises a transistor, the transistor comprising a first gate (G1) and a second gate (G2); the first gates (G1) of memory cells of the same layer are connected to first word lines (WL1) corresponding to the layer, and the second gates (G2) of memory cells in the same row of different layers are connected to second word lines (WL2) corresponding to the row.

In some implementations, a memory system may receive a first indication of one or more memory address ranges to be monitored and a second indication of a memory unit size. The memory system may determine one or more memory units associated with the one or more memory address ranges. The memory system may determine, using an access counter for each memory unit, a quantity of accesses to that memory unit during a monitoring period. The memory system may determine that a corresponding access counter for each memory unit, of a subset of the one or more memory units, satisfies an access threshold. The memory system may add an identifier of, and an indication of the corresponding access counter for, each memory unit, of the subset of the one or more memory units, to a data structure based on determining that the corresponding access counter satisfies the access threshold.

A method includes determining an address associated with a data transform command in a container data structure which is in the data transform accelerator. The data transform accelerator is in communication with a host computing unit. In response to a determination that the address is in the container data structure, the method includes accessing the data transform command based on the address. The data transform command is in the host computing unit. The method includes obtaining metadata based on information in the data transform command. The metadata is in the data transform accelerator or spread out in the host computing unit memory and in the memory of data transform accelerator. The method includes configuring a data transform pipeline based on the metadata. The metadata can be shared in its entirety or partially by multiple data transform commands grouped together.

A 3D in-memory computing accelerator system (100) and method for efficiently inferring a hybrid expert (MoE) neural network model. The system includes a plurality of in-memory computing cores (102), each memory core including a plurality of layers of in-memory computing units (106). One or more layers of the in-memory computing unit correspond to expert sub-models of the MoE model. One or more expert sub-models for activation propagation are selected according to a function-based routing (115) based on which a corresponding expert layer is activated. In one embodiment, the function is a hash-based layer selection function for dynamic routing of input and output activation. In an embodiment, the function is applied to select a single expert or multiple experts for single-level activation using input data based or using MoE based on layer activation. Further, the system is configured as a multi-model system with a single expert model selection or a multi-model system with multiple expert selections.

A communication system includes a target unit provided in a vehicle and including at least one target unit processor and at least one target unit memory coupled to each other; and a communication tool coupled to the target unit for bidirectional communication and including at least one communication tool processor and at least one communication tool memory coupled to each other. The communication tool processor transmits certain information including first certain data and a first padding value to the target unit. The target unit processor determines whether the first padding value matches a preset specific padding value, and transmits abnormality information to the communication tool when the first padding value does not match the specific padding value. Upon receiving the abnormality information, the communication tool processor transmits the certain information including the first certain data and a second padding value different from the first padding value to the target unit.

The invention discloses a numerical comparator which comprises a storage unit array, storage units of the storage unit array are connected through word lines and bit lines to form an array, and first numbers participating in comparison are sequentially stored in the storage units of different word lines on the same bit line according to a bit sequence. The different word lines on the same bit line form a first word line group, and a second number participating in comparison is sequentially stored in a memory unit of a word line, which is different from any word line in the first word line group, on the same complementary bit line corresponding to the bit line according to a bit sequence. The word lines different from any word line in the first word line group form a second word line group, and the bit lines and the complementary bit lines are connected to the input ends of the sensing amplifiers corresponding to the bit lines. And the memory unit is a DRAM (Dynamic Random Access Memory) unit storage unit. The first number and the second number are binary numbers.

A user terminal that produces lighting effects for videos provided through a VOD service includes a communication unit for communicating with a server and a receiving device, a memory, and a processor electrically connected to the communication unit and the memory, and the processor is configured to acquire related information and playing time of the video, request and receive at least one piece of metadata from the server based on the related information, identify first metadata corresponding to the playing time from the at least one piece of metadata, generate a lighting control signal based on the first metadata, and transmit the lighting control signal to the receiving device.

In a data storage device with a multi-level-cell memory, bits of data are stored in different levels of each of the memory cells. In some situations, a quantized version of the stored data (e.g., the most-significant bits) may be requested. Responding to such a request can involve reading all levels of the memory cells to retrieve a full version of the data and then selectively providing only the quantized version. To improve performance, the data is stored in the memory in an interleaved manner in which the quantized version of the data is stored in the same level(s) instead of being spread across all levels of the memory cells. That way, when the quantized version of the data is later requested, only the relevant level(s) are sensed, thereby avoiding the time and resources needed to read memory level(s) that do not store the quantized data.

The invention discloses a cloth folding optimization method and equipment based on deep reinforcement learning. The method comprises the following steps: acquiring a cloth image, a key point and a folding actuator state in a mass point-spring physical simulation environment, and outputting a folding action by utilizing a model comprising a visual encoder, a strategy network and a double-action value network; a task progress is constructed based on a key point distance, sub-rewards such as angular point alignment, flatness, wrinkles and symmetry are dynamically weighted, and a stable folding strategy model is trained in combination with SumTree-based priority experience playback and advantage weighting strategy updating. The equipment comprises a folding actuator, an image acquisition unit, a memory and a processor, and the processor executes the strategy model and generates a control instruction according to an acquired image and an actuator state to drive the folding actuator to complete cloth folding. According to the scheme, the sample utilization rate and stability are improved, and a cloth folding strategy with higher folding quality and better generalization performance is obtained.

An embodiment relates to a robot executing a social-friendly navigation algorithm. The robot may include a communication unit, an input unit, a driving unit configured to move the robot, a memory, and at least one processor connected to the memory and configured to execute computer-readable instructions stored in the memory. By performing neural network computation using a separate processor and utilizing multiple processors in parallel, device efficiency may be improved.

This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

A wireless network includes: a mobile device that includes a first central processing unit (CPU), a memory, and a first wireless communication module; a first instrument that includes a second CPU, a physiological sensor, and a second wireless communication module paired with the first wireless communication module; and a second instrument that includes a third CPU, a load sensor, and a third wireless communication module paired with the first wireless communication module. The second CPU is programmed to cause digital physiological variable data derived from analog data output by the physiological sensor to be broadcast by the second wireless communication module. The third central processing unit is programmed to cause digital body weight data derived from analog data output by the load sensor to be broadcast by the third wireless communication module. The first CPU is programmed to convert the digital physiological variable data into digital caloric intake data in accordance with an empirical relationship of a physiological variable to caloric intake stored in the memory and store the digital body weight data in the memory.

A memory apparatus including memory cells connected to one of a plurality of word lines and disposed in memory holes arranged in rows comprising a plurality of strings. The memory cells are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply one of a plurality of program pulses of a program voltage to ones of the plurality of word lines connected to the memory cells of at least two of the plurality of strings in a program operation. The control means is also configured to selectively program the memory cells of a first one of the plurality of strings followed by the memory cells of at least one subsequent one of the plurality of strings during the one of the plurality of program pulses of the program voltage.

Memory circuits with tracking cells are provided. A memory circuit includes a memory array comprising a plurality of first memory cells. The memory circuit includes a tracking column comprising one or more second memory cells. Each of the second memory cells is coupled to a first metallization layer disposed on a first side of a substrate and a second metallization layer disposed on a second side of the substrate, the second side opposite to the first side. The second metallization layer is configured to receive, from the second memory cells, a level of an internal node of a memory node. The first metallization layer is configured to provide, to the second memory cells, at least one supply voltage.

A memory device of a first array of memory cells configured as quad-level cell (QLC) memory or penta-level cell (PLC) memory and including one or more first planes. A second array of memory cells configured as second memory that is less-densely programmed than the first array, the second array including one or more second planes. Control logic receives a first command to program a first set of memory cells of the first array with a first logical state and a second command to program a second set of memory cells of the second array with a second logical state corresponding in threshold voltage range to the first logical state. The first and second sets of memory cells are associated with a shared wordline. The control logic causes the first and second sets of memory cells to be concurrently programmed with a threshold voltage distribution corresponding to the first logical state.

Approaches presented herein provide for the reduction of workload bottlenecks during processing by offloading workload data to available data processing unit (DPU) memory, such as from graphics processing unit (GPU) memory or central processing unit (CPU) memory. Interfaces may be used to store the workload data to the pool of DPU memory, such as double data rate (DDR) memory, on-board non-volatile memory express (NVMe) devices, or NVMe devices over fabric. Interfaces may also be used to retrieve identified workload data required to complete a workload. The retrieved workload data may be provided to the GPU where the workload is completed. The pool of DPU memory may orchestrate transfers of the workload data. The workload data may be offloaded to the pool of DPU memory for training of a machine learning model. The workload data offloaded to the pool of DPU memory for training of a machine learning model may include model states, activation functions, or model checkpoints.

An example device includes a plurality of processing elements configured to perform a processing operation; memory cells interconnected with the processing elements, the memory cells organized into a plurality of wordlines, each wordline containing a set of columns; a controller interconnected with the processing elements, the controller configured to: for each coefficient vector of a coefficient matrix for the processing operation: assign a wordline identifier to each processing element; assign a column identifier to each processing element; write coefficients from the coefficient vector to the corresponding memory cell defined by the wordline identifier and the column identifier for each processing element; wherein the wordline identifiers and the column identifiers are assigned to the processing elements to load the coefficients of the coefficient vector in a diagonalized pattern in the memory cells.

An electronic device and a method for controlling the electronic device are disclosed. In particular, the electronic device according to the present disclosure comprises: a communicator unit; a memory in which information on the encoder and training data for training the encoder are stored; and a processor that, when information about an original text in a first language is obtained, inputs the information about the original text into the encoder to obtain a first encoding vector representing semantic information included in the original text, inputs the first encoding vector into the discriminator, and identifies the semantic information included in the original text. And a controller configured to control the communicator to obtain a probability value indicating a probability that the first encoding vector will correspond to a normal translated text, and to control the communicator to transmit the first encoding vector to an external device including a decoder configured to obtain a translated text of a second language corresponding to the original text when the probability value is greater than or equal to a predetermined first threshold value, and to control the communicator to transmit the translated text of the second language to the external device when the probability value is greater than or equal to the predetermined first threshold value. When the probability value is less than a first threshold value, a second encoding vector having a highest similarity value indicating a similarity with the first encoding vector among encoding vectors included in the training data is identified, and the communicator is controlled to transmit the identified second encoding vector to the external device.

A slit lamp microscope of an embodiment includes an image acquiring unit, a memory, and a misalignment information acquiring processor. The image acquiring unit is configured to acquire an image by applying a scan with slit light to an anterior segment of a subject's eye. The memory stores a first image of the anterior segment and a second image that is acquired by follow-up photography performed by the image acquiring unit with reference to the first image. The misalignment information acquiring processor is configured to acquire misalignment information between the first image and the second image by analyzing the first image and the second image after the follow-up photography.

Methods, systems, and devices for voltage threshold distribution using read estimate are described. A memory system may determine a voltage threshold distribution of memory cells. For a target memory cell, the memory system may identify the type of memory cell and identify voltage ranges associated with the memory cell based on the type. The memory system may set reference voltages for each voltage range, and read the memory cell using the reference voltages by counting the quantity of logic states between the reference voltages and endpoints of the voltage ranges. The memory system may increment the reference voltages and reread the memory cell using the incremented reference voltages. After incrementing the reference, the memory system may use the counts determined during the reading operations to determine the voltage threshold distribution.

A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including: causing hardware initialization of a set of sub-blocks that are to be programmed within the array of memory cells; causing a first sub-block of the set of sub-blocks to be preconditioned for a program operation; causing multiple pages of data to be programmed to respective ones of the set of sub-blocks; and selectively causing a program verify to be performed on memory cells of the set of sub-blocks after programming the multiple pages of data.

Dual-access memory circuit (100) comprising: - FeRAM cells (102) arranged in rows and columns, each coupled to plate lines (106) and bit lines (112A, 112B) common to a column; and, during a dual access to cells (102.1 - 102.4) belonging to different columns, the memory circuit is configured to apply, to bit lines coupled to access transistors of unselected memory cells and in the conducting state, electrical potentials of the same values ​​as those applied to the plate lines coupled to the memory elements of the unselected memory cells. Figure for the abstract: Fig. 1

This invention provides a Content Addressable Memory (CAM) unit, a CAM memory device, an operation method thereof, and a data search and comparison method. The CAM unit includes: a first flash memory unit, a first terminal of which receives a first search voltage; and a second flash memory unit, a first terminal of which receives a second search voltage, and a second terminal of the first flash memory unit electrically connected to a second terminal of the second flash memory unit; wherein the first flash memory unit and the second flash memory unit are connected in series, and a stored data in the content addressable memory unit is determined by a combination of multiple threshold voltages of the first flash memory unit and the second flash memory unit.

To improve the convenience of communication between vehicles and communication devices.SOLUTION: An intermediation unit includes one or more intermediation unit processors and one or more intermediation unit memories connected to the intermediation unit processors. Each of the intermediation unit processors executes processes including: when a first message is received from a communication device and its destination is a first target unit, transmitting the first message to the first target unit without dividing it; and when the first message is received from the communication device and the destination is a second target unit, generating a plurality of first division messages by dividing the first message and sequentially transmitting the plurality of first division messages to the second target unit.SELECTED DRAWING: Figure 7

The utility model relates to the technical field of low-voltage distribution monitoring, in particular to a modularized extensible low-voltage distribution network monitoring device, which comprises a communication main module, a monitoring module, a load control module and an interface extension module. A power supply circuit, a microcontroller, a memory, a carrier signal modulation module and a metering unit are also arranged in the communication main module; the power supply circuit is electrically connected with the microcontroller, the HPLC communication unit and the metering unit respectively; the microcontroller is electrically connected with the metering unit, the memory and the carrier signal modulation module, and the HPLC communication unit is electrically connected with the carrier signal modulation module. Through modular design, high flexibility and expandability are realized, the module scale of the device can be flexibly adjusted according to actual requirements, and comprehensive monitoring of low-voltage transformer areas of different scales can be realized by increasing or reducing the number of monitoring modules.

A memory sub-system includes a memory device and one or more processing devices to perform operations. A failure exhibited by a set of memory cells of the memory device is detected. It is determined whether a subset of memory cells of the set of memory cells satisfies a first threshold condition based on a read level voltage corresponding to a per-cell memory density of the memory device. In response to determining that the subset of memory cells satisfies the first threshold condition, a first data recovery operation is selected from a set of data recovery operations. The first data recovery operation is performed on the set of memory cells.

The embodiment of the invention provides a management method for processing bad blocks of a memory and a memory system. A coding management circuit; and a memory access instruction decoding unit. The memory access instruction decoding unit is used for receiving an instruction from a bus; identifying bad blocks in the memory; judging whether the instruction indicates to access the bad block or not; when the instruction indicates that data is written into the bad block, the address of the bad block and the data are output to the coding management circuit so as to trigger the coding management circuit to update the coding management circuit; when the instruction indicates to read the bad block, the address is output to the coding management circuit so as to trigger the coding management circuit to output simulation data of the bad block, and the coding management circuit obtains the simulation data according to the address.

A memory apparatus is provided and includes memory cells configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes each connected to bit lines. Each of the bit lines is coupled to one of a plurality of sense amplifiers arranged in tiers. A control means is configured to program the memory cells in each of a plurality of program iterations of a program operation. The control means counts a failure quantity of a group of the memory cells having the threshold voltage below one of a plurality of verify voltages associated with one of the data states targeted for the memory cells in each of a plurality of verify iterations of a program operation. The count is a coarse count not separately counting the memory cells coupled with ones of the plurality of sense amplifiers of one or more of the tiers.