19 results about "Cell memory" patented technology

Provided are a computer program product, system, and method for compiling an application having polynomial operations to produce directed acyclic graphs having commands to execute in a near memory processing device. An application is compiled including operations on a polynomial having coefficients, decomposed into a number of levels of coefficient elements, to generate hierarchical directed acyclic graphs (DAGs) having nodes indicating commands for execution by a hierarchy of hardware components in a near memory processing (NMP) device. The hierarchy of hardware components includes a plurality of enclaves of tiles. Each tile includes memory and a processing element to perform operations on the decomposed coefficients stored in the memory of the tile. Each of the hardware components includes a controller to process the commands in the DAG generated for the hardware components. The DAGs are provided to a hierarchical DAG tracker to generate commands for the NMP device.

This invention provides a memory device and a memory array. The memory device includes memory cells. Each memory cell includes a first switching element, a second switching element, and a storage element. The first switching element is used to receive a write bit line signal and is coupled to a storage node. The second switching element is used to receive a read bit line signal and is coupled to the storage node. The storage element is coupled to the storage node and is used to receive a voltage signal and store a first data bit, wherein the memory cell is used to store a second data bit, different from the first data bit, in the storage node.

An electronic device includes: a sensor unit; a memory; a projection unit for outputting a light source to a projection surface; and at least one processor, wherein the at least one processor is configured to: identify a first projection position based on an ambient illuminance value obtained from first data through the sensor unit and based on a first luminance value of the projection surface; obtain a second luminance value corresponding to the luminance of a projected image output by the projection unit at the first projection position; while the projected image is being output, obtain a third luminance value corresponding to the luminance of a projection area, wherein the third luminance value is based on the second data obtained from the sensor unit; and control the projection unit to output the projected image at a second projection position identified based on the second luminance value and the third luminance value.

This invention relates to a fast read system and method for NAND Flash memory. The method includes the following steps: outputting a clock signal from the clock source of a SoC chip to the NAND Flash memory and a programmable delay unit of the SoC chip; triggering a data read operation on the falling edge of the clock signal in the NAND Flash memory, outputting data byte by byte to the data bus; and in the SoC chip, delaying the clock signal by the programmable delay unit and outputting a sampling clock to a read data capture unit, which samples the data on the data bus on the rising edge of the sampling clock. Compared to traditional non-continuous single-byte reads, the read method of this invention improves the data throughput and data read speed of the interface, and can achieve near-synchronous operation on the asynchronous interface of the NAND Flash memory.

An audio output apparatus is disclosed. The present apparatus comprises: a communication unit; a memory; an audio output unit; and a processor. When information regarding an external apparatus is received through the communication unit, the processor: determines a role of each apparatus on the basis of information stored in the memory and the received information; divides one piece of audio content into a plurality of audio elements; transmits an audio element corresponding to a role of the external apparatus to one external apparatus; and controls the audio output unit to output the audio element according to an output of the external apparatus. Accordingly, harmonious audio enjoyment becomes possible.

The present invention relates to a gain cell EDRAM with extended capacitance, providing a gain cell memory device including a semiconductor device layer including a silicon-on-insulator substrate of an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source / drain region adjacent to the storage transistor, the isolation structure extending through the active region to isolate a first portion of the active region from a second portion of the active region, and a capacitor coupled with the storage transistor. A bottom plate of the capacitor includes the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor includes the gate electrode of the storage transistor and a metal structure over the gate electrode.

Various embodiments of the present disclosure are directed to ferroelectric random access memory cells or some other suitable type of memory cells that include a bottom electrode interface structure. The memory cells also include a bottom electrode, a switching layer above the bottom electrode, and a top electrode above the switching layer. The bottom electrode interface structure separates the bottom electrode and the switching layer from one another. Moreover, the interface structure is dielectric and is configured to block or otherwise resist diffusion of metal atoms and / or impurities in the bottom electrode to the switching layer. By blocking or otherwise resisting such diffusion, leakage current can be reduced. Moreover, the durability of the memory cells can be increased. Various embodiments of the present disclosure are also directed to integrated circuit chips and methods of forming the same.

This invention discloses a heterogeneous system for implementing an attention mechanism in a large language model, comprising: a controller, a computing unit, and a memory; the computing unit includes a neural network processor and a graphics processor; the memory includes a local high-speed storage module; the controller controls the computing unit through an access interface and a data bus, and is connected to the memory via the computing unit; the computing unit and the local high-speed storage module are bidirectionally connected via a storage interface and a data bus; the heterogeneous system performs data transmission and exchange with an external global storage module; the local high-speed storage module and the global storage module are connected and interact with each other via a direct memory access channel. This invention also discloses an inference optimization method implemented through the above heterogeneous system, which has broad application value.

Control unit (35) for a wiper system (20) of a motor vehicle (10), comprising a control unit (95), a detection unit (95) and a memory (100), wherein the control unit (95) is connected to the memory (100) and the detection unit (90), wherein at least one first position characteristic curve (135) is stored in the memory (100), wherein the detection unit (90) is configured to detect a driving state of the motor vehicle and / or a system state of the wiper system (20) and to provide the control unit (95) with a status signal corresponding to the driving state, wherein the control unit (95) is configured to provide a control signal for controlling the wiper system (20) in a wiping movement across a window (15) of the motor vehicle (10), characterized in that a second position characteristic curve (140, 145) is stored in the memory (100), wherein the control unit (95) is trainedto detect the status signal of the detection device (90) and to select between the first and the second position characteristic curve (135, 140, 145) depending on the status signal and to provide a corresponding control signal according to the selection.

This invention discloses a remote upgrade system and method for a ZYNQ control platform, comprising: a remote user terminal, a ZYNQ control platform, and a memory cell address module. The remote user terminal connects to the ZYNQ control platform via a network. The remote user terminal and the ZYNQ control platform are configured to communicate via a network protocol. The ZYNQ control platform performs calculations and judgments through the memory cell address control software module, and then conducts encrypted data communication with QuadSPI Flash memory, NAND FLASH memory, and SD removable memory via the SPI interface. The upgrade file sent by the remote user terminal to the processor updates the bare metal, system, or application, and can also update FSBL, BIT, and other files individually. This invention eliminates the need for frequent hot-plugging and unplugging of JTAG, thus addressing the issues of rapid mass production and remote product maintenance.

A transistor device includes a substrate, a channel layer supported by the substrate, and a ferroelectric superlattice layer adjacent the channel layer. The ferroelectric superlattice layer includes a plurality of ferroelectric III-nitride alloy sub-layers. The plurality of ferroelectric III-nitride alloy sub-layers have different Group IIIB content levels.

An electronic device is disclosed. The electronic device includes: a projection unit; a driving unit; a memory for storing at least one computer program; and at least one processor communicatively connected to the projection unit, the driving unit, and the memory, wherein the at least one computer program includes computer-executable instructions, executed individually or collectively by the at least one processor, to cause the electronic device to perform the following operations: controlling the projection unit to project first content onto a projection surface; if the electronic device moves from a first position to a second position, identifying a projection angle of the projection surface based on the second position; obtaining second content by changing the screen shape of the first content based on the second position and the projection angle; and if the driving unit is controlled to move the electronic device from the first position to the second position, controlling the projection unit to project the second content onto the projection surface.

Disclosed is a method of storing data in a stuck-cell memory page of a memory array, the stuck-cell memory page having a cell at a stuck-cell-identifier cell of the memory page stuck at a stuck-cell-value, the method comprising: identifying a match between a first dataset and the stuck-cell memory page; and storing the dataset in the stuck-cell memory page; wherein the identifying a match comprises identifying that the at least one bit of the dataset which corresponds to the stuck-cell-identifier of the memory cell has a value which is equal to the stuck-cell value. A memory system configured for the above method is further disclosed.

Embodiments of the present disclosure relate to a memory device and an operating method of a memory device, the memory device including a first memory block and a second memory block, each of the first memory block and the second memory block including a plurality of memory cells. The memory device further includes a voltage generator for applying an operating voltage to a first global line, selectively applying a positive voltage to a global selection line included in a second global line while the operating voltage is applied, and applying a ground voltage to other global lines among the second global line except for the global selection line. The memory device further includes a row decoder for turning on a first pass switch between the first global line and a first local line connected to the first memory block, and turning off a second pass switch between the second global line and a second local line connected to the second memory block.

An electronic device and a method for controlling the electronic device are provided. The electronic device includes a sensor, a communication unit, memory, including one or more storage media, storing instructions, and at least one processor communicatively coupled to the sensor, the communication unit, and the memory, wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic apparatus to, identify whether a first type of sensor is included in the sensor when a request for access to a first type of sensor is received from an external device through the communication unit, perform authentication for allowing the external device to access the first type of sensor when the first type of sensor is identified to be included in the sensor, block another application remaining after excluding at least one application related to access to the first type of sensor by the external device from among multiple applications of the electronic device and other devices remaining after excluding the external device from accessing the first type of sensor, establish a security channel for communication with the external device by using encryption information, and when sensing data is obtained through the first type of sensor, control the communication unit to transmit information on the sensing data to the external device through the established security channel.

A gain cell memory device includes a semiconductor device layer of a silicon on insulator (SOI) substrate comprising an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source / drain region adjacent to the storage transistor, the isolation structure extending through the active region such that a first portion of the active region is isolated from a second portion of the active region, and a capacitor coupled to the storage transistor. A bottom plate of the capacitor comprises the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor comprises the gate electrode of the storage transistor and a metal structure over the gate electrode.

Disclosed are a clock delay compensation circuit and a memory device including the same. The memory device includes: a memory cell array including a plurality of memory cells; a memory peripheral portion controlling the memory cell array; and the interface comprises a system clock signal receiver, a data clock signal receiver, a data signal receiver and a clock delay compensation circuit. The clock delay compensation circuit includes a clock driver including a plurality of cross-coupled latches and a four-phase clock generation circuit. The clock driver generates a second pair of differential clock signals using the first pair of differential clock signals. The four-phase clock generation circuit generates a plurality of phase clock signals using the second differential clock signal pair. At least one of the plurality of cross-coupled latches receives an external power supply voltage.