175 results about "Cell memory" patented technology

A communication system includes a target unit provided in a vehicle and including at least one target unit processor and at least one target unit memory coupled to each other; and a communication tool coupled to the target unit for bidirectional communication and including at least one communication tool processor and at least one communication tool memory coupled to each other. The communication tool processor transmits certain information including first certain data and a first padding value to the target unit. The target unit processor determines whether the first padding value matches a preset specific padding value, and transmits abnormality information to the communication tool when the first padding value does not match the specific padding value. Upon receiving the abnormality information, the communication tool processor transmits the certain information including the first certain data and a second padding value different from the first padding value to the target unit.

A user terminal that produces lighting effects for videos provided through a VOD service includes a communication unit for communicating with a server and a receiving device, a memory, and a processor electrically connected to the communication unit and the memory, and the processor is configured to acquire related information and playing time of the video, request and receive at least one piece of metadata from the server based on the related information, identify first metadata corresponding to the playing time from the at least one piece of metadata, generate a lighting control signal based on the first metadata, and transmit the lighting control signal to the receiving device.

In a data storage device with a multi-level-cell memory, bits of data are stored in different levels of each of the memory cells. In some situations, a quantized version of the stored data (e.g., the most-significant bits) may be requested. Responding to such a request can involve reading all levels of the memory cells to retrieve a full version of the data and then selectively providing only the quantized version. To improve performance, the data is stored in the memory in an interleaved manner in which the quantized version of the data is stored in the same level(s) instead of being spread across all levels of the memory cells. That way, when the quantized version of the data is later requested, only the relevant level(s) are sensed, thereby avoiding the time and resources needed to read memory level(s) that do not store the quantized data.

The invention discloses a cloth folding optimization method and equipment based on deep reinforcement learning. The method comprises the following steps: acquiring a cloth image, a key point and a folding actuator state in a mass point-spring physical simulation environment, and outputting a folding action by utilizing a model comprising a visual encoder, a strategy network and a double-action value network; a task progress is constructed based on a key point distance, sub-rewards such as angular point alignment, flatness, wrinkles and symmetry are dynamically weighted, and a stable folding strategy model is trained in combination with SumTree-based priority experience playback and advantage weighting strategy updating. The equipment comprises a folding actuator, an image acquisition unit, a memory and a processor, and the processor executes the strategy model and generates a control instruction according to an acquired image and an actuator state to drive the folding actuator to complete cloth folding. According to the scheme, the sample utilization rate and stability are improved, and a cloth folding strategy with higher folding quality and better generalization performance is obtained.

An embodiment relates to a robot executing a social-friendly navigation algorithm. The robot may include a communication unit, an input unit, a driving unit configured to move the robot, a memory, and at least one processor connected to the memory and configured to execute computer-readable instructions stored in the memory. By performing neural network computation using a separate processor and utilizing multiple processors in parallel, device efficiency may be improved.

A wireless network includes: a mobile device that includes a first central processing unit (CPU), a memory, and a first wireless communication module; a first instrument that includes a second CPU, a physiological sensor, and a second wireless communication module paired with the first wireless communication module; and a second instrument that includes a third CPU, a load sensor, and a third wireless communication module paired with the first wireless communication module. The second CPU is programmed to cause digital physiological variable data derived from analog data output by the physiological sensor to be broadcast by the second wireless communication module. The third central processing unit is programmed to cause digital body weight data derived from analog data output by the load sensor to be broadcast by the third wireless communication module. The first CPU is programmed to convert the digital physiological variable data into digital caloric intake data in accordance with an empirical relationship of a physiological variable to caloric intake stored in the memory and store the digital body weight data in the memory.

A memory apparatus including memory cells connected to one of a plurality of word lines and disposed in memory holes arranged in rows comprising a plurality of strings. The memory cells are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply one of a plurality of program pulses of a program voltage to ones of the plurality of word lines connected to the memory cells of at least two of the plurality of strings in a program operation. The control means is also configured to selectively program the memory cells of a first one of the plurality of strings followed by the memory cells of at least one subsequent one of the plurality of strings during the one of the plurality of program pulses of the program voltage.

Memory circuits with tracking cells are provided. A memory circuit includes a memory array comprising a plurality of first memory cells. The memory circuit includes a tracking column comprising one or more second memory cells. Each of the second memory cells is coupled to a first metallization layer disposed on a first side of a substrate and a second metallization layer disposed on a second side of the substrate, the second side opposite to the first side. The second metallization layer is configured to receive, from the second memory cells, a level of an internal node of a memory node. The first metallization layer is configured to provide, to the second memory cells, at least one supply voltage.

A memory device of a first array of memory cells configured as quad-level cell (QLC) memory or penta-level cell (PLC) memory and including one or more first planes. A second array of memory cells configured as second memory that is less-densely programmed than the first array, the second array including one or more second planes. Control logic receives a first command to program a first set of memory cells of the first array with a first logical state and a second command to program a second set of memory cells of the second array with a second logical state corresponding in threshold voltage range to the first logical state. The first and second sets of memory cells are associated with a shared wordline. The control logic causes the first and second sets of memory cells to be concurrently programmed with a threshold voltage distribution corresponding to the first logical state.

Approaches presented herein provide for the reduction of workload bottlenecks during processing by offloading workload data to available data processing unit (DPU) memory, such as from graphics processing unit (GPU) memory or central processing unit (CPU) memory. Interfaces may be used to store the workload data to the pool of DPU memory, such as double data rate (DDR) memory, on-board non-volatile memory express (NVMe) devices, or NVMe devices over fabric. Interfaces may also be used to retrieve identified workload data required to complete a workload. The retrieved workload data may be provided to the GPU where the workload is completed. The pool of DPU memory may orchestrate transfers of the workload data. The workload data may be offloaded to the pool of DPU memory for training of a machine learning model. The workload data offloaded to the pool of DPU memory for training of a machine learning model may include model states, activation functions, or model checkpoints.

An example device includes a plurality of processing elements configured to perform a processing operation; memory cells interconnected with the processing elements, the memory cells organized into a plurality of wordlines, each wordline containing a set of columns; a controller interconnected with the processing elements, the controller configured to: for each coefficient vector of a coefficient matrix for the processing operation: assign a wordline identifier to each processing element; assign a column identifier to each processing element; write coefficients from the coefficient vector to the corresponding memory cell defined by the wordline identifier and the column identifier for each processing element; wherein the wordline identifiers and the column identifiers are assigned to the processing elements to load the coefficients of the coefficient vector in a diagonalized pattern in the memory cells.

A slit lamp microscope of an embodiment includes an image acquiring unit, a memory, and a misalignment information acquiring processor. The image acquiring unit is configured to acquire an image by applying a scan with slit light to an anterior segment of a subject's eye. The memory stores a first image of the anterior segment and a second image that is acquired by follow-up photography performed by the image acquiring unit with reference to the first image. The misalignment information acquiring processor is configured to acquire misalignment information between the first image and the second image by analyzing the first image and the second image after the follow-up photography.

Methods, systems, and devices for voltage threshold distribution using read estimate are described. A memory system may determine a voltage threshold distribution of memory cells. For a target memory cell, the memory system may identify the type of memory cell and identify voltage ranges associated with the memory cell based on the type. The memory system may set reference voltages for each voltage range, and read the memory cell using the reference voltages by counting the quantity of logic states between the reference voltages and endpoints of the voltage ranges. The memory system may increment the reference voltages and reread the memory cell using the incremented reference voltages. After incrementing the reference, the memory system may use the counts determined during the reading operations to determine the voltage threshold distribution.

Dual-access memory circuit (100) comprising: - FeRAM cells (102) arranged in rows and columns, each coupled to plate lines (106) and bit lines (112A, 112B) common to a column; and, during a dual access to cells (102.1 - 102.4) belonging to different columns, the memory circuit is configured to apply, to bit lines coupled to access transistors of unselected memory cells and in the conducting state, electrical potentials of the same values ​​as those applied to the plate lines coupled to the memory elements of the unselected memory cells. Figure for the abstract: Fig. 1

This invention provides a Content Addressable Memory (CAM) unit, a CAM memory device, an operation method thereof, and a data search and comparison method. The CAM unit includes: a first flash memory unit, a first terminal of which receives a first search voltage; and a second flash memory unit, a first terminal of which receives a second search voltage, and a second terminal of the first flash memory unit electrically connected to a second terminal of the second flash memory unit; wherein the first flash memory unit and the second flash memory unit are connected in series, and a stored data in the content addressable memory unit is determined by a combination of multiple threshold voltages of the first flash memory unit and the second flash memory unit.

A memory sub-system includes a memory device and one or more processing devices to perform operations. A failure exhibited by a set of memory cells of the memory device is detected. It is determined whether a subset of memory cells of the set of memory cells satisfies a first threshold condition based on a read level voltage corresponding to a per-cell memory density of the memory device. In response to determining that the subset of memory cells satisfies the first threshold condition, a first data recovery operation is selected from a set of data recovery operations. The first data recovery operation is performed on the set of memory cells.

A memory apparatus is provided and includes memory cells configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes each connected to bit lines. Each of the bit lines is coupled to one of a plurality of sense amplifiers arranged in tiers. A control means is configured to program the memory cells in each of a plurality of program iterations of a program operation. The control means counts a failure quantity of a group of the memory cells having the threshold voltage below one of a plurality of verify voltages associated with one of the data states targeted for the memory cells in each of a plurality of verify iterations of a program operation. The count is a coarse count not separately counting the memory cells coupled with ones of the plurality of sense amplifiers of one or more of the tiers.

A memory chip comprises memory banks, each memory bank including a compute unit. The memory banks are configured to be interconnected through an inter-bank network and perform inter-bank communication, and the compute unit is configured to perform a computation using data transmitted through the inter-bank network.

A continuous glucose monitoring (CGM) system is configured to detect a reinserted CGM sensor. The system reads a CGM sensor identifier stored in a CGM sensor unit memory in response to insertion of a CGM sensor into the skin of user. The system compares the identifier to any previously-stored identifiers of previously-inserted CGM sensors. If the identifier does not match a previously-stored identifier, indicating a newly-inserted sensor, the identifier is stored and CGM may begin. If the identifier matches a previously-stored identifier, indicating a reinserted sensor, a usage limit corresponding to the stored identifier of the reinserted sensor is then checked to determine whether it has been met. If it has, CGM is halted. If it has not, CGM may continue with the reinserted CGM sensor. Methods of detecting reinsertion and usage limits of a CGM sensor are also provided, as are other aspects.

In a data storage device with a multi-level-cell memory, bits of data are stored in different levels of each of the memory cells. In some situations, a quantized version of the stored data (e.g., the most-significant bits) may be requested. Responding to such a request can involve reading all levels of the memory cells to retrieve a full version of the data and then selectively providing only the quantized version. To improve performance, the data is stored in the memory in an interleaved manner in which the quantized version of the data is stored in the same level(s) instead of being spread across all levels of the memory cells. That way, when the quantized version of the data is later requested, only the relevant level(s) are sensed, thereby avoiding the time and resources needed to read memory level(s) that do not store the quantized data.

Three-terminal, multi-level non-volatile memory cells having a FeFET in the BEOL are provided. In one aspect, a memory cell includes: a cascade of elements all sharing a common gate terminal and, via the common gate terminal, a common VG, where the cascade of elements includes: an nMOS FET; an ox-FeFET located in the BEOL that is connected to the nMOS FET; and a pMOS FET that is connected to the ox-FeFET. Multi-cell memory implementations thereof, and methods for operating the present memory cells are also provided.

Semiconductor devices and methods are disclosed, including memory cells / memory strings, semiconductor devices and systems. Example semiconductor devices and methods include a stack of alternating dielectric layers and conductor layers, and a vertical conductor passing between a top level of the stack and a bottom level of the stack. Lateral connections are included between a location along the vertical conductor and a selected conductor layer from the stack, wherein a direct interface is formed between the vertical conductor and the selected conductor layer.

Processing logic in a memory sub-system receives, from a host system, a plurality of write commands for writing data to the memory device. Upon writing the data to a cache of the memory device, the processing logic generates a plurality of completion entries, the plurality of completion entries corresponding to the plurality of write commands and comprising respective timestamps, wherein the respective timestamps are based on a target host-to-cache data rate, and sends the plurality of completion entries to the host system based on the respective timestamps.

A data processing device includes a detection unit, a memory and a processor. The processor performs a short-term Fourier transform on photoplethysmographic data to generate a first spectrogram matrix. The processor also performs numerical split processing on the first spectrogram matrix to generate a first spectrum matrix, where the first spectrum matrix includes first spectrum arrays arranged in sequence from left to right. The processor also inputs the first spectrum arrays into a transformer model from left to right to generate second spectrum arrays in sequence, and transforms the second spectrum arrays into a second spectrum matrix according to an order in which the second spectrum arrays are generated. The processor also performs numerical combining processing on the second spectrum matrix to generate a second spectrogram matrix, and performs an inverse short-term Fourier transform on the second spectrogram matrix to generate arterial blood pressure data.

A memory apparatus includes memory cells connected to word lines and configured to store a threshold voltage corresponding to data states. The memory cells are disposed in memory holes coupled to bit lines. A control means applies program pulses to selected ones of the word lines. The control means determines when the threshold voltage of each of the memory cells exceeds a lower verify level of one of the data states targeted and maintains a respective count of a number of the program pulses subsequently applied thereto before reaching a lockout state. Each of the program pulses is divided into phases. The control means sets a voltage of one of the bit lines coupled to each of the memory cells at a stepped up level as a function of the respective count and according to each of the phases in which the voltage is set to the stepped up level.

Processing logic in a memory sub-system monitors an amount of free space in a cache of a memory device, determines an operating gear of a host system based on the amount of free space in the cache of the memory device, and configures one or more data rate control parameters of the system based on the operating gear of the host system.

An integrated circuit memory device includes a semiconductor pattern including a first source / drain impurity region, a second source / drain impurity region and a channel region extending in series between the first and second source / drain impurity regions. A dual work function word line is provided, which includes a first material having a first work function on a first portion of the channel region, and a second material having a second work function greater than the first work function on at least a second portion of the channel region. A bit line is electrically connected to the first source / drain impurity region, and a first node of a memory cell storage device is electrically connected to the second source / drain impurity region. The first and second source / drain impurity regions may be net P-type impurity regions.

The invention relates to a self-timing memory circuit. A dummy SRAM cell included in a dummy row of a memory circuit including first and second data storage nodes connected by cross-coupled latch circuitry. The first pass gate transistor has a first source / drain node connected to the first data storage node, a second source / drain node connected to a ground node, and a gate node coupled to a dummy word line. The first data storage node is also connected to a ground node. The second pass gate transistor has a first source / drain node connected to the second data storage node, a second source / drain node connected to the first source / drain node, and a gate node coupled to the dummy word line. The read transistor and the pass transistor are coupled in series. A gate node of the pass transistor is coupled to the dummy read word line, and a source / drain node of the pass transistor is connected to a ground node.

This application relates to hybrid parallel programming of single-level cell memory. A memory device includes a page buffer having a cache register and a data register, a memory array having a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including causing a first page of SLC data to be stored in the cache register, causing the first page of the SLC data to be moved from the cache register to a first data register, causing a subsequent page of the SLC data to be stored in the cache register, causing the SLC data stored in the cache register and the SLC data stored in the data register to be programmed concurrently to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block, and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel.

A storage unit, a memory, an electronic device and a data read-write method, the storage unit comprising: a write transistor comprising a first electrode, a second electrode and a first gate electrode; a read transistor comprising a third electrode, a fourth electrode and a second gate electrode; a switch transistor comprising a fifth electrode, a sixth electrode and a third gate electrode; a storage node; wherein the fourth electrode is connected with the second electrode; the first electrode is connected with the storage node, and the first gate electrode is connected with a write word line; the third electrode is connected with a first bit line, and the second gate electrode is connected with the storage node; the fifth electrode is connected with the fourth electrode and the second electrode, the sixth electrode is connected with a second bit line, and the third gate electrode is connected with a read word line; the write transistor is used for controlling storage data to be written into the storage node, and the read transistor is used for controlling the storage data to be read. The storage unit of the embodiment of the application is convenient for realizing read-write operation, has simple structure, is easy to manufacture, and occupies small area.