70results about "Error correction/detection using block codes" patented technology

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

A digital steganography system comprises a message sender in electronic communication with a message receiver through a social media platform. The message sender uses a compute device configured to conceal a secret digital message in the semantic components of a digitally synthesized image which is uploaded onto the social media platform and published in a social media post. As part of the message encoding process, the compute device for the message sender coverts the digital message into binary code, applies encryption and error-correction algorithms, and then implements image synthetization operations to yield the digitally synthesized image. The message receiver is provided with a compute device configured to identify the social media post, automatically download the synthesized image, and apply an inverse set of the image synthetization operations to yield binary code which is subsequently decoded and decrypted in order to extract the original covert message.

A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.

An integrated circuit includes data terminals 0 to 11; an ECC encoder circuit configured to operate an H matrix on transmission data to be transmitted to the data terminals 0 to 11 to generate a transmission parity code, the transmission parity code corresponding to the transmission data; and an ECC decoder circuit configured to operate the H matrix on reception data and a reception parity code received through the data terminals 0 to 11 to detect and correct an error in the reception data. A data portion of the H matrix is divided into 24 groups, each of the 24 groups includes a group matrix portion and a non-group matrix portion, the group matrix portion is used by k group matrices that circulate in the 24 groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups is shifted.

The embodiment of the invention provides a data block coding method and device, a data block recovery method and device and electronic equipment. The data block coding method comprises the steps that a plurality of original data blocks are divided to obtain a plurality of groups, the groups comprise at least one cross block, and the cross blocks are the same original data blocks in the groups; constructing a Cauchy matrix based on the number of the original data blocks and the number of the groups; generating a global check block of each group based on the Cauchy matrix and the plurality of original data blocks, generating a local check block of each group based on the Cauchy matrix, the plurality of original data blocks, a preset cross block coefficient and a cross block, and adding the global check block and the local check block of each group into each group, and a plurality of grouped global check blocks are added to form a new global check block, so that multiple local recovery modes are realized, and the recovery delay is prevented from being too long.

An encoding method, applied to the field of encoding technologies, may be used for reducing the delay and reducing the decoding memory, and includes: obtaining a data signal including a plurality of information bits; and performing encoding process on the data signal to obtain an encoded signal. An encoding block in the encoded signal includes a first encoding sub-block and at least one second encoding sub-block. The first encoding sub-block includes first component codewords and second component codewords, and all information bits constitute an information bit matrix. Each second encoding sub-block includes a first check matrix, which includes first check bit sets each determined based on bits of a first bit matrix with same side lengths, and the first check bit set and the bits of the first bit matrix constitute a third component codeword.

An encoding method, applied to the field of encoding technologies, may be used for reducing the delay and reducing the decoding memory, and includes: obtaining a data signal including a plurality of information bits; and performing encoding process on the data signal to obtain an encoded signal. An encoding block in the encoded signal includes a first encoding sub-block and at least one second encoding sub-block. The first encoding sub-block includes first component codewords and second component codewords, and all information bits constitute an information bit matrix. Each second encoding sub-block includes a first check matrix, which includes first check bit sets each determined based on bits of a first bit matrix with same side lengths, and the first check bit set and the bits of the first bit matrix constitute a third component codeword.

The present disclosure provides a data error correction circuit and a data transmission method. The data error correction circuit includes a data error correction module used for receiving first data and a first check code corresponding to the first data, correcting an error in the first data according to the first check code to generate second data, and outputting the second data, and a check code generation module used for receiving the first data and the first check code, and generating and outputting the second check code according to the first data and the first check code. The embodiment of the present disclosure can save elements and layout area required for the data error correction function.

A communication device may include: a processor configured to perform a procedure comprising: receiving a first consensus check code from a first communication device; receiving a second consensus check code from a second communication device; generating a combination code by network encoding the first consensus check code and the second consensus check code; and instructing the transmission of the combination code to the first communication device and to the second communication device.

A method for improving the forward error correction in serial coding in a data transmission in a vehicle allowing the physical behavior on a transmission channel to always be deterministically controlled despite a reduction in the resource requirements. Tit errors are minimal and a transmission error can be corrected efficiently. In addition, encoders used are designed with a minimum number of gates and an interleaving is implicit in the proposed method, which is based on the fact that burst errors can be corrected particularly advantageously. This interleaving makes it possible to dispense with conventional buffer memory required for explicit interleaving. In addition, user data together with correcting metadata can be encoded advantageously. It can be ensured that not only the user data is line-coded or line-encoded, but also the correction data. Also provided is a system for implementing the method.

To provide methods for transmitting and receiving an audio stream.SOLUTION: For transmission, a method involves obtaining a frame of an audio signal, and determining a number of source blocks to divide the frame of the audio signal into and a number of parity blocks to generate for forward error correction. The number of source blocks and the number of parity blocks are determined based on characteristics of a wireless communication protocol to be used. The wireless communication protocol may be BLUETOOTH. The parity blocks are usable by a decoder to reconstruct one or more corrupted or missing source blocks and may be obtained by means of Reed-Solomon encoding.SELECTED DRAWING: Figure 1

The present invention relates to a method for generating a bit sequence that can be transmitted efficiently and has a limited disparity and a limited run length. The proposed method allows data to be able to be transmitted particularly efficiently on a transmission channel. Compared to the prior art, the invention offers, among other things, the advantage that the physical behaviour on a transmission channel can always be deterministically controlled despite a reduction in resource requirements. Thus, according to the proposed method, bit errors are minimal and a transmission error can be corrected efficiently, i.e. with minimal technical effort. Furthermore, the encoders used are designed with a minimal number of gates, and the proposed method implicitly includes an form of nesting that allows so-called burst errors to be corrected particularly advantageously.

A coding method and apparatus are provided. The method includes: coding an information bit by using a preset generator matrix of a systematic (U|U+V)-code to obtain a codeword of a systematic code. The preset generator matrix of the systematic (U|U+V)-code includes a first identity sub-matrix of a U code and a second identity sub-matrix of a V code. A plurality of elements in a same column as the first identity sub-matrix are all 0. A plurality of elements in a same column as the second identity sub-matrix are all 0.

Provided in the present application are a data block encoding method, a data block recovery method, an apparatus and an electronic device. The data block encoding method comprises: partitioning a plurality of original data blocks to obtain a plurality of groups, the plurality of groups comprising at least one cross block, and the cross block being the same original data block in the plurality of groups; on the basis of the number of the original data blocks and the number of the groups, constructing a Cauchy matrix; and generating a global parity block of each group on the basis of the Cauchy matrix and the plurality of original data blocks, generating a local parity block of each group on the basis of the Cauchy matrix, the plurality of original data blocks, a preset cross block coefficient and the cross block, and adding the global parity block and the local parity block of each group into the group, the global parity blocks of the plurality of groups being added to form a new global parity block.

A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a memory cell array, an error correction circuit, an input / output (I / O) gating circuit, and a control logic circuit. The memory cell array is coupled to a word line and a bit line, and is divided into subarray blocks. The error correction circuit generates parity data based on main data using an error correction code (ECC). The control logic circuit controls the error correction circuit and the I / O gating circuit based on a command and an address. The control logic circuit stores the main data and the parity data in (k+1) target subarray blocks in a second direction among the subarray blocks, and controls the I / O gating circuit such that a portion of the (k+1) target subarray blocks stores both a portion of the main data and a portion of the parity data.

The invention relates to a method for generating an efficiently transmittable bit sequence with a limited degree of discrepancy and a limited run length. The proposed method allows a particularly efficient transmission of data over a transmission channel. Compared with the prior art, one of the advantages of the invention is that the physical behavior on the transmission channel can be certainly controlled all the time although the resource demand is reduced. Thus, according to the proposed method, bit errors are few, and transmit errors can be corrected efficiently (i.e., with little technical effort). Furthermore, the encoder used is designed to have a minimum number of gates, and interlacing is implied in the proposed method, which ensures that so-called burst errors can be particularly advantageously corrected.

An error correction apparatus (20) that performs two-bit error correction decoding using a block error correcting code includes: a syndrome generation unit (1) that generates a syndrome pattern from a reception sequence; a number-of-errors determination unit (2) that determines a number of bit errors in the reception sequence based on the syndrome pattern; and a two-bit error candidate error correction unit (5) that calculates a first parameter based on the syndrome pattern in a case where the number-of-errors determination unit (2) determines that there is a two-bit error and that there is a possibility of correction of the two-bit error, excepts the first parameter, from the first parameter to be used, based on which the number-of-errors determination unit determines that the two-bit error is uncorrectable, and obtains a normalized root for the two-bit error by using a second parameter obtained by degeneracy of the first parameter by one bit, the first parameter being a constant term of a normalized polynomial and being a normalized parameter, the normalized polynomial being obtained by normalization of a quadratic error locator polynomial.

A decoding method implemented at a decoder. The method includes determining a current channel realized reliability metric for each symbol in a received sequence of symbols. The current channel realized reliability metrics of the symbols are then sorted to identify a predetermined number of most reliable independent bits in the sequence. A set of one or more bit-flip patterns are then enumerated based on the current channel realized reliability metrics of the predetermined number of the most reliable independent bits in the sequence. The set of bit-flip patterns or a subset thereof are then applied to a received vector corresponding to the sequence of symbols to decode a codeword.

Technologies for storing burst error information in a buffer structure and signaling to prevent overflow and over-writing the buffer structure are described. One controller device includes error detection logic, a buffer, and buffer control logic. The error detection logic detects an error in a read operation associated with a memory device coupled to the controller device. The buffer stores error information associated with the error. The buffer control logic generates and outputs a first signal responsive to the buffer being full.

A method for transmitting and receiving an audio stream is provided. For transmission, the method includes obtaining a frame of an audio signal and determining a number of source blocks for dividing the frame of the audio signal and a number of parity blocks to generate for forward error correction. The number of source blocks and the number of parity blocks are determined based on characteristics of a wireless communication protocol to be used. The wireless communication protocol may be BLUETOOTH. The parity blocks may be used by a decoder to reconstruct one or more corrupted or missing source blocks and may be obtained by Reed-Solomon encoding.

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

The present disclosure provides a data error correction circuit and a data transmission method. The data transmission circuit includes: a data error correction module, receiving first data and a first check code corresponding to the first data, the data error correction module is used to correct the first data according to the first check code to generate second data, and output the second data; a check code generation module, receiving the first data and the first check code, and generating and outputting a second check code according to the first data and the first check code. The embodiments of the present disclosure can save the components and layout area required for the data error correction function.

Code blocks (CBs) are transmitted by a transmitting device and received by a receiving device in a wireless communication network. The CBs are generated based on a batch of physical layer packets to which a subset of higher-layer encoded packets are mapped, and the higher-layer encoded packets are generated from higher-layer information packets. Packets of the higher-layer information packets that are used to generate the subset of higher-layer encoded packets for the batch overlap with packets of the higher layer information packets that are used to generate a further subset of the higher-layer encoded packets for mapping to a further batch of physical layer packets. Check blocks are also transmitted and received, and each check block is generated based on portions of multiple CBs.

Provided are a communication method, a communication device, and a storage medium. The communication method applied to the first communication device includes performing, based on code type indication information, FEC decoding on part or all of associated downstream slots using an FEC code type corresponding to the code type indication information (S110), where the code type indication information is received from a second communication device and is used to indicate an FEC code type used in at least one of the associated downstream slots.

Analog error correction circuit (100) comprising: one or more non-volatile resistive analog memory crossbar arrays comprising: a first crossbar array portion including a circuit (102) programmed with values of a multiplication matrix (A'); a second crossbar array part for correcting calculation errors, which includes a circuit (104) programmed with values of an encoder matrix (A''), the values of the encoder matrix (A'') depending on the values of the multiplication matrix (A'); and a third crossbar array part for detecting calculation errors, which contains a circuit (114) programmed with values of a decoder matrix, wherein the first crossbar array part and the second crossbar array part are configured to output a first output (c') and a second output (c''), respectively, representing a result (c) of a matrix multiplication operation with an input vector (u), wherein the first and second outputs (c', c'') are provided as inputs for the third crossbar array part, and wherein a third output of the third crossbar array part indicates whether a calculation error is present in the first output (c') of the first crossbar array part, wherein the third output of the third crossbar array part represents a measured syndrome vector (212), and wherein the measured syndrome vector (212) comprises two off-threshold values indicating the presence of the calculation error in the first output (c') of the first crossbar array part, wherein the measured syndrome vector (212) is thresholded to obtain a thresholded syndrome vector (302), and wherein the thresholded syndrome vector (302) is fed back to the third crossbar array part to determine the location of the calculation error.

Various aspects of this disclosure provide a device (100) for encoding a digital data word (102). The device (100) may include a processor (104) configured to group (302) a digital data word (102) having a plurality of bits into at least one data word bit group (DB), wherein the at least one data word bit group (DB) has at least two bits; add (304) to the at least one data word bit group (DB) at least one bit (Zb) of a predefined value at a predefined position within the at least one data word bit group (DB); encode (306) the extended at least one data word bit group (106) with the at least one added bit (Zb) using an encoding method that operates on bit groups, such that a codeword (110) is generated having at least one information bit group (112) and at least one check word bit group (114);Removing (308) the at least one added bit (Zb) from the at least one information bit group (112) so that at least one reduced information bit group (116) is formed; and storing (310) the at least one reduced information bit group (116) and the at least one check word bit group (114).

Method for encoding source data, method for decoding code words, corresponding devices and computer program. The invention relates to a method for encoding at least one block of source data, delivering at least one code word of size , said method implementing a step of encoding said source data using a parity matrix . According to the invention, said parity matrix is ​​obtained from a basic matrix expressed in the form: The extension matrix comprises at least two blocks of rows and at least one block of columns, with an integer between 1 and , each block of rows comprising at least one matrix obtained by applying a circular rotation coefficient to a diagonal matrix of size , with an integer between 0 and , said at least one block of columns comprising at least two matrices obtained by applying a distinct circular rotation coefficient to said diagonal matrix of size .Figure for abstract: Figure 5A.

A data processing method, a medium, a computing device, and a program product. The method comprises: acquiring original data from an external storage unit of a processor; writing the original data into an internal storage unit of the processor; respectively carrying out a plurality of data processing operations on the original data stored in the internal storage unit to obtain a plurality of processing results of the original data; and writing the plurality of processing results of the original data into the external storage unit from the internal storage unit.