145 results about "Ldpc decoding" patented technology

The invention discloses a data error correction method and device based on low-density parity check, equipment and a medium, and relates to the technical field of data error correction, and the method comprises the steps: reading data to be corrected from a data memory, and carrying out the pre-verification of the data to be corrected and a verification matrix of a preset low-density parity check code, and obtaining a pre-verification result; based on the pre-verification result, determining a first error position set in a code word position set; performing bit flipping operation on code words indicated by the first error position set to complete pre-error correction; and inputting the code word after pre-error correction processing into a low density parity check decoder for decoding, outputting data after error correction, pre-detecting the error position of the code word, and performing bit flipping on the code word at the error position, thereby reducing the number of error bits entering LDPC decoding, and improving the decoding efficiency. Therefore, the number of error bits does not exceed the decoding capability limit of hard decoding, the probability that the system enters soft decoding is reduced, and the decoding throughput rate of the system is ensured.

The invention provides a belief propagation LDPC decoding method and device based on deep learning, a medium and a program product. The method comprises the following steps: acquiring an LDPC code training sample set corresponding to a check matrix H; according to the check matrix H, determining a weight matrix and an activation function of each layer of a deep learning decoding model; based on the weight matrix and the activation function, using a belief propagation algorithm to establish a deep learning decoding model; training the deep learning decoding model by using the training sample set, and storing the trained deep learning decoding model as a decoder; and sending the LDPC code soft information which is corresponding to the check matrix H and needs to be decoded into the decoder to complete LDPC decoding. According to the method, iterative operation is completed by using deep learning in the error correction decoding process, the number of decoding iterations is reduced, and the sequence sent by the sending end is restored from the sequence containing noise and interference, so that the problem of decoding error codes caused by noise and other interference factors is solved.

The invention discloses a layered LDPC (Low Density Parity Check Code) decoding method based on syndrome feedback self-adaption, and aims to solve the problem of poor decoding performance caused by fixed correction factors and poor adaptability to different check matrixes and channel conditions in the existing LDPC decoding algorithm. The method comprises the following steps of: firstly, dividing rows of a check matrix into a plurality of independent layers by adopting a hierarchical scheduling architecture so as to accelerate propagation and convergence of decoding information; secondly, in each iteration process of hierarchical decoding, a self-adaptive mechanism based on syndrome feedback is used, and a core offset factor beta in an offset minimum sum algorithm is adjusted in real time; the mechanism intelligently increases or decreases the offset factor by diagnosing the current decoding state (i.e., the number of unsatisfied check equations) to help the decoding process jump out of local optimum and stably converge. A simulation result shows that compared with a traditional offset minimum sum algorithm, the decoding performance is effectively improved and the bit error rate is reduced on the premise that the complexity is not obviously increased, and particularly, the performance gain is obvious in a medium-high signal-to-noise ratio region, and the robustness is higher.

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

The invention discloses a coding method, a decoding method and a device, which are used for supporting an IEEE (Institute of Electrical and Electronic Engineers) 802.11 ax next generation Wi-Fi (Wireless Fidelity) protocol (such as 802.11 be, Wi-Fi7 or EHT), or an IEEE 802.11 be next generation Wi-Fi protocol (such as 802.11 bn, Wi-Fi 8 or UHR), or Wi-Fi AI (Wireless Fidelity), or MMW (Millimeter Wave), or UWB (Ultra Wideband) or perception and the like. After acquiring an information bit sequence, the first communication device performs LDPC encoding on the information bit sequence based on a check matrix to obtain an encoded sequence, and outputs the sequence. The length of the sequence is N1, N1 is n times of 1944, and n is an integer greater than or equal to 2. Z of the check matrix can be equal to 81. And after obtaining the to-be-decoded information, the second communication device performs LDPC decoding in combination with the check matrix to obtain an information bit sequence. The method can improve the decoding performance.

The invention relates to a coding method, a decoding method and a device, in the coding method, first equipment can determine a second bit sequence and a third bit sequence based on a first bit sequence, and the third bit sequence comprises a bit sequence of which the weight is higher than a first threshold in a base graph corresponding to the first bit sequence. That is, the weight corresponding to the second bit sequence is lower than the weight corresponding to the third bit sequence. Furthermore, the first device can perform polar code coding on the second bit sequence, which is equivalent to providing additional protection for the second bit sequence with lower weight in a polar code coding mode, so as to improve the error correction performance. And for the third bit sequence with relatively high weight, LDPC coding can be performed on the third bit sequence and a polarization code coding result (namely, a fourth bit sequence obtained by performing polarization code coding on the second bit sequence). The error floor of LDPC decoding is reduced, and the error correction performance of LDPC codes is improved.

The invention relates to an LDPC (Low Density Parity Check) decoding method and system based on a dynamic scale factor, belongs to the technical field of circuit design, and solves the problem of low decoding performance caused by adopting a fixed value to correct deviation in the prior art. Comprising the following steps: S1, receiving to-be-decoded information, initializing posterior probability information and check node information, and iteratively executing S2-S4 until a termination condition is met; s2, acquiring a decoding decision value according to the check matrix and the hard decision value of the posterior probability information, identifying whether a termination condition is met or not according to the decoding decision value and the number of iterations, if yes, outputting a decoding result, and otherwise, entering S3; s3, updating variable node information according to posterior probability information and check node information of the last iteration; calculating a dynamic scale factor, and updating check node information according to the dynamic scale factor and the updated variable node information; and S4, updating the posterior probability information according to the updated check node information to obtain the posterior probability information of the current iteration, and returning to S2. And the decoding performance is improved.

The invention relates to an LDPC (Low Density Parity Check) decoder oriented to a CCSDS (Consultative Committee for Space Data System) standard and a decoding method thereof, relates to the technical field of satellite communication and channel coding, and aims to solve the technical problems of insufficient parallelism and low resource utilization rate of a satellite communication LDPC decoder in the prior art. The LDPC decoder for the CCSDS standard comprises a frame input module, a control module, an initial probability storage module, a check node calculation module, a variable node calculation module and a frame output module. The LDPC decoder facing the CCSDS standard and the decoding method thereof are suitable for efficient decoding of long-frame data in satellite communication, dynamic block storage architecture, hybrid iterative decoding algorithm and configurable control module collaborative design, balance of decoding algorithm performance and complexity is achieved through storage design optimization, the algorithm flexibility is improved through a configurable strategy, and the decoding efficiency is improved. And the contradiction between the efficiency and resources of long-frame LDPC decoding in satellite communication is systematically solved.

The invention discloses a multi-user joint decoding method for a cellular-free large-scale MIMO system based on model-driven deep learning, and the method comprises the steps: building an optimization problem of a simulation combination matrix with maximization of the reachable rate of the cellular-free large-scale MIMO system as a target in a simulation part of data decoding; on the basis of a heuristic algorithm, an optimization target is simplified, an optimization problem is divided into a plurality of sub-problems, the single AP simulation precoding matrix optimization problem is solved one by one, and an optimal simulation combination matrix is obtained; a multi-user joint LDPC decoding algorithm is expanded to a cellular-free large-scale MIMO scene, multi-user joint LDPC decoding is realized based on an MIMO-LDPC-Net decoding network, an input layer of the MIMO-LDPC-Net decoding network generates an initial value as an input of a hidden layer, the hidden layer is formed by stacking modules composed of a first sub-layer, a second sub-layer and an MIMO detection layer, and the first sub-layer, the second sub-layer and the MIMO detection layer are stacked. The output layer generates a log-likelihood ratio of the variable node. Experiments show that compared with a traditional algorithm, the heuristic algorithm and the AI auxiliary joint decoding algorithm have a signal-to-noise ratio gain of 1dB.

The invention relates to an adaptive low density parity check (LDPC) decoder architecture. An LDPC decoder architecture is provided for adaptively adjusting an LDPC control input for successfully decoding a corresponding received code block. The architecture supports a machine learning based process that facilitates learning the optimal LDPC control input required for a given channel condition and deployment scenario, such as log-likelihood (LLR) term scaling. This is accomplished by an unused LDPC decoder accelerator collecting posterior decoding metrics as a background process, the function of the accelerator being to process a tagged LLR dataset of different LDPC control input values. This optimal LDPC control input estimate may then be applied to real-time LDPC decoding based on previous learning under UE / channel conditions.

The embodiment of the invention provides an LDPC decoding capability test application method and device, storage equipment, a storage medium and a program product, and relates to the technical field of storage. According to the method, after the LDPC decoding function of the main control chip is started, reading operation is performed on the storage medium, the decoding failure probability corresponding to a plurality of invalid bit numbers is obtained, and the decoding capability performance of the main control chip for different invalid bit number scenes can be reflected. And reading operation is directly performed on the storage medium through the test platform to obtain the data volume ratio corresponding to the plurality of invalid bit numbers, so that the original error distribution characteristics of the storage medium under the condition that decoding correction is not performed can be reflected. And finally, through quantitative comparison and analysis of the original error distribution characteristics of the storage medium and the decoding performance of the main control chip, scientificity and reliability of LDPC decoding capability evaluation of the storage medium with different code rates by different main control chips are ensured, so that a solid technical basis and a clear judgment standard are provided for project decision making.

The present invention provides a method and device for high-speed LDPC decoding of broadband signals with low computing power requirements, relating to the field of radio monitoring. This method addresses the issues of long processing time, high resource consumption, and difficulty in engineering implementation of current LDPC code decoders. The method comprises: buffering data frames and serially reading and processing adjacent codewords in the data frames to be decoded after configuration; determining long codewords and designing control logic timing; and achieving multi-path concurrent processing of long codewords under low computing power requirements through soft switching of parallelism parameters. The method also includes designing a concurrent decoding processing path and iteratively updating variable nodes and check nodes based on an improved NMSA decoding algorithm. After satisfying the iterative stopping strategy, a decoded bit sequence for the long codeword is obtained, forming a decoding result under low computing power requirements. The present invention has the characteristics of low processing latency, low resource consumption, and is suitable for practical use environments. It can effectively improve the decoding processing rate and decoding data throughput of satellite signal monitoring.

Disclosed are a 64-bit LDPC decoding method and device for BeiDou-3 satellite signals. The implementation of each stage's operations is more rigorous and detailed, providing confidence vectors for check node updates and variable node updates, and the required finite field elements for final verification, making the decoding process easier to understand and implement. A permutation process is added before check node updates, a depermutation process is added before variable node updates, and a posteriori confidence calculation is performed before final verification. The posteriori LLR is calculated by adding the LLRs of two non-zero confidence vectors in the same column to the original LLRs and sorting them. The corresponding finite field element of the minimum LLR is the calculation result. The finite field element obtained from the posterior confidence calculation is finite field multiplied with the check matrix for verification.

The present application discloses a method and apparatus for LDPC decoding using index messages. The present invention discloses a low density parity check (LDPC) decoder, the LDPC decoder comprising a variable node unit (VNU), the VNU comprising a plurality of variable nodes configured to perform a sum. A first message mapper of the LDPC decoder receives a first n1-bit index from a likelihood ratio (LLR) input and maps the first n1-bit index to a first numerical value of the variable nodes input to the VNU. A second message mapper of the LDPC decoder receives a second n2-bit index from a check node unit (CNU) and maps the second n2-bit index to a second numerical value of the variable nodes input to the VNU. The CNU comprises a plurality of check nodes that perform parity check operations. The ranges of the first numerical value and the second numerical value are respectively greater than the ranges represented in n1-bit and n2-bit binary.

The embodiment of the application discloses a kind of LDPC decoding device and electronic equipment applied to chip, it is related to circuit field.The LDPC decoding device of the application includes: demodulation unit, first buffer unit, second buffer unit, LDPC decoder and controller;Wherein, the output of demodulation unit is connected with the input of first buffer unit, the output of first buffer unit is connected with the input of second buffer unit, the output of second buffer unit is connected with LDPC decoding unit;Controller is connected with the control end of first buffer unit and the control end of second buffer unit respectively;First data queue is arranged in first buffer unit, and second data queue is arranged in second buffer unit.The queue buffering mechanism is introduced in the application, the order and integrity of data are guaranteed, decoding requirements are flexibly adapted, and the rate matching problem between the LDPC decoder of rear end and the demodulation unit of front stage is effectively solved by using asynchronous processing mode.

The present invention discloses an LDPC decoding method, device, equipment and computer-readable storage medium, belonging to the field of decoding, and is used for LDPC decoding of data stored in NAND. When performing LDPC encoding and decoding, it is necessary to pad some data with zeros. Considering that during the decoding process, the data at the zero-padding positions in the variable nodes itself has a definite value and relatively high credibility. If a relatively complex decoding algorithm is used to update the prior probability and posterior probability of the zero-padding positions in the variable nodes, the decoding efficiency will inevitably be reduced. Therefore, in the decoding process of this application, a preset optimization update algorithm is used to update the prior probability and posterior probability of the zero-padding positions in the variable nodes. By setting a suitable preset optimization update algorithm, the amount of computation can be greatly reduced. On the one hand, the number of error corrections within a limited number of iterations can be increased, and on the other hand, the working efficiency is improved and the energy consumption is reduced.

A method for generating a parity check matrix, and a communication apparatus. The method comprises: acquiring a base matrix, the base matrix comprising a first matrix, the first matrix being a matrix consisting of the first column to the tenth column and the first row to the fourth row of the base matrix, elements comprised in the first column of the base matrix being all non-zero elements, and the first column being a punctured column; and, on the basis of the base matrix, obtaining a parity check matrix of a non-binary low-density parity check (LDPC) code, the parity check matrix being used for LDPC coding or LDPC decoding. The elements comprised in the first column of the base matrix are all non-zero elements, and the first column is a punctured column, such that the code rate of the LDPC code corresponding to the base matrix provided in the method can reach 2 / 3. Compared with the prior art, the method improves the code rate of non-binary LDPC codes, thereby improving coding and decoding performance of non-binary LDPC codes.

The present invention provides a method for generating LDPC soft information, comprising reading hard bit data corresponding to data stored in an NVM; performing LDPC hard decision decoding based on the hard bit data to obtain an LDPC hard decision decoding result and a hard decision decoding output; if the LDPC hard decision decoding result is a failure, reading soft bit data associated with the hard bit data; mapping the hard decision decoding output and the soft bit data into soft information; and performing LDPC soft decision decoding based on the soft information. The technical solution of the present invention can reduce the number of repeated flash reads, improve throughput, and increase decoding success rate.

The present invention discloses a highly reliable and secure transmission method based on OTFS. For a source sequence at the transmitting end, a transmission sequence is obtained after sequentially undergoing LDPC encoding, QAM mapping, SVD precoding, inverse symplectic finite Fourier transform, Heisenberg transform, R-CP addition, D / A conversion, and up-conversion, which is then transmitted via a wireless channel. After a legitimate user's receiving end obtains the received sequence, down-conversion, A / D conversion, R-CP removal, Wigner transform, symplectic finite Fourier transform, SVD decoding, single-tap equalizer processing, QAM demapping, and LDPC decoding are performed to obtain a destination sequence. The present invention achieves highly reliable physical layer secure transmission in highly dynamic communication scenarios through precoding technology based on an OTFS equivalent matrix and error control coding technology based on LDPC, thereby improving system total throughput and spectrum efficiency, and reducing system peak-to-average ratio and transmission bit error rate, while simultaneously avoiding excessive computational complexity and time-frequency resource overhead.

The invention discloses a coding method and device and a decoding method and device. A sending end acquires a first bit sequence, performs LDPC coding on the first bit sequence based on a check matrix to obtain a second bit sequence, and outputs the second bit sequence. Correspondingly, the receiving end receives the to-be-decoded information of the second bit sequence, LDPC decoding is carried out on the to-be-decoded information of the second bit sequence based on the check matrix, and K1 information bits are obtained. Wherein the check matrix is determined based on the corresponding relation of the first information columns and the first base graph, and the column number of the first information columns is determined based on the number K1 of the information bits and the column number K of the information columns of the first base graph. According to the technical scheme provided by the invention, the code rate can be effectively improved.

The present invention provides a low-complexity LDPC decoding method, medium and device applicable to the NR standard. The method includes: calculating an effective check node set; discarding variable nodes that are no longer updated in the soft decision information based on the effective check node set; performing hard decision using the soft decision information from which the variable nodes that are no longer updated have been discarded to obtain an LDPC decoding result, and using CRC check as a judgment condition for LDPC decoding termination. By discarding the calculation of variable nodes whose soft decision information is no longer updated, the present invention can effectively reduce the computational complexity of LDPC decoding under high code rate conditions without degrading the performance.

The present invention discloses an underwater wireless single-photon communication system and method based on adaptive coding and decoding, relating to the field of underwater wireless single-photon communication systems. The system comprises: a transmitting end and a receiving end; the transmitting end comprises a data coding and modulation module and a laser emission module; the receiving end comprises a detection module and a data processing module; the data coding and modulation module is used to obtain a target LDPC coding rate and, based on the target LDPC coding rate, perform LDPC coding and modulation on the data to be transmitted to generate a corresponding modulated signal; the laser emission module is used to convert the modulated signal into an optical signal and transmit it to an underwater channel; the detection module is used to detect single-photon signals formed after the optical signal is attenuated by the underwater channel; and the data processing module is used to demodulate and LDPC decode the detected single-photon signals to obtain the original data to be transmitted. The present invention can adapt to the LDPC coding rate, thereby achieving efficient and reliable data transmission in complex underwater environments.

The invention provides a greedy confidence method and device applied to low-density parity check codes, and the method comprises the steps: initializing a decoder, and obtaining a variable node and a check node after initialization processing; transmitting a message obtained based on the received signal to a check node through the variable node; a greedy optimization strategy is adopted to carry out partial node updating and iteration in the message transmission process of the variable nodes and the check nodes, and an optimal analysis result is obtained; and obtaining decoding information according to the optimal analysis result, and outputting a decoding result for the decoding information. According to the invention, the greedy algorithm is applied to the BP algorithm, the BP algorithm is optimized, messages of part of variable nodes and check nodes are updated according to a greedy optimization strategy, the complexity of the BP algorithm is reduced, the iteration time is effectively reduced, the decoding time delay is reduced, and the LDPC decoding efficiency is improved.

The invention provides an LDPC decoding method, a program product, an electronic device and a storage medium, and is applied to the technical field of communication, and the LDPC decoding method comprises the steps: obtaining an expansion factor corresponding to LDPC decoding and to-be-decoded data; determining the degree of parallelism corresponding to LDPC decoding according to the expansion factor; decoding the to-be-decoded data according to the expansion factor, the parallelism degree and the check matrix to obtain target decoded data corresponding to the plurality of clock cycles; and calculating judgment output according to the target decoding data corresponding to the plurality of clock periods respectively. The degree of parallelism is automatically determined according to the expansion factor, and the to-be-decoded data is decoded in combination with the expansion factor, the degree of parallelism and the check matrix, so that expansion factors of different sizes can be dynamically adapted. When small expansion factor data is processed, hardware resources are fully utilized, and the decoding speed is increased; and when large expansion factor data is processed, hardware implementation complexity increase and power consumption overload are avoided, so that the resource utilization rate and the processing speed are improved.

The present application provides a communication method and apparatus. In the method, a communication apparatus performs first-stage lifting on a first matrix (for example, a base matrix) to obtain a second matrix, which is used for obtaining a check matrix, and then performs LDPC encoding or LDPC decoding by means of the obtained check matrix. By means of the above implementation, it is beneficial to increasing the scale of the check matrix, thereby optimizing the decoding threshold.

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Decoding low-density parity check (LDPC) codes in a communication system includes identifying a first set of indices of variable nodes (VNs) having log-likelihood ratios (LLRs) greater than a threshold. A second set of indices that includes the first set of indices, indices of shortening VNs, and indices of single parity check (SPC) VNs is created. LDPC decoding proceeds by iteratively updating check-to-variable (C2V) messages and variable-to-check (V2C) messages, with updates for a VN being skipped when an index of the respective VN belongs to the second set of indices.

The invention relates to the technical field of decoding, and discloses a three-code-in-one interpretation method and device of a probability domain based on a storage and calculation integrated device, which can configure a three-code-in-one decoding array comprising an LDPC (Low Density Parity Check) decoding array, a Polar decoding array and a Turbo decoding array on the storage and calculation integrated device based on a target probability graph model corresponding to three error correction codes to be interpreted. According to a probability domain operation mode, determining a state value initial probability of each variable node in each target probability graph model, and using the state value initial probability of each variable node in each target probability graph model and the three-code-in-one decoding array to perform unified interpretation on three to-be-interpreted error correction codes so as to obtain an error correction code interpretation result; according to the invention, unified interpretation of the to-be-interpreted LDPC code, the Polar code and the Turbo code is realized, and unified decoding power consumption of the to-be-interpreted LDPC code, the Polar code and the Turbo code can be effectively reduced.

The invention relates to the technical field of communication, in particular to a coding method and device and a decoding method and device. The method can be applied to the IEEE 802.11 ax standard, the 802.11 be standard, the 802.11 bn standard and the like and other standards of the IEEE 802.11 series, such as the 802.15 standard, the 802.11 bf standard, the IMMW standard or the star flash standard and the like. The method comprises the following steps: a first site obtains information bits, performs LDPC coding on the information bits based on a check matrix, obtains coded bits, and outputs a sequence. And after obtaining the to-be-decoded information, the second station performs LDPC decoding in combination with the check matrix to obtain information bits. The code length corresponding to the check matrix is 7776, the code rate corresponding to the check matrix is 3 / 4, and the expansion factor of the check matrix is 162. The check matrix can be better matched with a longer code length, and the coding and decoding performance is improved.

The invention discloses a satellite-borne SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) program on-orbit reconstruction system, which comprises a data processing unit, a JFMRS01RH unit, an external storage unit and a target FPGA, and is characterized in that the data processing unit comprises a satellite-ground data processing module used for receiving an intermediate frequency signal from a satellite and carrying out demodulation, AOS (Advanced Orthogonal System) data frame recovery, data descrambling and LDPC (Low Density Parity Check) decoding; the on-satellite data processing module is used for carrying out AOS data frame analysis, uploading data packet recombination, verification and secondary packaging; the JFMRS01RH unit is used for receiving the uploading data packet which is secondarily packaged by the data processing unit, performing state monitoring and feeding back to the data processing unit, and is also used for task scheduling management; the external storage unit is used for caching the recombined uploading data packet and is also used for storing an uploading file to be loaded to the target FPGA; and the target FPGA is used for providing logic control and algorithm implementation for the load of the on-orbit satellite.

The application discloses a model-driven neural network-based offset min-sum LDPC code decoding algorithm and relates to an offset min-sum LDPC code decoding algorithm. The application is designed to solve the problems of the traditional LDPC decoding algorithm in convergence speed, calculation complexity, flexibility and the like. The application comprises the following steps: 1, a model-driven offset min-sum algorithm network model is constructed, wherein the network model comprises an input layer, a check node layer, a variable node layer and an output layer; 2, the input layer is used to calculate the received channel LLR by using a received signal y to perform initialization; 3, the check node layer is used to calculate the CN-to-VN LLR value; 4, the variable node layer is used to calculate the VN-to-CN LLR value; and 5, the output layer is used to calculate a final decoding output. The application belongs to the technical field of decoding.