268 results about "Ldpc decoding" patented technology

The invention provides a coding method, a decoding method and a communication device, in the coding method, a basis matrix of LDPC is designed by adopting a JSCC scheme, a state column is introduced into a verification part of the basis matrix, a first column of the verification part is a state column with high column weight, a second column is a column with a degree of 1, and the first column and the second column are different. According to the JSCC-LDPC decoding method and the JSCC-LDPC decoding system, the element '1' in the column with the degree of 1 and the element '2' in the state column are located in the same row of the basis matrix, and the combination of the column with the degree of 1 and the state column can improve the decoding threshold of the JSCC-LDPC and improve the decoding performance of the JSCC-LDPC.

The invention discloses a high-performance low-complexity LDPC (Low Density Parity Check) decoding method for satellite communication, and belongs to the field of digital signal processing. And performing iterative decoding on the received channel information based on a low density parity check (LDPC) code in the 5G standard. The implementation method comprises the following steps of: dynamically setting an erasing range by utilizing the amplitude of current check node information when a variable node is updated; the amplitude of check node information is gradually increased along with the increase of the number of iterations, the whole iteration process is divided into two parts, and the erasing range is set by adopting different parameters. And outputting the decoding result when the decoding result is correct or reaches the maximum number of iterations. According to the method, the reliability of variable node information is improved through the two points, reliable variable information is prevented from being erased, unreliable variable node information is prevented from being spread, and excellent decoding performance is achieved. Non-linear operation in a log-likelihood ratio belief propagation algorithm LLR-BPA does not exist in the decoding algorithm, and the decoding algorithm has the advantages of being high in decoding performance and low in decoding complexity.

The invention discloses a data error correction method and device based on low-density parity check, equipment and a medium, and relates to the technical field of data error correction, and the method comprises the steps: reading data to be corrected from a data memory, and carrying out the pre-verification of the data to be corrected and a verification matrix of a preset low-density parity check code, and obtaining a pre-verification result; based on the pre-verification result, determining a first error position set in a code word position set; performing bit flipping operation on code words indicated by the first error position set to complete pre-error correction; and inputting the code word after pre-error correction processing into a low density parity check decoder for decoding, outputting data after error correction, pre-detecting the error position of the code word, and performing bit flipping on the code word at the error position, thereby reducing the number of error bits entering LDPC decoding, and improving the decoding efficiency. Therefore, the number of error bits does not exceed the decoding capability limit of hard decoding, the probability that the system enters soft decoding is reduced, and the decoding throughput rate of the system is ensured.

A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and / or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).

The invention discloses a coding method, a decoding method and a device, which are used for supporting an IEEE (Institute of Electrical and Electronic Engineers) 802.11 ax next generation Wi-Fi (Wireless Fidelity) protocol (such as 802.11 be, Wi-Fi7 or EHT), or an IEEE 802.11 be next generation Wi-Fi protocol (such as 802.11 bn, Wi-Fi 8 or UHR), or Wi-Fi AI (Wireless Fidelity), or MMW (Millimeter Wave), or UWB (Ultra Wideband) or perception and the like. The method comprises the following steps: a first communication device obtains an information bit sequence, performs LDPC coding on the information bit sequence based on a check matrix, obtains a coded sequence, and outputs the sequence. The length of the sequence is N1, N1 is n times of 1944, and n is an integer greater than or equal to 2. And after obtaining the to-be-decoded information, the second communication device performs LDPC decoding in combination with the check matrix to obtain an information bit sequence. The method can improve the decoding performance.

The invention provides an LDPC (Low Density Parity Check) decoding method based on a node reliability dynamic correction criterion. The LDPC decoding method comprises the following steps: step 1, initializing channel information; step 2, judging whether the maximum number of iterations is reached or not, if so, outputting a result, otherwise, entering step 3; 3, calculating extrinsic information from the check node to the variable node; 4, calculating extrinsic information from the variable node to the check node; 5, adjusting the correction factor according to the matching condition of the variable node symbol and the last iteration symbol; 6, if the correction factor exceeds the threshold value, limiting the correction factor to be the threshold value, otherwise, continuing the next step; 7, multiplying the correction factor by the variable node information, and adjusting the weight of the node information; 8, calculating full information of the variable nodes and performing hard decision; step 9, checking whether the judgment result meets the condition that the checksum is zero or not, if so, outputting a decoding result, otherwise, continuing iteration; and step 10, if the condition is not met, entering a next round of iteration, and updating check node information.

The invention provides a belief propagation LDPC decoding method and device based on deep learning, a medium and a program product. The method comprises the following steps: acquiring an LDPC code training sample set corresponding to a check matrix H; according to the check matrix H, determining a weight matrix and an activation function of each layer of a deep learning decoding model; based on the weight matrix and the activation function, using a belief propagation algorithm to establish a deep learning decoding model; training the deep learning decoding model by using the training sample set, and storing the trained deep learning decoding model as a decoder; and sending the LDPC code soft information which is corresponding to the check matrix H and needs to be decoded into the decoder to complete LDPC decoding. According to the method, iterative operation is completed by using deep learning in the error correction decoding process, the number of decoding iterations is reduced, and the sequence sent by the sending end is restored from the sequence containing noise and interference, so that the problem of decoding error codes caused by noise and other interference factors is solved.

The invention discloses a space laser communication device, and relates to the technical field of laser communication. The system comprises a protocol stack module, an Aurora Ethernet data forwarding module, a ground monitoring instruction issuing module, an RS422 serial port transceiving module, an LVDS link state reporting module, a laser link channel monitoring module, a self-adaptive rate switching module, a rate gear identification module, a sending channel and a receiving channel. The sending channel comprises a first CRC verification module, a PN code filling module, an LDPC coding module, an interleaving module and a first GTX serial-parallel conversion module. The receiving channel comprises a second CRC verification module, a PN code deletion module, an LDPC decoding module, a de-interleaving module and a second GTX serial-parallel conversion module. According to the invention, an anti-turbulence effect can be achieved in a digital domain, so that high rate and low error code of data transmission are ensured; on the premise of ensuring the transmission rate, the reliability is improved, and the performance of the optical system is improved.

The invention discloses a layered LDPC (Low Density Parity Check Code) decoding method based on syndrome feedback self-adaption, and aims to solve the problem of poor decoding performance caused by fixed correction factors and poor adaptability to different check matrixes and channel conditions in the existing LDPC decoding algorithm. The method comprises the following steps of: firstly, dividing rows of a check matrix into a plurality of independent layers by adopting a hierarchical scheduling architecture so as to accelerate propagation and convergence of decoding information; secondly, in each iteration process of hierarchical decoding, a self-adaptive mechanism based on syndrome feedback is used, and a core offset factor beta in an offset minimum sum algorithm is adjusted in real time; the mechanism intelligently increases or decreases the offset factor by diagnosing the current decoding state (i.e., the number of unsatisfied check equations) to help the decoding process jump out of local optimum and stably converge. A simulation result shows that compared with a traditional offset minimum sum algorithm, the decoding performance is effectively improved and the bit error rate is reduced on the premise that the complexity is not obviously increased, and particularly, the performance gain is obvious in a medium-high signal-to-noise ratio region, and the robustness is higher.

A base graph-based parallel LDPC decoding method and apparatus, a device, and a medium. The method comprises: in response to a decoding request for target data, on the basis of a preset instruction set, generating an LDPC decoding code adapted to the current processor (S110); on the basis of an expansion factor corresponding to the decoding request, determining a target subgraph corresponding to a base graph, and generating a check matrix matching the target subgraph (S120); performing grouping on the check matrix by row according to a preset grouping rule, and obtaining decoding block sequences by division on the basis of the expansion factor (S130); and executing the LDPC decoding code, and on the basis of the decoding block sequences, performing, in parallel, loop iteration and update on check nodes in a tanner graph obtained by transforming the check matrix, so as to obtain a decoding result of the target data (S140).

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

The invention discloses an offset minimum sum LDPC (Low Density Parity Check) code decoding algorithm based on a model-driven neural network, and relates to an offset minimum sum LDPC code decoding algorithm. The invention aims to solve the problem that a traditional LDPC decoding algorithm is insufficient in convergence speed, calculation complexity, flexibility and the like. The method comprises the following steps: step 1, constructing a model-driven offset minimum sum algorithm network model, wherein the network model comprises an input layer, a check node layer, a variable node layer and an output layer; step 2, an input layer calculates a receiving channel LLR by using the receiving signal y to carry out initialization; step 3, the check node layer calculates the LLR value of the CN-to-VN; step 4, the variable node layer calculates the LLR value of the VN-to-CN; and step 5, calculating final decoding output by an output layer. The invention belongs to the technical field of decoding.

The invention discloses a coding method, a decoding method and a device, which are used for supporting an IEEE (Institute of Electrical and Electronic Engineers) 802.11 ax next generation Wi-Fi (Wireless Fidelity) protocol (such as 802.11 be, Wi-Fi7 or EHT), or an IEEE 802.11 be next generation Wi-Fi protocol (such as 802.11 bn, Wi-Fi 8 or UHR), or Wi-Fi AI (Wireless Fidelity), or MMW (Millimeter Wave), or UWB (Ultra Wideband) or perception and the like. After acquiring an information bit sequence, the first communication device performs LDPC encoding on the information bit sequence based on a check matrix to obtain an encoded sequence, and outputs the sequence. The length of the sequence is N1, N1 is n times of 1944, and n is an integer greater than or equal to 2. Z of the check matrix can be equal to 81. And after obtaining the to-be-decoded information, the second communication device performs LDPC decoding in combination with the check matrix to obtain an information bit sequence. The method can improve the decoding performance.

The method includes: A transmitter obtains a first bit sequence, and then performs LDPC encoding on the first bit sequence based on a check matrix, to obtain a second bit sequence. Correspondingly, a receiver receives the second bit sequence, and then performs LDPC decoding on the second bit sequence based on the check matrix, to obtain K information bits. The first bit sequence includes the K information bits, the second bit sequence includes M check bits, and both K and M are positive integers. The check matrix is obtained based on a first base matrix, the first base matrix corresponds to a second base matrix, the second base matrix includes the following elements: 0, 1, and 2.

The invention relates to a coding method, a decoding method and a device, in the coding method, first equipment can determine a second bit sequence and a third bit sequence based on a first bit sequence, and the third bit sequence comprises a bit sequence of which the weight is higher than a first threshold in a base graph corresponding to the first bit sequence. That is, the weight corresponding to the second bit sequence is lower than the weight corresponding to the third bit sequence. Furthermore, the first device can perform polar code coding on the second bit sequence, which is equivalent to providing additional protection for the second bit sequence with lower weight in a polar code coding mode, so as to improve the error correction performance. And for the third bit sequence with relatively high weight, LDPC coding can be performed on the third bit sequence and a polarization code coding result (namely, a fourth bit sequence obtained by performing polarization code coding on the second bit sequence). The error floor of LDPC decoding is reduced, and the error correction performance of LDPC codes is improved.

The invention provides a decoding method of a low-density parity check code, electronic equipment and a storage medium, and relates to the technical field of communication. The method comprises the following steps: acquiring a processor model of a user terminal, and matching system computing power information corresponding to the processor model; obtaining a first case decoding time corresponding to a low density parity check (LDPC) decoding test case; and obtaining the maximum number of iterations according to the system computing power information and the first case decoding time, and performing LDPC decoding based on the maximum number of iterations when the to-be-decoded data is received. According to the LDPC decoding method and device, the maximum number of iterations is cooperatively determined in combination with the two aspects of system computing power information and use case decoding time, LDPC decoding is carried out through the maximum number of iterations, the requirement of a communication system for communication performance is met, the error rate of LDPC decoding is reduced to a certain extent, and therefore the number of retransmission times of data is reduced.

The invention relates to an LDPC (Low Density Parity Check) decoding method and system based on a dynamic scale factor, belongs to the technical field of circuit design, and solves the problem of low decoding performance caused by adopting a fixed value to correct deviation in the prior art. Comprising the following steps: S1, receiving to-be-decoded information, initializing posterior probability information and check node information, and iteratively executing S2-S4 until a termination condition is met; s2, acquiring a decoding decision value according to the check matrix and the hard decision value of the posterior probability information, identifying whether a termination condition is met or not according to the decoding decision value and the number of iterations, if yes, outputting a decoding result, and otherwise, entering S3; s3, updating variable node information according to posterior probability information and check node information of the last iteration; calculating a dynamic scale factor, and updating check node information according to the dynamic scale factor and the updated variable node information; and S4, updating the posterior probability information according to the updated check node information to obtain the posterior probability information of the current iteration, and returning to S2. And the decoding performance is improved.

The invention discloses an OTFS-based high-reliability secure transmission method, which comprises the following steps of: sequentially carrying out LDPC (Low Density Parity Check) coding, QAM (Quadrature Amplitude Modulation) mapping, SVD (Singular Value Decomposition) pre-coding, inverse symplectic finite Fourier transform, Hisenberg transform, R-CP (Reverse-CP) addition, D / A (Digital-to-Analog) transform and up-conversion on an information source sequence of a transmitting end to obtain a transmitting sequence, and transmitting the transmitting sequence through a wireless channel; after a receiving end of a legal user obtains a receiving sequence, down-conversion, A / D conversion, R-CP removal, Wigner conversion, symplectic finite Fourier transform, SVD decoding, single-tap equalizer processing, QAM demapping and LDPC decoding are carried out to obtain an information sink sequence. Through a precoding technology based on an OTFS equivalent matrix and an error control coding technology based on LDPC, high-reliability physical layer secure transmission is realized in a high-dynamic communication scene, the total throughput and the spectrum efficiency of a system are improved, the peak-to-average power ratio and the transmission bit error rate of the system are reduced, and meanwhile, overhigh calculation complexity and time-frequency resource overhead are not brought.

The invention discloses a method and device for obtaining log-likelihood ratio information of an LDPC algorithm and a medium, and relates to the technical field of flash memories. The method comprises the following steps: acquiring a to-be-decoded data sequence and an LDPC check matrix; wherein the LDPC check matrix comprises a plurality of candidate row check sequences; performing row check processing according to the data sequence to be decoded and the LDPC check matrix to obtain a row check result; determining a target row verification sequence from the plurality of candidate row verification sequences according to the row verification result; performing sequence superposition processing on the target row verification sequence to obtain a weight sequence; and performing mapping processing according to the data sequence to be decoded, the weight sequence and a preset index mapping table to obtain log-likelihood ratio information, and performing LDPC decoding processing for flash memory error correction according to the data sequence to be decoded and the log-likelihood ratio information. The log-likelihood ratio information of the LDPC decoding algorithm can be quickly obtained, so that the LDPC decoding algorithm is enabled to take both higher decoding speed and stronger decoding capability into account.

The invention relates to an LDPC (Low Density Parity Check) decoder oriented to a CCSDS (Consultative Committee for Space Data System) standard and a decoding method thereof, relates to the technical field of satellite communication and channel coding, and aims to solve the technical problems of insufficient parallelism and low resource utilization rate of a satellite communication LDPC decoder in the prior art. The LDPC decoder for the CCSDS standard comprises a frame input module, a control module, an initial probability storage module, a check node calculation module, a variable node calculation module and a frame output module. The LDPC decoder facing the CCSDS standard and the decoding method thereof are suitable for efficient decoding of long-frame data in satellite communication, dynamic block storage architecture, hybrid iterative decoding algorithm and configurable control module collaborative design, balance of decoding algorithm performance and complexity is achieved through storage design optimization, the algorithm flexibility is improved through a configurable strategy, and the decoding efficiency is improved. And the contradiction between the efficiency and resources of long-frame LDPC decoding in satellite communication is systematically solved.

The invention discloses a multi-user joint decoding method for a cellular-free large-scale MIMO system based on model-driven deep learning, and the method comprises the steps: building an optimization problem of a simulation combination matrix with maximization of the reachable rate of the cellular-free large-scale MIMO system as a target in a simulation part of data decoding; on the basis of a heuristic algorithm, an optimization target is simplified, an optimization problem is divided into a plurality of sub-problems, the single AP simulation precoding matrix optimization problem is solved one by one, and an optimal simulation combination matrix is obtained; a multi-user joint LDPC decoding algorithm is expanded to a cellular-free large-scale MIMO scene, multi-user joint LDPC decoding is realized based on an MIMO-LDPC-Net decoding network, an input layer of the MIMO-LDPC-Net decoding network generates an initial value as an input of a hidden layer, the hidden layer is formed by stacking modules composed of a first sub-layer, a second sub-layer and an MIMO detection layer, and the first sub-layer, the second sub-layer and the MIMO detection layer are stacked. The output layer generates a log-likelihood ratio of the variable node. Experiments show that compared with a traditional algorithm, the heuristic algorithm and the AI auxiliary joint decoding algorithm have a signal-to-noise ratio gain of 1dB.

The invention relates to an adaptive low density parity check (LDPC) decoder architecture. An LDPC decoder architecture is provided for adaptively adjusting an LDPC control input for successfully decoding a corresponding received code block. The architecture supports a machine learning based process that facilitates learning the optimal LDPC control input required for a given channel condition and deployment scenario, such as log-likelihood (LLR) term scaling. This is accomplished by an unused LDPC decoder accelerator collecting posterior decoding metrics as a background process, the function of the accelerator being to process a tagged LLR dataset of different LDPC control input values. This optimal LDPC control input estimate may then be applied to real-time LDPC decoding based on previous learning under UE / channel conditions.

The embodiment of the invention provides an LDPC decoding capability test application method and device, storage equipment, a storage medium and a program product, and relates to the technical field of storage. According to the method, after the LDPC decoding function of the main control chip is started, reading operation is performed on the storage medium, the decoding failure probability corresponding to a plurality of invalid bit numbers is obtained, and the decoding capability performance of the main control chip for different invalid bit number scenes can be reflected. And reading operation is directly performed on the storage medium through the test platform to obtain the data volume ratio corresponding to the plurality of invalid bit numbers, so that the original error distribution characteristics of the storage medium under the condition that decoding correction is not performed can be reflected. And finally, through quantitative comparison and analysis of the original error distribution characteristics of the storage medium and the decoding performance of the main control chip, scientificity and reliability of LDPC decoding capability evaluation of the storage medium with different code rates by different main control chips are ensured, so that a solid technical basis and a clear judgment standard are provided for project decision making.

The present invention provides a method and device for high-speed LDPC decoding of broadband signals with low computing power requirements, relating to the field of radio monitoring. This method addresses the issues of long processing time, high resource consumption, and difficulty in engineering implementation of current LDPC code decoders. The method comprises: buffering data frames and serially reading and processing adjacent codewords in the data frames to be decoded after configuration; determining long codewords and designing control logic timing; and achieving multi-path concurrent processing of long codewords under low computing power requirements through soft switching of parallelism parameters. The method also includes designing a concurrent decoding processing path and iteratively updating variable nodes and check nodes based on an improved NMSA decoding algorithm. After satisfying the iterative stopping strategy, a decoded bit sequence for the long codeword is obtained, forming a decoding result under low computing power requirements. The present invention has the characteristics of low processing latency, low resource consumption, and is suitable for practical use environments. It can effectively improve the decoding processing rate and decoding data throughput of satellite signal monitoring.

Disclosed are a 64-bit LDPC decoding method and device for BeiDou-3 satellite signals. The implementation of each stage's operations is more rigorous and detailed, providing confidence vectors for check node updates and variable node updates, and the required finite field elements for final verification, making the decoding process easier to understand and implement. A permutation process is added before check node updates, a depermutation process is added before variable node updates, and a posteriori confidence calculation is performed before final verification. The posteriori LLR is calculated by adding the LLRs of two non-zero confidence vectors in the same column to the original LLRs and sorting them. The corresponding finite field element of the minimum LLR is the calculation result. The finite field element obtained from the posterior confidence calculation is finite field multiplied with the check matrix for verification.

The present invention discloses a high-speed demodulation method, device and equipment suitable for low-orbit satellites. The demodulation method includes down-converting an intermediate frequency signal to a baseband signal, then decimating and down-sampling the baseband signal and low-pass filtering it, searching for the frame header through an FFT-based capture method, determining the pilot position, and then performing power estimation and channel gain control, followed by fast timing synchronization and carrier synchronization, and finally performing LDPC decoding on the synchronized data. The present invention adopts high-speed parallel processing technology and high-order modulation and demodulation technology, and the information processing capacity can reach more than 1Gbps; it also adopts high-dynamic capture and synchronization technology, which can adapt to the high-speed movement characteristics of low-orbit satellites. The center frequency and channel gain of the present invention are flexibly configurable, and can support a variety of rates and modulation methods, and are particularly suitable for high-speed signal communications in low-orbit satellite communication systems.

The present application discloses a method and apparatus for LDPC decoding using index messages. The present invention discloses a low density parity check (LDPC) decoder, the LDPC decoder comprising a variable node unit (VNU), the VNU comprising a plurality of variable nodes configured to perform a sum. A first message mapper of the LDPC decoder receives a first n1-bit index from a likelihood ratio (LLR) input and maps the first n1-bit index to a first numerical value of the variable nodes input to the VNU. A second message mapper of the LDPC decoder receives a second n2-bit index from a check node unit (CNU) and maps the second n2-bit index to a second numerical value of the variable nodes input to the VNU. The CNU comprises a plurality of check nodes that perform parity check operations. The ranges of the first numerical value and the second numerical value are respectively greater than the ranges represented in n1-bit and n2-bit binary.

An encoding method, a decoding method, and an apparatus, which are applied to support IEEE 802.11ax next-generation WiFi protocols (for example, 802.11be, WiFi 7 or EHT), or IEEE 802.11be next-generation WiFi protocols (for example, 802.11bn, WiFi 8 or UHR), or WiFi AI, or millimeter wave (MMW), or ultra-wideband (UWB), or sensing, etc. The encoding and decoding methods comprise: a first communication apparatus acquiring an information bit sequence, and on the basis of a check matrix, performing LDPC encoding on the information bit sequence, so as to obtain an encoded sequence, and outputting the sequence, wherein the length of the sequence is N1, N1 is n times 1944, and n is an integer greater than or equal to 2; and a second communication apparatus performing LDPC decoding on the basis of the check matrix after obtaining information to be decoded, so as to obtain the information bit sequence. The methods can improve the decoding performance.

The embodiment of the application discloses a kind of LDPC decoding device and electronic equipment applied to chip, it is related to circuit field.The LDPC decoding device of the application includes: demodulation unit, first buffer unit, second buffer unit, LDPC decoder and controller;Wherein, the output of demodulation unit is connected with the input of first buffer unit, the output of first buffer unit is connected with the input of second buffer unit, the output of second buffer unit is connected with LDPC decoding unit;Controller is connected with the control end of first buffer unit and the control end of second buffer unit respectively;First data queue is arranged in first buffer unit, and second data queue is arranged in second buffer unit.The queue buffering mechanism is introduced in the application, the order and integrity of data are guaranteed, decoding requirements are flexibly adapted, and the rate matching problem between the LDPC decoder of rear end and the demodulation unit of front stage is effectively solved by using asynchronous processing mode.

The present invention discloses an LDPC decoding method, device, equipment and computer-readable storage medium, belonging to the field of decoding, and is used for LDPC decoding of data stored in NAND. When performing LDPC encoding and decoding, it is necessary to pad some data with zeros. Considering that during the decoding process, the data at the zero-padding positions in the variable nodes itself has a definite value and relatively high credibility. If a relatively complex decoding algorithm is used to update the prior probability and posterior probability of the zero-padding positions in the variable nodes, the decoding efficiency will inevitably be reduced. Therefore, in the decoding process of this application, a preset optimization update algorithm is used to update the prior probability and posterior probability of the zero-padding positions in the variable nodes. By setting a suitable preset optimization update algorithm, the amount of computation can be greatly reduced. On the one hand, the number of error corrections within a limited number of iterations can be increased, and on the other hand, the working efficiency is improved and the energy consumption is reduced.