93 results about "Ldpc decoding" patented technology

The invention discloses a layered LDPC (Low Density Parity Check Code) decoding method based on syndrome feedback self-adaption, and aims to solve the problem of poor decoding performance caused by fixed correction factors and poor adaptability to different check matrixes and channel conditions in the existing LDPC decoding algorithm. The method comprises the following steps of: firstly, dividing rows of a check matrix into a plurality of independent layers by adopting a hierarchical scheduling architecture so as to accelerate propagation and convergence of decoding information; secondly, in each iteration process of hierarchical decoding, a self-adaptive mechanism based on syndrome feedback is used, and a core offset factor beta in an offset minimum sum algorithm is adjusted in real time; the mechanism intelligently increases or decreases the offset factor by diagnosing the current decoding state (i.e., the number of unsatisfied check equations) to help the decoding process jump out of local optimum and stably converge. A simulation result shows that compared with a traditional offset minimum sum algorithm, the decoding performance is effectively improved and the bit error rate is reduced on the premise that the complexity is not obviously increased, and particularly, the performance gain is obvious in a medium-high signal-to-noise ratio region, and the robustness is higher.

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

The invention discloses a multi-user joint decoding method for a cellular-free large-scale MIMO system based on model-driven deep learning, and the method comprises the steps: building an optimization problem of a simulation combination matrix with maximization of the reachable rate of the cellular-free large-scale MIMO system as a target in a simulation part of data decoding; on the basis of a heuristic algorithm, an optimization target is simplified, an optimization problem is divided into a plurality of sub-problems, the single AP simulation precoding matrix optimization problem is solved one by one, and an optimal simulation combination matrix is obtained; a multi-user joint LDPC decoding algorithm is expanded to a cellular-free large-scale MIMO scene, multi-user joint LDPC decoding is realized based on an MIMO-LDPC-Net decoding network, an input layer of the MIMO-LDPC-Net decoding network generates an initial value as an input of a hidden layer, the hidden layer is formed by stacking modules composed of a first sub-layer, a second sub-layer and an MIMO detection layer, and the first sub-layer, the second sub-layer and the MIMO detection layer are stacked. The output layer generates a log-likelihood ratio of the variable node. Experiments show that compared with a traditional algorithm, the heuristic algorithm and the AI auxiliary joint decoding algorithm have a signal-to-noise ratio gain of 1dB.

The invention relates to an adaptive low density parity check (LDPC) decoder architecture. An LDPC decoder architecture is provided for adaptively adjusting an LDPC control input for successfully decoding a corresponding received code block. The architecture supports a machine learning based process that facilitates learning the optimal LDPC control input required for a given channel condition and deployment scenario, such as log-likelihood (LLR) term scaling. This is accomplished by an unused LDPC decoder accelerator collecting posterior decoding metrics as a background process, the function of the accelerator being to process a tagged LLR dataset of different LDPC control input values. This optimal LDPC control input estimate may then be applied to real-time LDPC decoding based on previous learning under UE / channel conditions.

The embodiment of the application discloses a kind of LDPC decoding device and electronic equipment applied to chip, it is related to circuit field.The LDPC decoding device of the application includes: demodulation unit, first buffer unit, second buffer unit, LDPC decoder and controller;Wherein, the output of demodulation unit is connected with the input of first buffer unit, the output of first buffer unit is connected with the input of second buffer unit, the output of second buffer unit is connected with LDPC decoding unit;Controller is connected with the control end of first buffer unit and the control end of second buffer unit respectively;First data queue is arranged in first buffer unit, and second data queue is arranged in second buffer unit.The queue buffering mechanism is introduced in the application, the order and integrity of data are guaranteed, decoding requirements are flexibly adapted, and the rate matching problem between the LDPC decoder of rear end and the demodulation unit of front stage is effectively solved by using asynchronous processing mode.

A method for generating a parity check matrix, and a communication apparatus. The method comprises: acquiring a base matrix, the base matrix comprising a first matrix, the first matrix being a matrix consisting of the first column to the tenth column and the first row to the fourth row of the base matrix, elements comprised in the first column of the base matrix being all non-zero elements, and the first column being a punctured column; and, on the basis of the base matrix, obtaining a parity check matrix of a non-binary low-density parity check (LDPC) code, the parity check matrix being used for LDPC coding or LDPC decoding. The elements comprised in the first column of the base matrix are all non-zero elements, and the first column is a punctured column, such that the code rate of the LDPC code corresponding to the base matrix provided in the method can reach 2 / 3. Compared with the prior art, the method improves the code rate of non-binary LDPC codes, thereby improving coding and decoding performance of non-binary LDPC codes.

The invention provides a greedy confidence method and device applied to low-density parity check codes, and the method comprises the steps: initializing a decoder, and obtaining a variable node and a check node after initialization processing; transmitting a message obtained based on the received signal to a check node through the variable node; a greedy optimization strategy is adopted to carry out partial node updating and iteration in the message transmission process of the variable nodes and the check nodes, and an optimal analysis result is obtained; and obtaining decoding information according to the optimal analysis result, and outputting a decoding result for the decoding information. According to the invention, the greedy algorithm is applied to the BP algorithm, the BP algorithm is optimized, messages of part of variable nodes and check nodes are updated according to a greedy optimization strategy, the complexity of the BP algorithm is reduced, the iteration time is effectively reduced, the decoding time delay is reduced, and the LDPC decoding efficiency is improved.

The invention provides an LDPC decoding method, a program product, an electronic device and a storage medium, and is applied to the technical field of communication, and the LDPC decoding method comprises the steps: obtaining an expansion factor corresponding to LDPC decoding and to-be-decoded data; determining the degree of parallelism corresponding to LDPC decoding according to the expansion factor; decoding the to-be-decoded data according to the expansion factor, the parallelism degree and the check matrix to obtain target decoded data corresponding to the plurality of clock cycles; and calculating judgment output according to the target decoding data corresponding to the plurality of clock periods respectively. The degree of parallelism is automatically determined according to the expansion factor, and the to-be-decoded data is decoded in combination with the expansion factor, the degree of parallelism and the check matrix, so that expansion factors of different sizes can be dynamically adapted. When small expansion factor data is processed, hardware resources are fully utilized, and the decoding speed is increased; and when large expansion factor data is processed, hardware implementation complexity increase and power consumption overload are avoided, so that the resource utilization rate and the processing speed are improved.

The present application provides a communication method and apparatus. In the method, a communication apparatus performs first-stage lifting on a first matrix (for example, a base matrix) to obtain a second matrix, which is used for obtaining a check matrix, and then performs LDPC encoding or LDPC decoding by means of the obtained check matrix. By means of the above implementation, it is beneficial to increasing the scale of the check matrix, thereby optimizing the decoding threshold.

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Decoding low-density parity check (LDPC) codes in a communication system includes identifying a first set of indices of variable nodes (VNs) having log-likelihood ratios (LLRs) greater than a threshold. A second set of indices that includes the first set of indices, indices of shortening VNs, and indices of single parity check (SPC) VNs is created. LDPC decoding proceeds by iteratively updating check-to-variable (C2V) messages and variable-to-check (V2C) messages, with updates for a VN being skipped when an index of the respective VN belongs to the second set of indices.

The invention relates to the technical field of decoding, and discloses a three-code-in-one interpretation method and device of a probability domain based on a storage and calculation integrated device, which can configure a three-code-in-one decoding array comprising an LDPC (Low Density Parity Check) decoding array, a Polar decoding array and a Turbo decoding array on the storage and calculation integrated device based on a target probability graph model corresponding to three error correction codes to be interpreted. According to a probability domain operation mode, determining a state value initial probability of each variable node in each target probability graph model, and using the state value initial probability of each variable node in each target probability graph model and the three-code-in-one decoding array to perform unified interpretation on three to-be-interpreted error correction codes so as to obtain an error correction code interpretation result; according to the invention, unified interpretation of the to-be-interpreted LDPC code, the Polar code and the Turbo code is realized, and unified decoding power consumption of the to-be-interpreted LDPC code, the Polar code and the Turbo code can be effectively reduced.

The invention relates to the technical field of communication, in particular to a coding method and device and a decoding method and device. The method can be applied to the IEEE 802.11 ax standard, the 802.11 be standard, the 802.11 bn standard and the like and other standards of the IEEE 802.11 series, such as the 802.15 standard, the 802.11 bf standard, the IMMW standard or the star flash standard and the like. The method comprises the following steps: a first site obtains information bits, performs LDPC coding on the information bits based on a check matrix, obtains coded bits, and outputs a sequence. And after obtaining the to-be-decoded information, the second station performs LDPC decoding in combination with the check matrix to obtain information bits. The code length corresponding to the check matrix is 7776, the code rate corresponding to the check matrix is 3 / 4, and the expansion factor of the check matrix is 162. The check matrix can be better matched with a longer code length, and the coding and decoding performance is improved.

The invention discloses a satellite-borne SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) program on-orbit reconstruction system, which comprises a data processing unit, a JFMRS01RH unit, an external storage unit and a target FPGA, and is characterized in that the data processing unit comprises a satellite-ground data processing module used for receiving an intermediate frequency signal from a satellite and carrying out demodulation, AOS (Advanced Orthogonal System) data frame recovery, data descrambling and LDPC (Low Density Parity Check) decoding; the on-satellite data processing module is used for carrying out AOS data frame analysis, uploading data packet recombination, verification and secondary packaging; the JFMRS01RH unit is used for receiving the uploading data packet which is secondarily packaged by the data processing unit, performing state monitoring and feeding back to the data processing unit, and is also used for task scheduling management; the external storage unit is used for caching the recombined uploading data packet and is also used for storing an uploading file to be loaded to the target FPGA; and the target FPGA is used for providing logic control and algorithm implementation for the load of the on-orbit satellite.

The application discloses a model-driven neural network-based offset min-sum LDPC code decoding algorithm and relates to an offset min-sum LDPC code decoding algorithm. The application is designed to solve the problems of the traditional LDPC decoding algorithm in convergence speed, calculation complexity, flexibility and the like. The application comprises the following steps: 1, a model-driven offset min-sum algorithm network model is constructed, wherein the network model comprises an input layer, a check node layer, a variable node layer and an output layer; 2, the input layer is used to calculate the received channel LLR by using a received signal y to perform initialization; 3, the check node layer is used to calculate the CN-to-VN LLR value; 4, the variable node layer is used to calculate the VN-to-CN LLR value; and 5, the output layer is used to calculate a final decoding output. The application belongs to the technical field of decoding.

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

The present application relates to the technical field of communications, and particularly relates to a coding method and apparatus, and a decoding method and apparatus. The present application can be applied to the IEEE 802.11ax standard, the 802.11be standard, the 802.11bn standard, and other standards of the IEEE 802.11 series, such as the 802.15 standard, the 802.11bf standard, the IMMW standard or the SparkLink standard. The method comprises: a first station acquiring information bits, performing LDPC coding on the information bits on the basis of a parity-check matrix, so as to obtain the coded bits, and outputting a sequence; and after obtaining information to be decoded, a second station performing LDPC decoding in combination with the parity-check matrix, so as to obtain information bits, wherein the code length corresponding to the parity-check matrix is 7776, the code rate corresponding to the parity-check matrix is 5 / 6, and the expansion factor of the parity-check matrix is 162. The parity-check matrix can better match a longer code length, thereby improving the coding and decoding performance.

The application provides a method for sharing LDPC hard decoding and soft decoding engines of a solid state disk, comprising the following steps: configuring N hard decoding nodes and L soft decoding nodes for a solid state disk comprising N channels; the N channels share the N hard decoding nodes and L soft decoding nodes; and the N hard decoding nodes and L soft decoding nodes share M decoders. N, L and M are all natural numbers greater than or equal to 1, and M < N. The application also provides a system for sharing LDPC hard decoding and soft decoding engines of a solid state disk. Through the above method and system, LDPC can be fully utilized in the working cycle of the SSD, and has a relatively ideal resource occupancy rate.

The application relates to the technical field of data storage, in particular to a data checking method and system based on a solid state disk master control chip, which solves the technical problem that in the prior art, LDPC decoding may occur in a NAND flash deep aging scene, leading to silent data damage. The method comprises the following steps: obtaining error-corrected data obtained after error correction decoding when a solid state disk reads data, and determining the current environmental drift direction of a flash memory unit in the solid state disk; based on a preset mapping relationship, determining the physical voltage change direction corresponding to the logical flip type of a target bit in the error-corrected data; based on the environmental drift direction and the physical voltage change direction of the target bit, performing risk assessment on the error-corrected data to determine whether the error-corrected data is untrustworthy data with a risk of silent data damage.

The invention relates to an LDPC decoding performance evaluation system and method based on a heterogeneous platform, and belongs to the field of signal testing. According to the system, a processor system PS end and a programmable logic PL end are arranged on a ZYNQ platform, and interconnection of modules at the two ends is achieved through an AXI bus. The PL end comprises a random information sequence generation module, a coding module, a noise generation module, a modulation and demodulation module, a dual-port synchronous buffer FIFO module, a decoder to be tested and an error rate calculation module, and is responsible for random information sequence generation, coding, noise generation, modulation and demodulation, data caching, decoding and error rate calculation; the PS end comprises a parameter configuration module and a data visualization module and is responsible for parameter configuration and data visualization. According to the method, code word information such as simulation code length and code rate can be flexibly configured, the coding and decoding performance of various code rates and code length combinations can be simulated, the adaptability and practicability of the system are greatly improved, and diversified requirements under different application scenes are met.

The invention provides an LDPC (Low Density Parity Check) decoding method and device, equipment and a storage medium. The method comprises the following steps: dividing a check matrix into multiple layers according to rows; combining the plurality of layers to obtain a plurality of layer groups; wherein each layer group is numbered in sequence; and based on each layer group, decoding according to an inverted sequence. According to the method provided by the invention, after the rows are layered, the layers are grouped, and decoding is carried out according to an inverted sequence based on each layer group, so that processing time delay caused by layer jump can be avoided, and implementation of parallel pipeline is facilitated.

The application discloses an LDPC decoding method and system with a dynamic clock-off function, and relates to the technical field of communication. The method comprises the following steps: counting the number of current code words to be decoded; counting the actual iteration number in the decoding process, and calculating the average iteration number; determining the number of decoding cores that need to be started with a clock signal according to the number of current code words to be decoded, the average iteration number and system performance constraints; and dynamically controlling the on-off of the clock signal of the decoding core based on the number of decoding cores that need to be started with the clock signal. The application can dynamically perceive the load and channel quality, accurately match the required decoding resources, and maximally reduce the power consumption of idle resources on the premise of guaranteeing the system performance constraints, and is suitable for high-bandwidth and low-power communication scenes such as 50G PON.

The invention discloses a QC-LDPC decoding FPGA pipeline implementation method and device. The method comprises the steps that a first lookup table, a second lookup table, a first storage array and a second storage array are constructed on an FPGA; receiving demodulated code word soft information, calculating the log-likelihood ratio of each bit, and writing the log-likelihood ratio into a first storage array; decoding iteration is executed according to a row traversal mode after parameter initialization, and an intermediate message and a log-likelihood ratio are updated; dividing the operation of each row of verification equations into a plurality of serial assembly lines; after all check nodes finish one-time pipeline processing, if the current iteration number is smaller than the maximum iteration number and a check equation which does not meet the parity check constraint exists, iteration is returned, and otherwise, decoding is ended; and performing hard decision on the symbol of the final log-likelihood ratio to obtain a decoding bit sequence, and outputting the decoding bit sequence. According to the invention, the occupation of FPGA storage resources is reduced, the compromise between performance and complexity is realized, the decoding throughput rate is improved, and the time delay is reduced.

The application provides a kind of multinary LDPC decoding method based on node reliability subset division criterion, comprising: step 1: initialization of channel information value;Step 2: decoding iteration process, if the current iteration number reaches the maximum iteration number or decoding check succeeds, exit the iteration process, otherwise enter step 3;Step 3: information update is carried out to check node, and the division mechanism is triggered after the third iteration;Step 4: calculate the information value of the check node to the check node, and the message truncation is carried out to the check node outside information transmitted by the check node;Step 5: calculate the information value of the check node to the variable node inverse substitution;Step 6: the calculation and decision of variable node full information;Step 7: check the decision result, if it is satisfied, decoding is ended, otherwise enter step 8;Step 8: return to the decoding iteration process of step 2, while the information of last round iteration is transmitted to the check node to be updated, for the reasonable allocation of check node.

The application discloses a shortened LDPC decoding method and system with high coding gain, and the method comprises the following steps: initializing channel reception log-likelihood ratio information and extrinsic information transmitted from check nodes to variable nodes; taking the initialized channel reception log-likelihood ratio information and the extrinsic information transmitted from the check nodes to the variable nodes as first iteration input, performing iteration decoding calculation to obtain a code word decision result; and outputting the code word decision result as a decoding result. The application improves the accuracy of decoding and the convergence speed of decoding.

The application relates to an iterative channel estimation method of a constant envelope modulation system based on DBD decomposition, which comprises the following steps: S1, DBD decomposition is carried out on a constant envelope modulation signal to obtain a decomposition form of the constant envelope modulation signal, and then sampling is carried out on a received signal to obtain a sampling result; S2, an initial estimation value of a channel parameter is obtained; S3, Viterbi demodulation and LDPC decoding are carried out to obtain bit information; S4, a reconstruction signal is generated; S5, the channel parameter is re-estimated to obtain a new channel estimation result; and S6, the new channel estimation result is taken as a current channel estimation result, and S3-S5 are repeated. Compared with the prior art, the application has the advantages of effectively reducing time complexity and space complexity, improving channel estimation performance and the like.

The invention discloses an LDPC (Low Density Parity Check) decoding acceleration method and device based on an RISC-V (Reduced Initiation Standard-Value) custom extension instruction. The method comprises the following steps: extracting an LDPC code from a software radio platform OAI; decoding performance analysis is carried out on the extracted low density parity check code LDPC, and a performance bottleneck module in the LDPC decoding process is determined; designing an RISC-V custom extension instruction for the performance bottleneck module determined in the step 2 based on the open characteristic of an RISC-V instruction set architecture; and performing optimization effect verification and evaluation on the RISC-V custom extension instruction designed in the step 3 by adopting a simulation platform. According to the invention, the memory access and branch processing in the LDPC decoding process are optimized, and the memory access efficiency is improved.

The application discloses a high-performance low-complexity LDPC decoding method for satellite communication and belongs to the field of digital signal processing. Based on the low-density parity-check (LDPC) code in the 5G standard, the received channel information is iteratively decoded. The implementation method of the application is as follows: the amplitude of the current check node information is used to dynamically set the erasure range when updating the variable node; the amplitude of the check node information gradually increases with the increase of the iteration number, and the entire iteration process is divided into two parts, and different parameters are used to set the erasure range. When the decoding result is correct or the maximum iteration number is reached, the decoding result is output. The application increases the reliability of the variable node information, prevents reliable variable information from being erased and prevents the propagation of unreliable variable node information through the above two points, and has excellent decoding performance. There is no nonlinear operation in the log-likelihood ratio belief propagation algorithm (LLR-BPA) in the decoding algorithm of the application, and the decoding performance is high and the decoding complexity is low.

The invention discloses a high-bit-rate multi-index continuous phase modulation signal receiver which comprises a frequency conversion and conditioning module, an AD daughter card module, a frequency synthesis module, an FPGA chip 1 and an FPGA chip 2. Wherein the frequency conversion and conditioning module is configured to complete down-conversion and AGC (Automatic Gain Control) of an S-band radio frequency signal and output an S-band intermediate frequency signal; the AD daughter card module is configured to convert a received S-band intermediate frequency signal into an intermediate frequency digital signal; the frequency synthesis module is configured to complete system work clock generation; the FPGA chip 1 is configured to complete Doppler frequency capture of a received intermediate frequency digital signal, send the captured signal to the FPGA chip 2, receive a demodulation information sequence fed back by the FPGA chip 2 to complete LDPC decoding, descrambling and frame synchronization of corresponding data, and output telemetry data; the FPGA chip 2 is configured to perform carrier phase tracking, modulation index synchronization, timing synchronization and sequence detection on received data.

The invention provides a multi-LDPC code word joint verification method based on partial extra verification, belongs to the field of flash memory error correction coding, and aims to solve the problems that the read-write efficiency is reduced due to the fact that 16KB LDPC code words are not matched with common flash memory pages in size, and the hardware overhead of a 16KB codec is too high. According to the method, the error correction capability close to 16KB LDPC is achieved by improving 4KB LDPC, and the error correction efficiency of the 16KB codec is improved. Bits in a specific proportion are selected from each 4KB code word to perform pairwise parity check, four 4KB LDPC code words are associated, generated additional check bits are stored in respective flash memory pages and serve as information codes to participate in LDPC coding and decoding, when data are read, LDPC decoding is performed respectively, if decoding fails, part of bits are recovered by the aid of correctly-solved code words and by the aid of additional check, and data are read. According to the flash memory error correction circuit designed based on the method, only a 4KB LDPC codec and a single-bit parity check circuit are needed, the performance of the flash memory error correction circuit can be close to that of 16KB LDPC, and the balance between the error correction performance and hardware overhead is achieved.