58 results about "Ldpc decoding" patented technology

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

A method for generating a parity check matrix, and a communication apparatus. The method comprises: acquiring a base matrix, the base matrix comprising a first matrix, the first matrix being a matrix consisting of the first column to the tenth column and the first row to the fourth row of the base matrix, elements comprised in the first column of the base matrix being all non-zero elements, and the first column being a punctured column; and, on the basis of the base matrix, obtaining a parity check matrix of a non-binary low-density parity check (LDPC) code, the parity check matrix being used for LDPC coding or LDPC decoding. The elements comprised in the first column of the base matrix are all non-zero elements, and the first column is a punctured column, such that the code rate of the LDPC code corresponding to the base matrix provided in the method can reach 2 / 3. Compared with the prior art, the method improves the code rate of non-binary LDPC codes, thereby improving coding and decoding performance of non-binary LDPC codes.

The invention provides a greedy confidence method and device applied to low-density parity check codes, and the method comprises the steps: initializing a decoder, and obtaining a variable node and a check node after initialization processing; transmitting a message obtained based on the received signal to a check node through the variable node; a greedy optimization strategy is adopted to carry out partial node updating and iteration in the message transmission process of the variable nodes and the check nodes, and an optimal analysis result is obtained; and obtaining decoding information according to the optimal analysis result, and outputting a decoding result for the decoding information. According to the invention, the greedy algorithm is applied to the BP algorithm, the BP algorithm is optimized, messages of part of variable nodes and check nodes are updated according to a greedy optimization strategy, the complexity of the BP algorithm is reduced, the iteration time is effectively reduced, the decoding time delay is reduced, and the LDPC decoding efficiency is improved.

The present application provides a communication method and apparatus. In the method, a communication apparatus performs first-stage lifting on a first matrix (for example, a base matrix) to obtain a second matrix, which is used for obtaining a check matrix, and then performs LDPC encoding or LDPC decoding by means of the obtained check matrix. By means of the above implementation, it is beneficial to increasing the scale of the check matrix, thereby optimizing the decoding threshold.

The invention relates to the technical field of communication, in particular to a coding method and device and a decoding method and device. The method can be applied to the IEEE 802.11 ax standard, the 802.11 be standard, the 802.11 bn standard and the like and other standards of the IEEE 802.11 series, such as the 802.15 standard, the 802.11 bf standard, the IMMW standard or the star flash standard and the like. The method comprises the following steps: a first site obtains information bits, performs LDPC coding on the information bits based on a check matrix, obtains coded bits, and outputs a sequence. And after obtaining the to-be-decoded information, the second station performs LDPC decoding in combination with the check matrix to obtain information bits. The code length corresponding to the check matrix is 7776, the code rate corresponding to the check matrix is 3 / 4, and the expansion factor of the check matrix is 162. The check matrix can be better matched with a longer code length, and the coding and decoding performance is improved.

The invention discloses a satellite-borne SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) program on-orbit reconstruction system, which comprises a data processing unit, a JFMRS01RH unit, an external storage unit and a target FPGA, and is characterized in that the data processing unit comprises a satellite-ground data processing module used for receiving an intermediate frequency signal from a satellite and carrying out demodulation, AOS (Advanced Orthogonal System) data frame recovery, data descrambling and LDPC (Low Density Parity Check) decoding; the on-satellite data processing module is used for carrying out AOS data frame analysis, uploading data packet recombination, verification and secondary packaging; the JFMRS01RH unit is used for receiving the uploading data packet which is secondarily packaged by the data processing unit, performing state monitoring and feeding back to the data processing unit, and is also used for task scheduling management; the external storage unit is used for caching the recombined uploading data packet and is also used for storing an uploading file to be loaded to the target FPGA; and the target FPGA is used for providing logic control and algorithm implementation for the load of the on-orbit satellite.

The application discloses a model-driven neural network-based offset min-sum LDPC code decoding algorithm and relates to an offset min-sum LDPC code decoding algorithm. The application is designed to solve the problems of the traditional LDPC decoding algorithm in convergence speed, calculation complexity, flexibility and the like. The application comprises the following steps: 1, a model-driven offset min-sum algorithm network model is constructed, wherein the network model comprises an input layer, a check node layer, a variable node layer and an output layer; 2, the input layer is used to calculate the received channel LLR by using a received signal y to perform initialization; 3, the check node layer is used to calculate the CN-to-VN LLR value; 4, the variable node layer is used to calculate the VN-to-CN LLR value; and 5, the output layer is used to calculate a final decoding output. The application belongs to the technical field of decoding.

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

The present application relates to the technical field of communications, and particularly relates to a coding method and apparatus, and a decoding method and apparatus. The present application can be applied to the IEEE 802.11ax standard, the 802.11be standard, the 802.11bn standard, and other standards of the IEEE 802.11 series, such as the 802.15 standard, the 802.11bf standard, the IMMW standard or the SparkLink standard. The method comprises: a first station acquiring information bits, performing LDPC coding on the information bits on the basis of a parity-check matrix, so as to obtain the coded bits, and outputting a sequence; and after obtaining information to be decoded, a second station performing LDPC decoding in combination with the parity-check matrix, so as to obtain information bits, wherein the code length corresponding to the parity-check matrix is 7776, the code rate corresponding to the parity-check matrix is 5 / 6, and the expansion factor of the parity-check matrix is 162. The parity-check matrix can better match a longer code length, thereby improving the coding and decoding performance.

The application relates to the technical field of data storage, in particular to a data checking method and system based on a solid state disk master control chip, which solves the technical problem that in the prior art, LDPC decoding may occur in a NAND flash deep aging scene, leading to silent data damage. The method comprises the following steps: obtaining error-corrected data obtained after error correction decoding when a solid state disk reads data, and determining the current environmental drift direction of a flash memory unit in the solid state disk; based on a preset mapping relationship, determining the physical voltage change direction corresponding to the logical flip type of a target bit in the error-corrected data; based on the environmental drift direction and the physical voltage change direction of the target bit, performing risk assessment on the error-corrected data to determine whether the error-corrected data is untrustworthy data with a risk of silent data damage.

The application discloses an LDPC decoding method and system with a dynamic clock-off function, and relates to the technical field of communication. The method comprises the following steps: counting the number of current code words to be decoded; counting the actual iteration number in the decoding process, and calculating the average iteration number; determining the number of decoding cores that need to be started with a clock signal according to the number of current code words to be decoded, the average iteration number and system performance constraints; and dynamically controlling the on-off of the clock signal of the decoding core based on the number of decoding cores that need to be started with the clock signal. The application can dynamically perceive the load and channel quality, accurately match the required decoding resources, and maximally reduce the power consumption of idle resources on the premise of guaranteeing the system performance constraints, and is suitable for high-bandwidth and low-power communication scenes such as 50G PON.

The invention discloses a QC-LDPC decoding FPGA pipeline implementation method and device. The method comprises the steps that a first lookup table, a second lookup table, a first storage array and a second storage array are constructed on an FPGA; receiving demodulated code word soft information, calculating the log-likelihood ratio of each bit, and writing the log-likelihood ratio into a first storage array; decoding iteration is executed according to a row traversal mode after parameter initialization, and an intermediate message and a log-likelihood ratio are updated; dividing the operation of each row of verification equations into a plurality of serial assembly lines; after all check nodes finish one-time pipeline processing, if the current iteration number is smaller than the maximum iteration number and a check equation which does not meet the parity check constraint exists, iteration is returned, and otherwise, decoding is ended; and performing hard decision on the symbol of the final log-likelihood ratio to obtain a decoding bit sequence, and outputting the decoding bit sequence. According to the invention, the occupation of FPGA storage resources is reduced, the compromise between performance and complexity is realized, the decoding throughput rate is improved, and the time delay is reduced.

The application provides a kind of multinary LDPC decoding method based on node reliability subset division criterion, comprising: step 1: initialization of channel information value;Step 2: decoding iteration process, if the current iteration number reaches the maximum iteration number or decoding check succeeds, exit the iteration process, otherwise enter step 3;Step 3: information update is carried out to check node, and the division mechanism is triggered after the third iteration;Step 4: calculate the information value of the check node to the check node, and the message truncation is carried out to the check node outside information transmitted by the check node;Step 5: calculate the information value of the check node to the variable node inverse substitution;Step 6: the calculation and decision of variable node full information;Step 7: check the decision result, if it is satisfied, decoding is ended, otherwise enter step 8;Step 8: return to the decoding iteration process of step 2, while the information of last round iteration is transmitted to the check node to be updated, for the reasonable allocation of check node.

The application discloses a shortened LDPC decoding method and system with high coding gain, and the method comprises the following steps: initializing channel reception log-likelihood ratio information and extrinsic information transmitted from check nodes to variable nodes; taking the initialized channel reception log-likelihood ratio information and the extrinsic information transmitted from the check nodes to the variable nodes as first iteration input, performing iteration decoding calculation to obtain a code word decision result; and outputting the code word decision result as a decoding result. The application improves the accuracy of decoding and the convergence speed of decoding.

The application relates to an iterative channel estimation method of a constant envelope modulation system based on DBD decomposition, which comprises the following steps: S1, DBD decomposition is carried out on a constant envelope modulation signal to obtain a decomposition form of the constant envelope modulation signal, and then sampling is carried out on a received signal to obtain a sampling result; S2, an initial estimation value of a channel parameter is obtained; S3, Viterbi demodulation and LDPC decoding are carried out to obtain bit information; S4, a reconstruction signal is generated; S5, the channel parameter is re-estimated to obtain a new channel estimation result; and S6, the new channel estimation result is taken as a current channel estimation result, and S3-S5 are repeated. Compared with the prior art, the application has the advantages of effectively reducing time complexity and space complexity, improving channel estimation performance and the like.

The invention discloses a high-bit-rate multi-index continuous phase modulation signal receiver which comprises a frequency conversion and conditioning module, an AD daughter card module, a frequency synthesis module, an FPGA chip 1 and an FPGA chip 2. Wherein the frequency conversion and conditioning module is configured to complete down-conversion and AGC (Automatic Gain Control) of an S-band radio frequency signal and output an S-band intermediate frequency signal; the AD daughter card module is configured to convert a received S-band intermediate frequency signal into an intermediate frequency digital signal; the frequency synthesis module is configured to complete system work clock generation; the FPGA chip 1 is configured to complete Doppler frequency capture of a received intermediate frequency digital signal, send the captured signal to the FPGA chip 2, receive a demodulation information sequence fed back by the FPGA chip 2 to complete LDPC decoding, descrambling and frame synchronization of corresponding data, and output telemetry data; the FPGA chip 2 is configured to perform carrier phase tracking, modulation index synchronization, timing synchronization and sequence detection on received data.

The invention provides a multi-LDPC code word joint verification method based on partial extra verification, belongs to the field of flash memory error correction coding, and aims to solve the problems that the read-write efficiency is reduced due to the fact that 16KB LDPC code words are not matched with common flash memory pages in size, and the hardware overhead of a 16KB codec is too high. According to the method, the error correction capability close to 16KB LDPC is achieved by improving 4KB LDPC, and the error correction efficiency of the 16KB codec is improved. Bits in a specific proportion are selected from each 4KB code word to perform pairwise parity check, four 4KB LDPC code words are associated, generated additional check bits are stored in respective flash memory pages and serve as information codes to participate in LDPC coding and decoding, when data are read, LDPC decoding is performed respectively, if decoding fails, part of bits are recovered by the aid of correctly-solved code words and by the aid of additional check, and data are read. According to the flash memory error correction circuit designed based on the method, only a 4KB LDPC codec and a single-bit parity check circuit are needed, the performance of the flash memory error correction circuit can be close to that of 16KB LDPC, and the balance between the error correction performance and hardware overhead is achieved.

The invention discloses a burst data transmission method and system based on Hadamard-LDPC coding, and belongs to the technical field of wireless communication, the burst data transmission system comprises a transmitting subsystem and a receiving subsystem, the transmitting subsystem comprises a to-be-transmitted data cache module, a Hadamard-LDPC coding module, a framing module, a modulation module and an up-conversion / power amplification module; the receiving subsystem comprises a low noise amplification / down conversion module, a timing synchronization module, a carrier synchronization module, a demodulation module and a Hadamard-LDPC decoding module. The method can be used for wireless communication data transmission in a low signal-to-noise ratio environment so as to improve the transmission reliability.

The application discloses a multi-element LDPC decoding method based on a dynamic threshold cutting strategy, and is used for solving the problem of high complexity of a multi-element LDPC decoding algorithm. The method provided by the application introduces a dynamic threshold cutting strategy based on the reliability distribution characteristics of an information vector. The strategy dynamically selects a cutting threshold value by using the difference between the maximum value and the second maximum value of the reliability. If the difference reaches a preset difference parameter, the larger threshold value is selected, thereby reducing the finite field elements participating in the operation. If the difference does not reach the preset difference parameter, the smaller threshold value is selected, thereby relatively conservatively increasing more components. In the iteration process, information screening is carried out according to the threshold value, so that the number of states and the number of edges participating in the operation on a trellis diagram are less. The application can obtain lower average decoding complexity without performance loss.

An LDPC decoder includes a storage unit and one or more computing engine. The storage unit stores an LDPC matrix. The computing engine performs an LDPC decoding algorithm to estimate a decoding result for a codeword based on the LDPC matrix. The computing engine includes a minimum value searching unit to output a minimum value searching result based on a plurality of input values when the LDPC decoding algorithm performs a minimum value searching operation.

The application provides a storage addressing method suitable for an LDPC decoder, comprising: allocating a RAM array; storing initial channel information in the RAM array by means of bit splicing; calculating a starting reading address and a starting offset address of the RAM in the RAM array and saving; generating a reading address and an offset address of the RAM according to the starting reading address and the starting offset address; reading information in the RAM according to the reading address of the RAM, and sending the information to a check node updating unit or a variable node updating unit for processing after data bit sequence adjustment according to the offset address; and writing information processed by the check node updating unit or the variable node updating unit into corresponding RAMs in sequence. Through bit splicing storage, complicated reading and simple writing, the decoder can avoid address access conflict problems when completing LDPC decoding, and can achieve parallel high-speed decoding efficiency while realizing low operation complexity.

Neural Normalized MinSum (N-NMS) decoding for improving frame error rate (FER) performance on linear block codes over conventional normalized MinSum (NMS). Dynamic multiplicative weights are assigned to each check-to-variable message in each iteration to efficiently provide training parameters of N-NMS that support N-NMS for longer block lengths. Embodiment are described for neural two-dimensional normalized MinSum (N-2D-NMS) decoders requiring fewer training parameters. The N-2D-NMS approaches for example use the same weight for edges with the same check and / or variable node degree. Simulation results indicate that that this LDPC decoding performs similarly to previous techniques while substantially reducing the amount of training necessary.

Various aspects of this disclosure relate generally to wireless communication. In some aspects, a wireless communication device can receive transmissions associated with one or more bits. The wireless communication device can decode the transmissions using an average of one or more confidence level values ​​associated with the one or more bits relative to the number of one or more confidence level values ​​and an offset at least in part based on the number of one or more confidence level values. Numerous other aspects are described.

The application discloses a data checking method and device, equipment and medium, and relates to the technical field of distributed storage. The data checking method is applied to a distributed storage system and includes the following steps: obtaining original data written into a disk through a write operation, and encoding the original data based on LDPC to obtain encoded data; generating at least one checking copy and a plurality of normal copies according to the encoded data; when it is determined that the encoded data in the plurality of normal copies is damaged through a read operation, performing LDPC decoding on the checking copy by calling the read operation to obtain the original data, and repairing the encoded data in the plurality of normal copies according to the original data. Since the LDPC decoding is introduced, when there is only one checking copy, the damaged original data can be restored through the checking copy, and thus, the error data can be restored in the case that the number of normal copies is small and the normal copies are damaged.

The present application relates to the technical field of communications, and in particular to an encoding method, a decoding method, and an apparatus. The present application can be applied to the IEEE 802.11ax standard, the 802.11be standard, and the 802.11bn standard, as well as other standards of the IEEE 802.11 series, such as the 802.15 standard, the 802.11bf standard, the IMMW standard, or the SparkLink standard. The method comprises: a first station acquires information bits, performs LDPC encoding on the information bits on the basis of a check matrix, obtains encoded bits, and outputs a sequence. After obtaining information to be decoded, a second station performs LDPC decoding in combination with the check matrix to obtain information bits. A code length corresponding to the check matrix is 7776, a code rate corresponding to the check matrix is 2 / 3, and a spreading factor of the check matrix is 162. The check matrix can better match a longer code length, thereby improving encoding and decoding performance.

Decoding circuit (1) comprising: an input (14) for receiving raw bit values ​​of a forward error correction (FEC) block; a low-density parity check (LDPC) decoder (3) coupled to the input (14), wherein the LDPC decoder (3) performs a failed decoding operation on the raw bit values ​​of the FEC block and outputs a failed decoding syndrome (13) and a failed decoding output block (12); a trap detection comparator (4) coupled to the LDPC decoder (3), wherein the trap detection comparator (4) determines whether the FEC block is a trapped block by the number of failing check nodes indicated by the syndrome (13). are compared with an error threshold, whereby the FEC block is determined to be a trapped block if the number of failing check nodes specified by the syndrome (13)is less than the error threshold; and a trap control (2) coupled to the input (14), the trap detection comparator (4), and the LDPC decoder (3), wherein, when the FEC block is determined to be a trapped block, the trap control (2) performs trapped-block decoding iterations using the LDPC decoder (3) until the decoding operation is successful or until a predetermined number of trapped-block decoding iterations have been performed, wherein at each trapped-block decoding iteration, the trap control (2) does the following: generate an updated log likelihood ratio (LLR) map using weak bit values ​​corresponding to each bit in the FEC block and stochastic probability values ​​corresponding to each bit in the FEC block; provide to the LDPC decoder (3),the updated LLR card and either the raw bit values ​​of the FEC block or a failed decode output block from a previous failed decode operation, and sending a signal to the LDPC decoder (3) to perform a decode operation, wherein in response to the signal, the LDPC decoder (3) uses the updated LLR card to perform a decode operation on the respective bits of the raw bit values ​​of the FEC block or the failed decode output block from the previous failed decode operation, wherein, if it is not determined that the FEC block is a trapped block, the decode circuit outputs an error signal at an output of the decode circuit, and if the decode operation is successful in generating a codeword, the decode circuit outputs the codeword.

The invention provides a coding method and a decoding method based on LDPC (Low Density Parity Check). In the method, the communication device obtains a first matrix, and partial rows of the first matrix are obtained by replacing partial rows of a second matrix with a third matrix; and the communication device performs LDPC coding on a bit sequence to be coded based on the first matrix to obtain a coded sequence. According to the coding method and the decoding method provided by the invention, a part of rows of the LDPC check matrix can be replaced by matrixes of other types of codes, so that the storage overhead of the LDPC check matrix for LDPC coding or LDPC decoding can be saved.

The present application provides an LDPC-based encoding method and an LDPC-based decoding method. In the encoding method, a communication apparatus acquires a first matrix, some rows of the first matrix being obtained by replacing some rows of a second matrix with third matrices; and, on the basis of the first matrix, the communication apparatus performs LDPC encoding on a bit sequence to be encoded, so as to obtain an encoded sequence. According to the encoding method and the decoding method provided in the present application, some rows of an LDPC check matrix can be replaced with matrices of another type of code, thereby reducing storage overhead of the LDPC check matrix used for LDPC encoding or LDPC decoding.

The application belongs to the technical field of decoding, and discloses an LDPC decoding system based on dynamic hypernetwork and two-stage learning, which is composed of a main decoding network and a dynamic hypernetwork, the dynamic hypernetwork is composed of a plurality of hypernetwork units corresponding to each layer of the main decoding network one by one, and the dynamic hypernetwork and the main decoding network are a controller-executor relationship; the dynamic hypernetwork dynamically outputs key parameters of the main decoding network for each iteration, and the main decoding network uses the key parameters to complete message passing and LLR updating; the input of the first hypernetwork unit is a log-likelihood ratio (LLR) value vector received by a channel, and the vector carries key information of a received signal; starting from the second hypernetwork unit, the input of the tth hypernetwork unit is the output of the t-1th layer of the main decoding network. The application significantly improves decoding performance, greatly improves decoding efficiency, enhances environmental adaptability, and reduces calculation and hardware costs.