9results about How to "Reduce bit width" patented technology

The invention provides a multiply-accumulate approximation operation device adopting shift compensation, which comprises an original weight decoding module, an input feature map rearrangement network module and a rearrangement index shift convolution RiSC algorithm operation module, the original weight decoding module is used for decoding and generating a base weight signal, a weight deviation signal and a switching network control signal; the input feature map rearrangement network module is used for rearranging an input original input feature map sequence according to the switching network control signal generated by the original weight decoding module and outputting a rearranged feature map sequence; and the rearrangement index shift convolution RiSC algorithm operation module is used for splitting the input rearranged feature map sequence into a plurality of groups of subsequences, respectively carrying out RiSC operation, generating a calculation result according to the RiSC algorithm and outputting the calculation result. According to the method, the multiplication operation amount and the model weight storage amount in the multiply-accumulate operation in the deep neural network can be reduced.

The invention provides a mixed precision quantization method and device for MIMO detection, and belongs to the technical field of communication, and the method comprises the steps: mapping a variable to be quantized in an MIMO signal detection process into an integer variable to be quantized and a decimal variable to be quantized; determining an integer initialization bit width corresponding to each integer to-be-quantized variable based on the probability density function, and determining a decimal initialization bit width corresponding to each decimal to-be-quantized variable based on a unified quantization method; training the intelligent agent according to the integer initialization bit width and the decimal initialization bit width, and determining a target quantization bit width output by the intelligent agent; and according to the target quantization bit width, simultaneously quantizing the integer to-be-quantized variable and the decimal to-be-quantized variable to obtain a quantization result. According to the method, the to-be-quantized variables are mapped into two parts, the integers in the DRL algorithm are used for automatically optimizing the integer to-be-quantized variables and the decimal to-be-quantized variables in the training process at the same time, the bit width can be further reduced, and the complexity of hardware implementation is further reduced while the detection performance is guaranteed.

The invention relates to a rectangular coordinate-to-polar coordinate conversion method and device based on an LUT and CORDIC hybrid architecture. The method comprises the following steps: S1, sector folding preprocessing; s2, performing coarse rotation iteration; s3, generating a dynamic address; s4, a compression lookup table is queried; and S5, data compensation and reconstruction. According to the method, a small amount of CORDIC iteration is introduced to rotate the input vector to a very small angle range, so that the input space required to be covered by a subsequent lookup table is greatly compressed; meanwhile, the bit width and the address depth of a storage value in the LUT are remarkably reduced by combining module value residual storage and a dynamic truncation technology, so that the storage resources of the LUT are greatly reduced on the premise of ensuring the precision, and the hardware implementation cost is lower.

The present application provides a signal detection method and system for a large-scale MIMO system, which determines a first damping coefficient and a second damping coefficient according to the number of antennas at the transmitting end and the number of antennas at the receiving end; determines the initial mean of the posterior probability distribution of the transmitted signal according to the received signal, the channel matrix, the average symbol energy and the first damping coefficient; uses the SORI method to perform SORI iteration on the mean of the posterior probability distribution of the transmitted signal, and determines the initial mean of the Gaussian distribution obeyed by the cavity edge probability according to the mean vector after the SORI iteration; uses the EPA iteration method to iteratively update the mean of the Gaussian distribution obeyed by the cavity edge probability, and uses the mean of the Gaussian distribution obeyed by the cavity edge probability that reaches the preset number of EPA iterations as the estimated value of the transmitted signal. SORI and EPA algorithms are combined, and SORI is used to approximate the matrix inversion of the initialization part of the EPA algorithm, thereby greatly improving the convergence speed.

The invention provides a configurable down-sampling multiple filtering method, circuit and system for a sinc3 filter, and the method comprises the steps: receiving a single-bit data stream from a sigma-delta modulator, carrying out the first-stage integration, the second-stage integration and the third-stage integration in sequence, carrying out the sampling of the third-stage integration value at a (D + 3) th clock, a (2D + 3) th clock and a (3D + 3) th clock, and carrying out the sampling of a (D + 3) th clock, a (2D + 3) th clock and a (3D + 3) th clock; three sampling values are obtained, two-stage differential operation is carried out on the three sampling values, and a final filtering output result is obtained; in the third-level integration process, when the input clock counts to D + 4 and 2D + 4, the second-level integration results of the (D + 3) th clock and the 2D + 3 th clock are used as third-level integration values of the D + 4 moment and the 2D + 4 moment respectively, and D is the set downsampling multiple. According to the method, the downsampling multiple is configurable, the problem that a traditional sinc3 filter with the fixed downsampling multiple lacks flexibility in the BMS field is solved, and the register bit width under the large downsampling multiple is reduced.

The invention discloses a brightness adjusting method and circuit, a chip and display equipment. The brightness adjusting method comprises the following steps: dividing a frame period into at least one sub-period; a plurality of brightness binding points are arranged in the brightness adjusting range, the brightness adjusting range is divided into a plurality of wave bands by the brightness binding points, and each wave band has a corresponding display brightness range and pulse frequency; according to two brightness binding points adjacent to the target brightness value, obtaining a band to which the target brightness value belongs so as to obtain a target pulse frequency corresponding to the target brightness value; obtaining the total screen-on duration of the target brightness value in any sub-period according to the band to which the target brightness value belongs; obtaining the screen-on duration of a single pulse in the pulse signal according to the total screen-on duration of the target brightness value in the sub-period and the target pulse frequency; and adjusting the pulse signal according to the screen-on duration of the single pulse and the target pulse frequency so as to adjust the display brightness. The circuit area is reduced; and the production cost is reduced.

This invention discloses an arithmetic logic circuit suitable for balanced ternary systems, comprising a unary balanced ternary operation circuit, a balanced ternary half-adder circuit, a balanced ternary full-adder circuit, and a balanced ternary multiplier circuit. Single-input logic conversion is achieved through the combination of polarized ternary inverters and transistors. The half-adder consists of a basic unit and a transmission gate, realizing two-bit summation and carry output. The full-adder employs two cascaded half-adders and optimizes the carry path, significantly shortening the critical path and reducing the number of transistors. The multiplier uses the basic unit as the control core and combines it with a standard ternary inverter to achieve accurate multiplication. This invention overcomes the interconnection bottleneck of traditional binary logic, avoids the high hardware overhead of unbalanced ternary logic circuits in signed number calculations, and avoids the accuracy loss of approximate calculations in existing balanced ternary logic circuits. It has advantages such as simplified structure, low latency, low power consumption, and accurate operation, and is suitable for high-performance computing scenarios such as artificial intelligence, big data, and very large-scale integrated circuits.

The invention discloses an asynchronous data transmission method and device, electronic equipment, a storage medium and a program product, and belongs to the technical field of electronics. The method comprises the steps that under the condition that a Slave end receives a write instruction, a first pointer is shifted, the first pointer is a pointer for writing data into an asynchronous FIFO at the Slave end and comprises N bits, the bit for performing (i + 1) th shift change on the first pointer is a bit adjacent to the left side of the bit for performing ith shift change on the first pointer, and the bit is a bit adjacent to the left side of the bit for performing ith shift change on the first pointer; n is an integer greater than 1, 1 < = i < = N; on the basis of the first pointer and a second pointer, whether the asynchronous FIFO is in a non-full state or not is determined, the second pointer is a pointer for reading data from the asynchronous FIFO by the Master end, and the first pointer and the second pointer are pointers synchronized across clock domains.

The invention provides a video decompression method and device. The video decompression method comprises the following steps: acquiring a to-be-compressed original video file; processing the original video file by using multi-segment broken line mapping; performing offset quantization processing on the video image after bit width reduction to obtain a compressed video file; the decompression method comprises the following steps: acquiring a plurality of continuous compressed video images from a compressed video file; performing motion estimation on the compressed video image; performing inverse quantization processing on the image after motion estimation to obtain an inverse quantization image; and processing the inverse quantization image by utilizing multi-section broken line mapping to obtain a decompressed video file. Through multi-segment broken line mapping and offset quantization processing, the bit width of the image can be reduced through simple operation to complete compression; the compressed image is aligned through motion estimation, and the compressed image can be recovered through simple operation through inverse quantization processing and multi-segment broken line mapping, so that the problems of complex algorithm, large hardware resource occupation and low efficiency in the existing video compression and decompression process are solved.