3results about How to "Reduce bit width" patented technology

The invention relates to a rectangular coordinate-to-polar coordinate conversion method and device based on an LUT and CORDIC hybrid architecture. The method comprises the following steps: S1, sector folding preprocessing; s2, performing coarse rotation iteration; s3, generating a dynamic address; s4, a compression lookup table is queried; and S5, data compensation and reconstruction. According to the method, a small amount of CORDIC iteration is introduced to rotate the input vector to a very small angle range, so that the input space required to be covered by a subsequent lookup table is greatly compressed; meanwhile, the bit width and the address depth of a storage value in the LUT are remarkably reduced by combining module value residual storage and a dynamic truncation technology, so that the storage resources of the LUT are greatly reduced on the premise of ensuring the precision, and the hardware implementation cost is lower.

The invention provides a configurable down-sampling multiple filtering method, circuit and system for a sinc3 filter, and the method comprises the steps: receiving a single-bit data stream from a sigma-delta modulator, carrying out the first-stage integration, the second-stage integration and the third-stage integration in sequence, carrying out the sampling of the third-stage integration value at a (D + 3) th clock, a (2D + 3) th clock and a (3D + 3) th clock, and carrying out the sampling of a (D + 3) th clock, a (2D + 3) th clock and a (3D + 3) th clock; three sampling values are obtained, two-stage differential operation is carried out on the three sampling values, and a final filtering output result is obtained; in the third-level integration process, when the input clock counts to D + 4 and 2D + 4, the second-level integration results of the (D + 3) th clock and the 2D + 3 th clock are used as third-level integration values of the D + 4 moment and the 2D + 4 moment respectively, and D is the set downsampling multiple. According to the method, the downsampling multiple is configurable, the problem that a traditional sinc3 filter with the fixed downsampling multiple lacks flexibility in the BMS field is solved, and the register bit width under the large downsampling multiple is reduced.

This invention discloses an arithmetic logic circuit suitable for balanced ternary systems, comprising a unary balanced ternary operation circuit, a balanced ternary half-adder circuit, a balanced ternary full-adder circuit, and a balanced ternary multiplier circuit. Single-input logic conversion is achieved through the combination of polarized ternary inverters and transistors. The half-adder consists of a basic unit and a transmission gate, realizing two-bit summation and carry output. The full-adder employs two cascaded half-adders and optimizes the carry path, significantly shortening the critical path and reducing the number of transistors. The multiplier uses the basic unit as the control core and combines it with a standard ternary inverter to achieve accurate multiplication. This invention overcomes the interconnection bottleneck of traditional binary logic, avoids the high hardware overhead of unbalanced ternary logic circuits in signed number calculations, and avoids the accuracy loss of approximate calculations in existing balanced ternary logic circuits. It has advantages such as simplified structure, low latency, low power consumption, and accurate operation, and is suitable for high-performance computing scenarios such as artificial intelligence, big data, and very large-scale integrated circuits.