102results about How to "Reduce bit width" patented technology

Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding with out-of-order processing.

A communication system has lighting equipment that has transmitter comprising multiple light-emitting elements that each emit light of different wavelengths and terminal equipment that has light-receiver comprising multiple light-receiving elements that receive optical signals for each of the different wavelengths.

The invention relates to a method of measuring the distance between a fixed point and an object, by the steps of:a) transmitting a light pulse (11) from the fixed point at a selected instant of transmission;b) periodically scanning of light intensity received at the fixed point and continuously storing, as a set of received scanned signal values, the scanned values at the scanning rate during a predetermined measuring time window (13) embracing the instant of reception of the light pulse reflected from the object;c) repeating steps a) and b) N number of times in order to obtain N number of sets of received signal values;d) summing the individual stored sets of received scanned signal values, set by set, to a summed scanned value set during a calculating window (14) following the N measuring time windows (13);e) repeating steps a) through d) in order to obtain a further summed scanning value set, whereby during or following step d) the further summed scanned value set is added, scanned value set by scanned value set, to the present summed scanned value set to actualize the latter, and whereby an equalizing portion of a summed scanned value set is optionally subtracted therefrom before and/or after the mentioned addition;f) searching within the summed scanned value set for significant scanning values which satisfy predetermined threshold values;g) repeating steps e) and f) until significant scanning values have been detected; andh) determining the looked-for distance from the position of the detected Significant scanning values in the summed scanned value set.

A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist by replacing memory with substitute nodes representing selected slots in the memory, segmenting word level nodes, including one or more of the substitute nodes, in the netlist into segmented nodes, finding reduced safe sizes for the segmented nodes and generating an updated data structure representing the circuit design using the reduced safe sizes of the segmented nodes. The correctness of such systems can require reasoning about a much smaller number of memory entries and using nodes having smaller bit widths than exist in the circuit design. As a result, the computational complexity of the verification problem is substantially reduced.

The invention relates to a multi-business supporting network switching device and an implementation method therefor. The device employs a multi-level CLOS switching configuration, and an input unit, an output unit and a switching unit are respectively provided with a buffer memory. The device can process a multi-business flow, and can achieve switching according to the business characteristics. The device can generate quick flow control in a congestion scene through the output unit, wherein the quick flow control acts on an input end, thereby reducing the congestion stress on the output end, and reducing the congestion degree of a central level. The device can reduce the input flow of a fault plane in a link fault scene through a load balancing scheme, and alleviates the congestion of the switching unit. An output unit package ordering method is employed, thereby reducing the design complexity of the switching unit. A data package cell load balancing method of the input unit is employed for enabling the time difference among cells to be small, thereby reducing the time delay of a data package, and reducing the size of the ordering and recombination buffer memory of an output end.

The invention discloses an implementation method based on various hardware platforms (such as CPLD, FPGA, special chips) for calculating a softmax function. The softmax function is widely applied to multi-classification tasks, attention models and the like for deep learning, wherein related e-exponent and division calculations need to consume many hardware resources. According to a design method,by conducting mathematical transformation on the function, the e-exponent calculation is simplified to one constant multiplication, one exponential operation of 2 with a fixed input range and one shift operation; n division operations are simplified to one highest nonzero digit detection operation, one reciprocal operation with a fixed input range, one shift operation and n multiplication operations. The exponential and reciprocal operations of 2 are achieved according to a specially-designed lookup table, and the same precision can be achieved with a smaller storage space. The method is usedin the attention models and the like for deep learning, the calculation speed can be greatly increased on the premise of almost not influencing the precision, and the consumption of calculation resources and storage resources is reduced.

The invention relates to a generation method of an LTE (Long Term Evolution) system upstream reference signal q-step ZC (Zadoff-Chu) sequence and a system thereof. The method comprises the steps of: firstly, acquiring the length of a ZC sequence according to the number of resource blocks; secondly, calculating a q value according to the length of the ZC sequence, a sequence number and a group number; and thirdly, generating the q-step ZC sequence by a recurrence method. In the invention, the problem of longer calculation time for calculating the maximum prime number is avoided by generating a ZC sequence length lookup table; since the ZC sequence is generated through recursion by skillfully using phase characteristics, the multiplication and division with large amplitude and poor precision during direct calculation of phases are avoided, and the invention has important meaning in practical realization of fixed points; the ZC sequence is generated by the recursion algorithm, and the problem of long calculation time caused by calculating trigonometric function many times during generating the ZC sequence directly by a formula is avoided.

The invention discloses a method for reducing the power consumption of the synchronous module of an OFDM system. The method comprises the following steps: step 101: performing swept frequency correlation operation to the sign bits of the received synchronization sequence and the local known sequence in the time domain to obtain the estimated value of integer carrier frequency offset; and step 102: performing correlation operation to the received sign bits corrected by frequency offset in the time domain to obtain the precise position of the FFT window. By using the method of the invention, the synchronous property of the system can be ensured while the working power of the synchronous module of the system can be reduced.

To perform a product-sum operation by adding third data to a product of first data and second data, a floating point multiplier first multiplies the first data by the second data, and a bit string representing a fixed-point part in the multiplication result is divided into a portion representing more significant digits in the fixed-point part and a portion representing less significant digits in the fixed-point part. Then, a floating point adder first adds less significant multiplication result data having a bit string representing the less significant digits as a fixed-point part to the third data, and then adds the addition result to more significant multiplication result data having a bit string representing the more significant digits as a fixed-point part. A rounding process is performed on the two addition results to obtain a result of the product-sum operation.

A radar sensing system for a vehicle includes transmitters, receivers, a memory, and a processor. The transmitters transmit radio signals and the receivers receive reflected radio signals. The processor produces samples by correlating reflected radio signals with time-delayed replicas of transmitted radio signals. The processor stores this information as a first radar data cube (RDC), with information related to signals reflected from objects as a function of time (one of the dimensions) at various distances (a second dimension) for various receivers (a third dimension). The first RDC is processed to compute velocity and angle estimates, which are stored in a second RDC and a third RDC, respectively. One or more memory optimizations are used to increase performance. Before storing the second RDC and the third RDC in an internal/external memory, the second and third RDCs are sparsified to only include the outputs in specific regions of interest.

An iterative refinement apparatus configured to generate data defining a solution vector x for a linear system represented by Ax=b, where A is a predetermined matrix and b is a predetermined vector. An outer solver processes input data, defining the matrix A and vector b, in accordance with an outer loop of an iterative refinement method to generate said data defining the solution vector x. An inner solver processes data items in accordance with an inner loop of the iterative refinement method. The inner solver is configured to process said data items having variable bit-width and data format. A precision controller determines the bit-widths and data formats of the data items adaptively in dependence on the results of the processing steps of the iterative refinement method; the precision controller configured to control operation of the inner solver for processing said data items with the bit-widths and data formats.

A discrete cosine transform method used on image coding and video cording includes using two input four multiplication structure to replace two input three multiplication structure to let multiplier with the same input enable to be realized unitedly and simultaneously enabling to pick up the same factor of two input four multiplication structure to be at external of butterfly structure for carrying out pretreatment or /and post treatment so as to decrease bit width and operation frequency required by realizing discrete cosine transform.

The utility model provides a filtering method of a far-infra-red (FIR) filter and a filter. On the basis that multiplying units in the filter can be reduced, bit width of the multiplying units is enabled to increase slightly, time delay from data being input to various processing paths of the filtering results are basically the same, and the method can be applicable to a down sampling parallel FIR filter. A first multiplying unit of the filter is used for acquiring ( X ( m )+ X (m+Q)) * (H ( n ) + H (n + Q) ), wherein the value of Q is between 1 and N, and the filter is further used for acquiring X ( m ) * H ( n + Q ) and X ( m + Q) * H ( n ). According to the acquired ( X ( m ) + X ( m + Q) ) * ( H (n) + H ( n + Q) ), X ( m ) * H ( n + Q ) and X ( m + Q ) * H ( n ), the filter acquires X ( m ) * H ( n ) + X ( m + Q ) * H ( n + Q ). The filtering method of the FIR filter and the filter are applicable to the technical field of the filters.

The invention relates to the technical field of GPS, in particular to an efficient GPS digital tracking method. The efficient GPS digital tracking method is characterized in that in the tracking process, the center frequency of a carrier wave is separated from the center frequency of a C/A code, a tracking ring only tracks and adjusts Doppler frequency deviation, corresponding deviation phase step length is calculated through the Doppler frequency deviation, and then the deviation phase step length is compensated with the center phase step length corresponding to the center frequency. According to the efficient GPS digital tracking method, the Doppler frequency is smaller than the center frequency and the largest Doppler frequency is only 1/818 of the center frequency of the carrier wave, and the width of 10 bits can be saved; the largest Doppler frequency of the C/A code is only 1/255750 of the central frequency of the C/A code, and width of 18 bits is saved, computation complexity is reduced when respective phase step lengths are computed, and the synchronous speed and efficiency of the GPS tracking ring are improved.

The present invention relates to a receiving apparatus (11) for receiving signals in a wireless communication system, in which the signals comprise a dedicated channel estimation sequence, comprising a gain control means (3) adapted to control the gain of a received signal, a channel estimation means (8) adapted to perform a channel estimation on the basis of a dedicated channel estimation sequence comprised in a received signal, a gain error correction means (12) adapted to correct a gain error in the result of said channel estimation caused by said gain control means (3) on the basis of said dedicated channel estimation sequence comprised in the received signal, and an equalizing means (7) adapted to perform an equalization on the received signal on the basis of the gain corrected channel estimation result. The present invention further relates to a corresponding receiving method.

The invention relates to an LDPC decoding method, a decoder, a decoding device and a storage medium. The LDPC decoding method comprises the following steps: in the current LDPC decoding iteration, for each check node, respectively limiting the minimum value and the second minimum value of a target information module value according to a preset first amplitude and a preset second amplitude, wherein the target information module value is an information module value transmitted to the check node by a variable node adjacent to the check node; transmitting information to a pre-marked target adjacent variable node according to the limited second minimum value; and transmitting information to other adjacent variable nodes according to the limited minimum value. On the basis of maintaining the error correction capability of the LDPC decoder, the bit width of the decoder can be effectively reduced.