The present application relates to prioritized
power budget arbitration for multiple concurrent memory access operations. A memory device includes memory dies, each memory die including: a
memory array; a memory for storing a
data structure; and
control logic including: a plurality of
processing threads for concurrently executing memory access operations on the
memory array; a priority
ring counter, the
data structure for storing an association between a value of the priority
ring counter and a subset of the plurality of
processing threads; a thread manager for incrementing the value of the priority
ring counter and identifying one or more prioritized
processing threads corresponding to the subset of the plurality of processing threads before a
power management cycle; and a peak
power manager coupled to the thread manager for prioritizing allocation of power to the one or more prioritized processing threads during the
power management cycle.