66 results about "Ring counter" patented technology

The determination of the signal modulation format for a channel is an important aspect of the operation of a signal receiver. A method (700) is described including the steps of receiving (710) a signal, comparing (720) a sample of the received signal to a first threshold value and a second threshold value, creating (720) a signal profile based on the comparison, and selecting (750) a modulation format for the received signal based on the signal profile. An apparatus (500) is also described including a ring counter (510) that receives a sample of an input signal, compares the sample to a first threshold value and a second threshold value, and creates a signal profile for the input signal, a signal profiler (550) that compares the signal profile for the input signal to at least two reference profiles, and a detector (560) that determines a modulation format for the input signal based on the comparison in the signal profiler (550).

This invention provides a printing head which can prevent an increase in the number of block enable signal lines, and can prevent changes in printing ink density caused by interference due to the relative pressures of nozzles generated in ink discharge, and an image printing apparatus using the printing head. For this purpose, an increase in the number of input signal lines along with an increase in the number of blocks is prevented using a block clock signal or the like instead of a block enable signal as an input signal to the printing head. Three ring counters generate signals having different nozzle driving orders. These signals are selectively used by a ring counter selection signal. Ink is not always discharged from the nozzles in the same output order. This can prevent changes in ink density caused by pressure interference.

The interleaved clock generator generates N interleaved clock signals in response to an input clock signal. The interleaved clock generator comprises an interleaved clock generator of a first type for receiving the input clock signal and for generating M interleaved intermediate clock signals in response to the input clock signal. The interleaved clock generator of the first type includes either a multi-stage serial-delay circuit or a ring counter circuit. The interleaved clock generator additionally comprises M interleaved clock generators of a second type, each of which is each for receiving a respective one of the intermediate clock signals from the clock generator of the first type and for generating N/M of the N interleaved clock signals in response to the respective one of the intermediate clock signals. Each of the interleaved clock generators of the second type includes either a ring counter circuit or a multi-stage serial-delay circuit: a ring counter when the interleaved clock generator of the first type includes a multi-stage serial-delay circuit; a multi-stage serial-delay circuit when the interleaved clock generator of the first type includes a ring counter circuit.

A fault state detector for a ring counter is formed from unit current sources each switched under the control of a different one of the outputs of the ring counter. The currents switched in that manner are passed through a unit resistance to generate a voltage signal proportional to the number of asserted outputs from the ring counter. The voltage signal is compared to boundary reference values for valid states of the ring counter outputs and, if the voltage signal is not between the boundary reference values, a fault state is indicated.

Disclosed is a high-speed data buffer, wherein a buffer circuit composed of a ring counter is divided into two sampling circuits composed of a rising-edge portion and a falling-edge portion, and both of the two sampling circuits comprises a trigger circuit and a sampling clock generation circuit. In such a manner, the excess pulse edge can be ensured to occur before the correct edge so that the error data caused by the excess pulse can be over-written with the correct data input afterwards. Therefore, a clock cycle of timing margin can be obtained and the data stored in the data buffer can be ensured to be correct.

The invention provides an LED sectional dimming circuit which comprises a dimming detection end, a power source generation circuit, an annular counter, a decoder and a selection circuit, wherein the dimming detection end is connected with an enable signal En in an LED driving chip and is used for detecting power failure and power on, caused by a dimming switch, of a system; the power source generation circuit is used for providing a power source for circuits in the LED sectional dimming circuit; the output end of the power source generation circuit is connected with the annular counter and the decoder; the input end of the annular counter is connected with the dimming detection end, and the annular counter is used for calculating the frequency of pressing the dimming switch; the input end of the decoder is connected with the annular counter, and the decoder is used for decoding an output signal of the annular counter to control the output of the selection circuit; the selection signal end of the selection circuit is connected with the decoder, the input end of the selection circuit is connected with reference voltage of each section, and the selection circuit is used for selecting the needed reference voltage as output. The LED sectional dimming circuit is wide in application range and can be applied to isolating, non-isolating and floating LED driving circuits and LED driving circuits with various frameworks of PFC (power factor correction) and the like.

The invention discloses relates to the field of machining, in particular to a sealing ring machining method. The method includes the following steps that a lathe supporting clamp is used for clamping blanks, rough machining and finish machining are performed on the front side of a sealing ring through an end face tool till the required size is achieved; rough machining and finish machining are performed on the outer circle of the sealing ring through an outer circle tool, and chamfering is performed; a lathe holding clamp is used for holding the outer circle of the sealing ring, and the inner circle of the sealing ring is machined through an inner circle tool; rough machining and finish machining are performed on the back side of the sealing ring through the end face tool till the required size is achieved, and chamfering is performed through a chamfering tool; a workpiece is clamped through a soft claw, and rough machining and finish machining are performed on the back side of the sealing ring; the workpiece is disassembled, an inner hole of the workpiece is supported through the lathe supporting clamp, and the outer circle of the sealing ring is turned through the outer circle tool; semi-finish machining and finish machining are performed on the front side of the sealing ring through the end face tool till the required thickness size is achieved; the workpiece is installed on a drilling machine, and a sealing ring front side hole is drilled; and a sealing ring counter bore is milled. By means of the sealing ring machining method, the machining process is simple, machining precision can be guaranteed, production efficiency is improved, and production cost is reduced.

The invention discloses a preparation apparatus and method of an ultra-low roughness tungsten probe. The preparation apparatus of an ultra-low roughness tungsten probe includes a damping platform, wherein the damping platform is connected with an L type fixed support; the L type fixed support is connected with a motion control system for driving motion of a tungsten filament; the damping platform is also provided with a container filled with etchant solution; the container filled with etchant solution is arranged just below the tungsten filament; a copper ring counter electrode is arranged in the container filled with etchant solution; a counter electrode isolation system is also arranged in the container filled with etchant solution, and is used for isolating the copper ring counter electrode from the tungsten filament; and the copper ring counter electrode and the tungsten filament are respectively connected with the cathode and anode of a digital control DC source. Based on a dynamic electrochemical corrosion principle, the preparation apparatus and method of an ultra-low roughness tungsten probe. The preparation apparatus of an ultra-low roughness tungsten probe can prepare an ultra-low roughness tungsten probe on the premise of effectively controlling the contour and the ratio length/diameter ratio of the probe point.

An output of a first ring counter is held in a first storage circuit. Outputs of a second ring counter and the first storage circuit are input to a first AND circuit group. An output of a third ring counter and an output of the first storage circuit are input to a second AND circuit group. Outputs of the first AND circuit group are input to a first OR circuit. Outputs of the second AND circuit group are input to a second OR circuit. An output of the first OR circuit is stored in a second storage circuit. An output of the second OR circuit is stored in a third storage circuit. Outputs of the first and second OR circuits and outputs of the second and third storage circuits are supplied to a decode circuit, and are decoded to output an overflow signal and an underflow signal.

The invention discloses a heavy load absolute type multi-ring resolving encoder, comprising an input shaft, a high-speed sealing ring, a heavy load labyrinth bearing cap; a heavy load bearing support, a heavy load bearing, a heavy load casing; a resolving base; a resolving stator, a resolving rotor, a resolving bearing cap, a precision bearing, a ring-number sending disk, a multi-ring counter PCB board, an RD connecting wire, an RD intelligent decoder PCB board, a data output PCN board, a bearing support O-shaped sealing ring, a bearing cap O-shaped sealing ring, an insulating shaft and a grounded braid. According to the invention, by perfectly combining resolver with microprocessor decoding chip and heavy load structure, the heavy load absolute type multi-ring resolving encoder which completely overcomes all the deficiencies existing in photoelectric encoder is formed with the characteristics of small size, good integration, high reliability and high precision. Compared with the photoelectric encoder, the heavy load absolute type multi-ring resolving encoder is especially prominently superior in position/speed feedback systems requiring high precision and high reliability.

A low-power delay buffer circuit is provided, which utilizes a ring counter as address decoder and a latch array for memory. To reduce power consumption, a gated-clock driver tree is applied to the ring-counter addressing architecture. Moreover, a similar gated-driver tree is applied to the input and output ports of the latch array. The delay buffer circuit not only could achieve a power consumption lower than SRAM-based delay buffers, but also could operation under high frequencies and take up less layout area than SRAM-based delay buffers.

The invention disclose a 'percent sign' counter passive mode-locking optical fiber laser, comprising an optical fiber amplifier and two non-linear optical fiber ring mirrors, wherein the two non-linear optical fiber ring mirrors are welded at an input port and an output port of the optical fiber amplifier to form a 'percent sign' counter structure. The two non-linear optical fiber ring mirrors and the optical fiber amplifier compose a F-P cavity which can realize an optical pulse output with stable line width; through the output of the non-linear optical fiber ring mirrors and by launching a feedback loop technology, the optical pulse output with stable line width can be realized; configurations of the non-linear optical fiber ring mirrors enable the light transited in the ring counter clockwise and clockwise to obtain different non-linear phase shift when reaching a coupler, only a phase shift difference rate of the central wavelength reaching pi first and a starting mode-locking forms.

The invention discloses a stream packet header credit processing device, comprising a packet header buffer unit and a packet header credit calculation unit, which is characterized in that: the packet header credit is calculated directly according to the amount of the packet header credit received, recorded and transmitted by a writing pointer and a reading pointer, so that delay-time is reduced; meanwhile, a credit processing device is provided in the invention and the credit processing device comprises the packet header credit processing device and a data credit calculation unit; wherein, in the data calculation circuit a ring counter control unit and a controlling table unit are used to choose different types of data; the data credit is calculated via the shared circuit, so that circuit area is saved and calculation speed is raised; the invention also provides a sending device, a receiving device, a transmission system and a processing and transmitting method using the receiving and sending devices and transmission system, so that credit processing is optimized; efficiency is increased and power consumption is reduced with the stream control device and stream control method in the invention.

Described are a system and method for transmitting digital messages through wire channels and telecommunication channels using electromagnetic waves. The use of the channels is simplified by excluding multiplication and division operators from the coding and a decoding process. The system and method allows to transmit any messages from elements of Abelian group including code words whose elements are matrixes, polynomials, numbers of mixed-base notation and nonpositional notation. An encoder of the system may include a driver clock, a function g<2> calculator, a pulse generator having recurrent frequency of f(k+1)/k, a pulse recurrent frequency doubler, a ring counter up to k, an adder-accumulator of elements of Abelian group, a key, a ring counter up to (2k+1), an AND component, a main memory unit, a key, a trigger, a main memory unit and a ring counter up to (k+1). A decoder of the system may include a driver clock, an adder-accumulator of elements of Abelin groupoid, a pulse generator having recurrent frequency of fk(k+1)/k, a pulse recurrent frequency doubler, a ring counter up to (k+1), a key, a main memory unit, a key, an AND component, a ring counter up to [2(k+1)+1], an identification unit provided with a single element of Abelian group, a trigger, a main memory unit a key, a ring counter up to k.

Disclosed are a latch circuit receiving a negative output of a next latch stage circuit as a feedback input, a double data rate (DDR) ring counter based on the latch circuit to perform DDR counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based DDR ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a CMOS image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a form of a ring. The plurality of latches may include positive-edge-triggered latches and negative-edge-triggered latches arranged alternately. A current latch stage receives an output of a preceding latch stage to shift to a next latch stage according to a counter clock, receives an output of the next latch stage to check a data shift to the next latch stage, and falls to a low level if the data shift is checked.

The invention discloses a prefabricated ring network cabinet foundation, comprising a left end plate, a right end plate, a bottom plate, a front side wall, a rear side wall and a ring network cabinet base, the left end plate is located at the left end of the bottom plate, and the left end plate and the bottom plate are integrated structure, the right end plate is set at the right end of the base plate, the height of the left end plate and the right end plate are the same; The top surface of the front side wall and the rear side wall are located on the same plane, and the base of the ring network cabinet is installed on the plane, and the length and width of the base of the ring network cabinet and the bottom plate are the same; A through hole is opened in the lower part, and the through hole communicates with the man well. The present invention adopts 7 components, which not only ensures the convenience of installation, but also takes into account the efficiency of production and transportation, and speeds up the progress of the whole project. On the basis of the combination, the angle steel frame is embedded outside, which not only ensures the stability of the structure, but also has a very good sensory effect.

The invention discloses an any input signal bit stream adder based on sigma-delta modulation. The any input signal bit stream adder comprises a n input 1-bit binary adder, an enabling end control logic unit, a n-bit ring counter set and a n+1-bit data selector; the output end of the n input 1-bit binary adder is respectively connected with the enabling end control logic unit and the n+1-bit data selector; and the enabling end control logic unit, the n-bit ring counter set and the n+1-bit data selector are sequentially connected. According to the any input signal bit stream adder based on sigma-delta modulation disclosed by the invention, a n-bit code is used for representing an intermediate value required by a n input bit stream adder (n is an any value); the n-bit ring counter set is used for storing the intermediate value; corresponding ring counters are selected and driven under corresponding conditions to circularly output sequentially; the any input signal bit stream adder based on sigma-delta modulation is finally realized; and thus, the any input signal bit stream adder based on sigma-delta modulation has high operation precision.

Disclosed are a latch circuit receiving a negative output of a next stage latch circuit as a feedback input, a double data rate (DDR) ring counter based on the latch circuit to perform DDR counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based DDR ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a CMOS image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a ring type. The plurality of latches may include positive-edge-triggered latches and negative-edge-triggered latches arranged alternately. A current stage latch receives an output of a previous latch stage to shift to a next latch stage according to a counter clock, receives an output of the next latch stage to check a data shift to the next latch stage, and falls to a low level if the data shift is checked.

A relative prime modulo parallel counter based on the congruent theory relates to a counter of synchronous shift register type composed of a first, a second synchronous ring counters, and a decode unit, among which, the numbers of triggers in any two synchronous ring counters from the first to r are prime mutually, the clock pulse input ends of all synchronous ring counters are connected and linked to the clock pulse signals, the positive output or negative output end of each trigger in all said counters are connected to an input end of the decode unit. It uses the counter as its basic component and numbers of triggers in each are prime mutually, so a large count can be got with only a few ring counters.