38 results about "Delta modulation" patented technology

The invention discloses an arrhythmia detection method based on a pulse neural network. The method comprises the following steps: performing incremental modulation pulse coding and pooling operation on a target electrocardiosignal to obtain a corresponding pulse sequence; and inputting the pulse sequence into a trained multi-level pulse neural network classification model to obtain an arrhythmia detection result. Wherein the multi-level pulse neural network classification model comprises a weight sharing layer and a plurality of cascaded classifiers, the weight sharing layer is used for extracting electrocardiosignal feature information from the pulse sequence, and the plurality of classifiers are used for obtaining an arrhythmia detection result based on the electrocardiosignal feature information. According to the method, on the premise that the accuracy is equivalent, the classification result is more refined, and the requirements for hardware storage resources and computing resources are reduced.

A system, method, and non-transitory computer readable medium for in-field seismic data compression. The system includes geophones each having a 1-bit adaptive delta modulation for converting analog seismic signals to a modulated signal and transmitting the modulated signal, and a data collection center having a 1D convolutional neural network for receiving and compressing the transmitted modulated signal. The 1D CNN is configured to suppress quantization and random noise in the modulated signal.

Transceiver array synchronization by receiving a clock signal and at least one synchronization pulse signal at each transceiver IC of a plurality of transceiver integrated circuit (IC) subarrays, wherein each transceiver IC subarray contains a respective set of serially connected transceiver ICs; and synchronizing the transceiver IC with other transceiver ICs of the respective set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal.

The invention relates to a light emitting diode driving device and a method for generating a driving signal thereof. A light emitting diode driving device using a control signal of M + N bits comprises: a Sigma-Delta modulation unit which receives the control signal of M bits and generates a modulation signal of 1 bit; a first summing unit that generates a first summed signal by summing an N1-bit control signal among the N-bit control signals and the modulation signal; and a drive unit that receives the first summation signal and generates the drive signal.

A procedure for overcurrent shutdown is proposed, comprising the following steps: - Capturing and providing a current value as an analog output signal; - a conversion of the analog output signal by means of an analog-to-digital converter, which converts the analog output signal by means of sigma-delta modulation and provides it as a bitstream, characterized in that - the bitstream is converted using a first decimation filter and provided as a first data stream; and - Evaluating the first data stream, wherein a threshold value for a current is compared with the current value from the first data stream, and if at least one threshold value is exceeded, the overcurrent shutdown is triggered by means of a shutdown signal, wherein the shutdown signal is transmitted to at least one signal output and is used for opening a power switch. Furthermore, the invention relates to a device.

An extension for HT Control field is provided to accommodate UEQM and LA parameters. The first m bits of HTC Extension may be used to demonstrate the type of extension. Tables of common UEQM patterns or combinations with high probability can be considered for different number of spatial streams. Delta modulation can be adopted to show UEQM patterns. An index for showing different combinations of delta modulation for streams can be used. A subfield in UHR LA Extension with n bits can be considered for UEQM Pattern Index.

Embodiments of the present disclosure disclose a self-adaptive single-bit quantization SAR imaging method and device, a storage medium and a product. The method comprises: iteratively reconstructing an image matrix, in each iteration, transforming the image matrix to an echo domain based on a threshold matrix, an original echo signal matrix and an inverse imaging operator, performing single-bit quantization on the image matrix in the echo domain to obtain an echo residual; performing matched filtering on the echo residual using an imaging operator and then performing gradient descent to obtain a gradient descent result matrix; performing threshold shrinkage on the gradient descent result matrix based on a weight matrix and a fractional order sparse norm to obtain an updated image matrix; updating the weight matrix based on the updated image matrix; updating the threshold matrix using a delta modulation algorithm; and obtaining a SAR imaging result when a maximum number of iterations is reached. The method can compensate for the loss of amplitude information and improve the SAR imaging accuracy by adaptively updating the threshold and the fractional order sparse norm constraint while only retaining the signs of the echo signals.

The invention provides a sigma-delta modulation circuit and a high-precision temperature sensor. The sigma-delta modulation circuit comprises a two-phase non-overlapping clock, a first switched capacitor integrating circuit, a second switched capacitor integrating circuit, a quantizer and a digital-analog conversion module. The two-phase non-overlapping clock provides a driving signal; the first switched capacitor integrating circuit performs integration processing on the analog detection voltage and outputs a first differential voltage; the second switched capacitor integrating circuit performs integration processing on the first differential voltage and outputs a second differential voltage; the quantizer converts the second differential voltage into a modulation signal; the digital-to-analog conversion module converts the modulation signal into a feedback voltage; and the switching circuit is used for switching the working states of the first switched capacitor integrating circuit and the second switched capacitor integrating circuit. When a temperature signal is in a low frequency band, the first switched capacitor integrating circuit and the second switched capacitor integrating circuit are used to form a second-order one-bit CIFB topological structure, noise is pushed to a high frequency band, the signal-to-noise ratio of the low frequency band is improved, and high-precision temperature detection is realized.

The invention belongs to the field of deep space exploration and space science, and relates to a digital fluxgate magnetometer system based on a 1-bit sigma-delta digital-to-analog converter, which comprises a sensor probe for sensing the size and direction of an environment magnetic field by adopting a single-axis fluxgate sensor and outputting a magnetic field signal to an analog circuit module, receiving excitation current and feedback current to maintain the working state of the magnetic core; the analog circuit module generates excitation current, performs amplification and analog-to-digital conversion on the received magnetic field signal, performs digital-to-analog conversion, filtering and driving on the signal output by the digital circuit module, and outputs feedback current to a feedback coil of the sensor probe; and the digital circuit module is realized based on an FPGA, performs phase-sensitive demodulation, digital integration, 1-bit sigma-delta modulation, down-sampling and digital low-pass filtering on the digital signal after analog-to-digital conversion, outputs the processed magnetic field detection data to an upper computer, and generates a synchronous clock signal to the analog circuit module at the same time.

The invention provides a sigma-delta modulation digital-to-analog conversion circuit, and belongs to the technical field of digital-to-analog conversion. A fully differential circuit structure is formed through a first capacitor module, a second switch capacitor module, a fourth capacitor module, a fifth switch capacitor module, a third switch capacitor module and a sixth switch capacitor module. According to the invention, charge storage, transfer, release and redistribution between each module and the in-phase input end, the anti-phase input end, the in-phase output end and the anti-phase output end of the operational amplifier can be realized, and the proportion among the modules can be adjusted, so that the step amplitude of charge transfer is controlled, and high-precision analog signal reconstruction is realized. Through the circuit provided by the invention, output analog signal reconstruction can be realized through charge storage, transfer, release and redistribution, the reconstruction precision is improved, the high reconstruction precision requirement of sigma-delta modulation can be met, and the problem of low reconstruction precision of a traditional circuit is solved.

The invention discloses an MEMS four-mass gyroscope closed-loop detection circuit system based on Sigma-Delta modulation technology, which is characterized in that the MEMS four-mass gyroscope closed-loop detection circuit system comprises a driving closed-loop circuit, a detection closed-loop circuit and an FPGA digital part, the driving closed-loop circuit comprises a C / V conversion circuit 1, a low-pass filter 1, an ADC module 1 and a DAC module 1; the detection closed loop comprises a C / V conversion circuit 2, a low-pass filter 2, an ADC module 2 and a four-channel switch; the FPGA digital part comprises a digital phase-locked loop circuit, a digital amplitude control circuit, a digital pulse density circuit, a demodulator 1 and a downsampling filter 1. The force feedback closed loop is formed, the sensitive mode of the MEMS gyroscope can obtain one-bit digital quantization output, quantization noise in the bandwidth is effectively restrained, and the closed loop detection loop bandwidth is improved.

One embodiment is a baseline restoration ("BLR") circuit for a non-imaging counting computed tomography ("PCCT") signal chain, the BLR circuit comprising: a comparator to compare a shaper voltage output from a shaper component of the PCCT signal chain to a baseline voltage, the comparator outputting a single bit indicating whether the shaper voltage is above or below the baseline voltage; a low pass filter connected to filter a voltage signal output from the comparator; and a transconductor connected to receive the filtered voltage signal output from the low pass filter, convert the filtered voltage signal to a current signal, and feed back the current signal to an input of the PCCT signal chain.

The invention relates to a method and an apparatus for overcurrent switch-off The method comprises the following steps: • detecting and providing a current intensity value as an analogue output signal (9); • converting the analogue output signal by means of an analogue-to-digital converter (2) which converts the analogue output signal by means of sigma-delta modulation and provides it as a bit stream (10); • the bit stream is converted by means of a first decimation filter (3) and provided as a first data stream (11); • evaluating the first data stream, wherein a threshold value for a current intensity is compared with the current intensity value from the first data stream and, if the threshold value is exceeded at least once, the overcurrent switch-off is triggered by means of a switch-off signal (21), wherein the switch-off signal is transmitted to at least one signal output (14) and used for opening a circuit breaker (7).

Spatial audio may be generated by a speaker array that is switched according to rows and / or columns to reduce its cost and complexity. The speaker array may include a row of speakers that are each coupled to a different column channel. The rows of speakers can receive portions of the spatial audio on a row-by-row basis as each row is activated to couple the speakers in a row to their respective column. This switched approach reduces a number of required audio sources. The audio sources may generate PWM signals for each column using an approach that is similar to that found in Class-D amplification or sigma-delta Modulation. Analog signals may be recovered from the PWM signals using a low-pass filter positioned before each speaker in the array.

The application discloses a quantization disturbance method and device based on a Sigma-Delta modulation DAC, which comprises the following steps: calculating the difference between a determined modulation signal and a determined feedback signal as a target signal, and performing a preprocessing operation on the target signal to obtain an integral signal, wherein the preprocessing operation comprises integral processing; performing a quantization operation on the integral signal to obtain a target disturbance modulation signal, wherein the target disturbance modulation signal is used as a disturbance modulation signal of the DAC. It can be seen that, by performing integral processing on the calculated signal and performing a quantization operation on the signal after the integral processing, the accurate disturbance modulation signal used for disturbing the DAC can be obtained, the randomness of the quantization code word of the disturbance modulation signal is enhanced, the SFDR performance of the DAC is improved, the stray radiation of the DAC is ensured, the application is not dependent on the specific implementation structure of the DAC, has higher universality, and can be used simultaneously with DEM.

A light-emitting diode driving device using (M+N) bit control signals may be configured to include: a sigma-delta modulation unit that receives the M bit control signals and generates a 1 bit modulation signal; a first summing unit that sums the N1 bit control signals among the N bit control signals and the modulation signal to generate a first summing signal; and a driving unit that receives the first summing signal and generates the driving signal.

The invention discloses a power supply system based on Sigma-Delta modulation and adaptive calibration, which belongs to the field of signal processing and comprises a signal modulation path and an adaptive calibration path. The signal modulation path comprises a first Sigma-Delta ADC, an MOS switch tube and a line equivalent filter, and modulates an input voltage into an output voltage for power supply. The self-adaptive calibration path comprises a programmable gain amplifier, a second Sigma-Delta ADC, a compensation filter and a pre-stored lookup table, wherein the programmable gain amplifier is used for sampling output voltage. And after compensation filtering, comparing with ideal calibration parameters in the lookup table, and dynamically feeding back a generated error signal to a reference voltage end of the ADC to carry out real-time closed-loop calibration. Through cooperation of Sigma-Delta modulation and adaptive calibration, output ripples are reduced, errors caused by nonlinearity and path loss of components are effectively compensated, and the method is suitable for supplying power to complex scenes.

A continuous-time sigma-delta modulator and an offset correction method for the continuous-time sigma-delta modulator. The continuous-time sigma-delta modulator comprises a continuous-time sigma-delta modulation module, a data monitoring module, and an offset correction module. In addition to the continuous-time sigma-delta modulation module, the data monitoring module and the offset correction module are added. On the basis of the hardware architecture design of the offset correction module and the data monitoring module in combination with software data processing, and on the basis of the feedback of the signal-to-noise ratio of a digital signal, offset of a quantizer in the continuous-time sigma-delta modulation module can be pre-corrected according to a preset correction algorithm, and an offset correction digital code is obtained; and finally, the offset correction digital code is input into the quantizer by means of the offset correction module, and offset of the quantizer is finally corrected by means of the offset correction digital code. On the basis of the hardware architecture design and software data processing, offset of the quantizer in the continuous-time sigma-delta modulation module can be quickly and effectively corrected.

Disclosed in the present invention is a high current-sharing accuracy and high dynamic constant on-time (COT) control system and method for a multiphase Buck converter. The system comprises an analog main control loop, an all-digital steady-state current-sharing loop, a high-performance PWM control module, and a high-precision on-time generation module. According to the present invention, a high current-sharing accuracy and high dynamic COT control method is used, improving the multiphase PWM overlapping capability of a VRM during load transients, reducing an output voltage undershoot, ensuring precise dynamic current sharing and output voltage stability during the load transients, and facilitating adaptation to high-frequency load transient scenarios of 100 KHz and above. The all-digital steady-state current-sharing loop uses Sigma-delta modulation technology and, in combination with a hybrid high-resolution DPWM in the high-precision on-time generation module, reduces a system requirement for high bandwidth in the steady-state current-sharing loop, thereby reducing the dependency of a COT-controlled multiphase digital power supply on a high-speed multiplexed ADC, reducing the volume of a circuit, and lowering chip costs.

A device (e.g., SAR ADC device) include a DAC circuit and generates a digital output based on logic circuitry that includes SAR logic. Additional logic circuitry includes delta modulation circuitry and dynamic element matching circuitry. The delta modulation circuitry provides several digital outputs of the SAR DAC, while the dynamic element matching circuitry selects a different set of capacitors from the DAC circuit. Each cycle is added together and averaged, and then added to the digital output from the SAR logic.

A continuous-time sigma-delta modulator includes a continuous-time sigma-delta modulation module, a data monitoring module, and an offset calibration module. The data monitoring module and the offset calibration module are added on the basis of the continuous-time sigma-delta modulation module. Based on a hardware architecture design of the offset calibration module and the data monitoring module, with reference to software data processing, an offset of a quantizer in the continuous-time sigma-delta modulation module can be pre-calibrated based on feedback of a signal-to-noise ratio of a digital signal and a preset calibration algorithm, to obtain an offset calibration digital code. Finally, the offset calibration digital code is input into the quantizer by using the offset calibration module, and the offset of the quantizer is finally calibrated based on the offset calibration digital code.

A method of encoding an analog signal into a digital signal, the method comprising the steps of: determining an envelope of a received analog signal thereby producing an enveloped signal, applying a non-linear transformation to the enveloped signal thereby obtaining a non-linearly transformed enveloped signal, Analog-to-Digital converting, by an Analog-to-Digital converter, ADC, the non-linearly transformed enveloped signal, to produce the digital signal, wherein the ADC is a delta modulator.

The invention provides an integrator multiplexing method for a high-order Sigma-Delta modulation system, and relates to the technical field of signal processing, and the method comprises the steps: signal preprocessing: filtering out the high-frequency noise of an original signal through an anti-aliasing filter, and enabling the high-frequency noise to serve as an input signal of an integrator multiplexing module; generating a three-phase clock signal: generating the three-phase clock signal through a three-phase clock circuit; integrator multiplexing: performing multi-stage integration at phi1-phi3 phases in a time-sharing manner through a single integrator under the control of a three-phase clock signal through a multi-stage integrating capacitor and a switching network which are connected in parallel; and integrator output transcoding: converting an integration result into a digital code, and suppressing quantization noise through a feedback path. Through the multi-stage integrating capacitor and the switching network which are connected in parallel, multi-stage integration is executed in a phi 1-phi 3 phase time-sharing mode under the control of the three-phase clock signal, the three-phase clock signal supports multi-stage multiplexing and dynamic configuration, the system integration degree is improved, power consumption is reduced through integrator multiplexing, and the system reliability is improved. A high-order system which can only be realized by a plurality of integrators is realized by using a small number of integrators.

Apparatus, Method and Computer Program There is provided an apparatus comprising means for providing channel state information as input to a spatial and frequency encoder, wherein the output of the spatial and frequency encoder is a latent vector, providing the latent vector to an adaptive delta modulation encoder, where-in the output of the adaptive delta modulation encoder is a bit stream comprising one or more bits per dimension of the latent vector, wherein the one or more bits per dimension indicate an adaptive delta modulation encoded value determined based on an initial step size for the respective dimension and providing the bit stream to a network entity for decoding by a spatial and frequency decoder.

A device and method for sigma-delta modulation may include an input signal and a plurality of integrators. The output of the integrators and a data input may be input to an adder, the sum output to be input to a quantizer to generate a quantized output signal. A reset input to the first integrator may be asserted during a first sample of the quantized output signal to reduce the signal discontinuity at the input of the first integrator, which improves the stability of the sigma-delta modulator.

There is provided an apparatus comprising means for obtaining a data set from a spatial and frequency encoder, the data set comprising latent vectors determined by the spatial and frequency encoder based on channel state information, determining a first parameter of an adaptive delta modulation scheme suitable for temporal encoding based on the data set, wherein the first parameter is an initial step size per dimension of a latent vector and providing the first parameter to a user equipment comprising the spatial and frequency encoder and an adaptive delta modulation encoder, wherein the output of the spatial and frequency encoder comprises a latent vector and wherein the output of the adaptive delta modulation encoder is a bit stream comprising adaptive delta modulation encoded values for each dimension of the latent vector based on the initial step size for the respective dimension.

The invention relates to a readout circuit (100) for reading out a current of 10 nA or less, wherein the readout circuit arrangement (100) comprises a capacitive current amplifier (10) and a continuous time delta sigma-delta modulator (20) in current mode. The invention further relates to the use of a readout circuit and to a method for reading out a readout circuit.

The invention provides a DEM (Digital Elevation Model) conversion method for a multi-bit quantizer Sigma-Delta modulation system, which relates to the technical field of signal processing, and comprises the following steps: signal preprocessing: receiving a digital output signal from a quantizer through an input signal processing module, carrying out input signal judgment, judging whether the signal is exponential power of 2 or not, and if yes, judging whether the signal is exponential power of 2 or not; if the exponential power is 2, entering a tree structure equivalent series circuit and adding randomized disturbance, and if the exponential power is not 2, entering a random disturbance circuit and adding randomized disturbance; and temporary storage and output: temporarily storing the intermediate state data through a data temporary storage module, converting the thermometer code into an analog signal based on a feedback DAC, and feeding back the analog signal to an integrator of the Sigma-Delta modulator. When the signal is the exponential power of 2, the tree structure equivalent series circuit organizes the selection structure of the DAC unit into a tree shape, the selection logic operation is completed in a short time, and when the signal is not the exponential power of 2, randomized disturbance is added through the random disturbance circuit, and the signal is converted into a thermometer code.

The examples herein provide enhanced optical architectures employing techniques and systems for scaling up a signal bandwidth and correcting errors in optical signals to achieve a corrected waveform that can be adjusted for the desired application with broad tuning of bandwidth, chirp rate, chirp duration and symmetry. An optical signal is provided for circulation in an optical loop, and incremental modulations are applied to the optical signal over a quantity of circulations to establish circulating waveforms that form a composite waveform. Detected errors in the circulating waveforms can be corrected during the incremental modulations. In some instances, a portion of the optical signal comprising the composite waveform can then be directed for emission toward a remote target and remote sensing of properties of the remote target.