75results about "Delta modulation" patented technology

An analog to digital converter has an input, a plurality of quantizers, a plurality of feedback loops, and a plurality of filters. The input is configured to receive an input signal. The plurality of quantizers has the Nth quantizer, and the Nth quantizer has the Nth quantizer input and the Nth quantizer output. The Nth quantizer input is connected to the input. The plurality of feedback loops has the Nth feedback loop, and the Nth feedback loop is formed around the Nth quantizer output and the Nth quantizer input and configured to reduce the difference between the signal of the Nth quantizer output and an Nth reference signal at an Nth frequency region. The plurality of filters has an Nth filter. The Nth filter is configured to select the Nth frequency region. The feedback loops provide a way to control the effect of some nonidealities such as comparator offsets.

A delta sigma type ADC (1) is provided with a quantizer (30) operating at a prescribed sampling frequency (fs), an FIR filter (40) connected to the quantizer (30), and a DAC (50). A feedback path for the quantizer (30) is structured by the FIR filter (40) and the DAC (50). A reference signal for the DAC (50) is supplied from a reference signal source (60) chopping at a frequency lower than the prescribed sampling frequency (fs).

Disclosed is a circuit including: a loop filter (105) to perform digital processing on a signal inputted from an outside; multiple quantizers (103-1 to 103-N) to output 1-bit signals corresponding to magnitude relationships with thresholds on the basis of the signal after the digital processing by the loop filter (105); and an averaging circuit (104) to calculate the average of the values shown by the signals outputted by the quantizers (103-1 to 103-N), and to feed back the average to the loop filter (105), in which the thresholds used by the quantizers (103-1 to 103-N) differ from one another.

A differential delta-sigma-modulator has an integrator (49) including a pair of single-ended amplifiers (46, 47). The differential delta-sigma-modulator comprises a sample clock (50) driving a first switchable capacitor configuration (31) and a second switchable capacitor configuration (32) at a predetermined switching cycle. The second switchable capacitor configuration (32) is adapted for sampling respective outputs from the pair of single-ended amplifiers (46, 47) on a pair of output sampling capacitors (C3, C5) in the first part of the switching cycle (P1), and charging a common mode capacitor (C4) with the average voltage of the voltage sampled by the pair of output sampling capacitors (C3, C5) in the second part of the switching cycle (P2). The voltage across the common mode capacitor (C4) represents the common mode voltage for the integrator (49).

To suppress a time difference in a conversion completion timing of an ADC within a desired range.SOLUTION: An AD conversion circuit comprises: a ΔΣAD converter 200-1 that has a ΔΣ modulator 300-1 and a digital filter 301-1; a ΔΣAD converter 200-2 that has a ΔΣ modulator 300-2 and a digital filter 301-2; a CPU 208 that outputs a conversion start request signal START_CPU at each measurement value acquisition cycle of the ΔΣAD converter 200-2; and a control unit 210 that operates the ΔΣAD converters 200-1 and 200-2 asynchronously in a normal mode, and sets the integration period of the digital filter 301-2 so that the conversion by the ΔΣAD converter 200-1 and the conversion by the ΔΣAD converter 200-2 are synchronized with each other within the measurement value acquisition cycle in a synchronous mode.SELECTED DRAWING: Figure 1

To provide an AD conversion circuit with low distortion.SOLUTION: An AD conversion circuit (101) includes: a delta-sigma converter (1) that converts an analog input voltage into one bit digital output data; a reference voltage source (2) that outputs a reference voltage for determining a full scale of AD conversion; a detection circuit (3) that includes at least one of a first detection circuit (31) that detects from the one bit digital output data that the analog input voltage is lower than a first voltage value and a second detection circuit (32) that detects from the one bit digital output data that the analog input voltage is higher than a second voltage value, the second voltage value being higher than the first voltage value; and a correction circuit (4) that corrects the reference voltage based on detection results of the detection circuit and outputs the corrected reference voltage. The delta-sigma converter performs delta-sigma conversion based on an output of the correction circuit.SELECTED DRAWING: Figure 1

A comparison circuit is provided with: an adder that generates an output voltage; a holding capacitor that holds the output voltage output from the adder; a comparator to which the output voltage held by the holding capacitor is input from one input terminal and which performs a comparison operation using the output voltage; a cut-off switch provided in a connection path between the adder and one input terminal of the comparator; and a reset switch which is connected between the cut-off switch and the holding capacitor and resets the potential of the holding capacitor.

A delta-sigma modulator (110) for detecting a current input signal from a current source (120), the delta-sigma modulator (110) comprising: a first node (138) configured to connect to the current source (120) and receive the current input signal, wherein the first node (138) is an input of the delta-sigma modulator (110); a capacitive summing circuit (132) having an input connected to the first node (138) and an output connected to a second node (142), the capacitive summing circuit (132) being configured to amplify a signal at the first node (138) and deliver an amplified signal to the second node (142), the capacitive summing circuit (132) comprising (i) a first amplifier (134) having an input connected to the first node (138) and an output connected to the second node (132) and (ii) a first capacitance (136) connected between the output of the first amplifier (134) and the input of the first amplifier (134); a loop filter circuit (140) having an input connected to the second node (142) and an output connected to a third node (152), the loop filter (140) being configured to filter the amplified signal at the second node (142) and supply a filtered signal to the third node (152); a quantizer circuit (150) having an input connected to the third node (152) and an output connected to a fourth node (154), the fourth node (154) being an output of the delta-sigma modulator (110), the quantizer circuit (150) being configured to quantize the filtered signal at the third node (152) and supply a quantized signal to the fourth node (154); a first feedback path (160) connected between the fourth node (154) and the first node (138), wherein at least one second capacitor (670) is arranged in the first feedback path (160) and is configured to capacitively couple the quantized signal to the first node (138); a first switch (404) connected between the current source (120) and the first node (138); and at least one processor configured to operate the first switch (404) to (i) open a first predetermined time period before any change in the value of the quantized signal at the fourth node (154) and (ii) close a second predetermined time period after any change in the value of the quantized signal at the fourth node (154).

To provide technology that makes is possible to suppress a computation error due to discontinuity by a simple configuration.SOLUTION: A delta sigma modulator (1000, 1400, 2000) comprises: a distribution unit (110, 2010) for dividing an input signal into a plurality of signal blocks; a parallel circuit unit (120, 2020) including two or more filter circuits, each of the two or more filter circuits including two or more delta sigma modulation circuits including different initial values; and a combining unit (130, 2030) for executing combining processing to combine a plurality of output signals. The combining unit executes combining processing by using the output selection signal of the delta sigma modulation circuit for processing a leading signal block among the plurality of signal blocks and the initial values.SELECTED DRAWING: Figure 20

This technology provides advantages in reducing the circuit size of ΔΣ type AD conversion circuits. [Solution] An AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, comprising: a ΔΣ type AD converter including an integration circuit for integrating a difference signal; a switching circuit that, in a first period, supplies the analog signal supplied to the input terminal to the ΔΣ type AD converter, and in a second period following the first period, switches the supply of a voltage signal corresponding to the voltage output from the integration circuit at the end of the first period to the ΔΣ type AD converter; and a holding circuit that holds the voltage signal corresponding to the voltage output from the integration circuit at the end of the first period and provides the voltage signal to the ΔΣ type AD converter via the switching circuit in the second period, wherein the integration circuit includes a continuous-time integrator and a discrete-time integrator connected to the output of the continuous-time integrator.

An ADC circuit with a comparator circuit for a neural interface is provided. The comparator circuit includes a comparator to receive a first and a second signal, and amplify the first and the second signal. A bump bias circuit of the comparator circuit receives the amplified first and second signal, and causes the comparator to operate at a higher power level when a difference between the amplified first and second signal is smaller and to operate at a lower power level when the difference between the amplified first and second signal is larger. Two comparator circuits are connected to a first and second switching circuit. A control circuit of the ADC circuit may set a capacitor state of first capacitor pairs of the first switching circuit and a capacitor state of second capacitors pairs of the second switching circuit, based on outputs of the first and second comparator circuit.

To restrain distortion that occurs in a signal output through delta-sigma modulation during a transmission process of the signal.SOLUTION: A delta-sigma modulation device 1300 performs delta-sigma modulation on a first signal as an input signal to output a second signal, learns parameters of a transmission path distortion model 1321 using the second signal and a third signal that is generated via a transmission path of the second signal, inputs the second signal to the transmission path distortion model 1321 to output a fourth signal that is an approximation value of a signal generated via at least a part of the transmission path of the second signal, and performs delta-sigma modulation on the first signal using the fourth signal to output the second signal.SELECTED DRAWING: Figure 13

Disclosed is a circuit including: a loop filter (105) to perform digital processing on a signal inputted from an outside; multiple quantizers (103-1 to 103-N) to output 1-bit signals corresponding to magnitude relationships with thresholds on the basis of the signal after the digital processing by the loop filter (105); and an averaging circuit (104) to calculate the average of the values shown by the signals outputted by the quantizers (103-1 to 103-N), and to feed back the average to the loop filter (105), in which the thresholds used by the quantizers (103-1 to 103-N) differ from one another.

To provide an isolator that can reduce signal transmission delay while simultaneously reducing power consumption. [Solution] The isolator according to the embodiment includes a ΔΣ modulated analog-to-digital converter that converts an input analog signal into a pulse train digital data signal corresponding to the amplitude and outputs it; an attribute signal detection circuit that outputs input attribute information relating to the attributes of the input analog signal; a high-speed feedback encoder that encodes the digital data signal based on the input attribute information and outputs a first encoded signal; an edge encoder that edge encodes the first encoded signal and outputs a second encoded signal; an isolated transmission circuit that outputs a transmission signal transmitted through an isolation section according to the second encoded signal; and a demodulation circuit that outputs a demodulated digital data signal obtained by demodulating the digital data signal based on the transmission signal, and / or outputs demodulated attribute information obtained by demodulating the input attribute information.

An integrated circuit comprises a sigma-delta modulator (SDM) coupled to a receiving electrode that is selectively coupled to multiple unit cell sensors. A demodulator is directly coupled to the SDM, and the demodulator is designed to generate a digital multi-bit signal by demodulating a digital pulse-density modulated (PDM) signal received by the SDM. The demodulation may involve multiplying digitized cosine values ​​by the digital PDM signal. A cascaded integrator-differentiator (CIC) filter is coupled to the demodulator and comprises a first integrator and a second integrator cascaded together to accumulate a multitude of samples of the digital multi-bit signal at the second integrator.The CIC filter includes a single-comb circuit coupled to the second integrator, whereby the single-comb circuit is intended to generate a bitstream with measured amplitude from the accumulated sample values.

To make the size of full scale the same even when OSR is changed by making the full scale of the output of a digital filter a power of 2.SOLUTION: A delta-sigma modulator including an input terminal to which an input signal is input, a first amplification and integration circuit, a second amplification and integration circuit, an adder, and a quantizer, and a digital filter including a first digital integration circuit that outputs a third digital signal generated by integrating an output signal of the delta-sigma modulator and a second digital integration circuit that outputs a fourth digital signal generated by integrating the third digital signal, the digital filter outputs a fifth digital signal generated by subtracting 1 / 2 of the third digital signal from the fourth digital signal.SELECTED DRAWING: Figure 1

This disclosure relates to an ADC circuit and a comparator circuit for a neural interface. The ADC circuit can include the comparator circuit. The comparator circuit comprises a comparator to receive a first and a second signal, and internally amplify the first and the second signal. A bump bias circuit of the comparator circuit receives the amplified first and second signal, and causes the comparator to operate at a higher power level when a difference between the amplified first and second signal is smaller, and at a lower power level when the difference between the amplified first and second signal is larger. The ADC circuit comprises two comparator circuits connected to a first and second switching circuit. A control circuit of the ADC circuit can set a capacitor state of first capacitor pairs of the first switching circuit, and a capacitor state of second capacitors pairs of the second switching circuit, based on outputs of the first and second comparator circuit.

A circuit (100) includes a programmable gain amplifier (PGA 102) having a PGA output. The circuit (100) further includes a delta-sigma modulator (104) having an input coupled to the PGA output. The circuit (100) also includes a digital filter (114) and a dynamic range enhancer (DRE) circuit (110). The digital filter (114) is coupled to the delta-sigma modulator output and to the PGA (102). The DRE circuit (110) is configured to monitor a signal level of the delta-sigma modulator output. In response to the signal level being less than a DRE threshold, the DRE circuit (110) is configured to program the PGA to a gain level greater than unity gain and to cause the digital filter to implement an attenuation of the same magnitude as the gain level to be programmed into the PGA (102).

A switching voltage-controlled current source comprising: a current source input terminal for receiving a first input logic signal and a current source output terminal for outputting current; a first logic circuit comprising a first logic input terminal connected to the current source input terminal, a first logic output terminal for outputting a current control signal, a first supply terminal for connecting to a power supply and a first ground terminal for connecting to the ground; a first resistor coupled between the first logic output terminal and the current source output terminal; a second resistor coupled between the power supply and first supply terminal and a third resistor coupled between the ground and the first ground terminal; wherein the first logic circuit is operable to selectively couple the second resistor or the third resistor to the first resistor; a first charge supply circuit and a second charge supply circuit.

The amplifier circuit is configured with a resistor divider (R ) including n resistor elements, two main nodes defined across the resistor elements, two readout nodes (d , d ), and a resistor node (q) defined between adjacent resistor elements. REF ), and an input current source (I REF ), including the resistor divider (R REF ) is the feedback signal (S FB ) and includes two arrays of addressable switch elements that can be controlled to open or close by a second node (b). The amplifier circuit includes a differential pair of transistors (T1, T2), the source terminals of each of the transistors (T1, T2) are connected to a second node (b), the gate terminals of the transistors (T1, T2) are connected to input signals (v1, v2), the drain terminals of the transistors (T1, T2) are connected to current sources (I1, I2), and the bulk terminals of the transistors (T1, T2) are connected to readout nodes (d1, d2). The amplifier circuit functions as a differential amplifier, where the bulk terminals are connected to a feedback signal (S FB ) determined by the resistor divider (R REF ) affects the thresholds of the transistors (T1, T2) respectively so as to add or subtract the differential signal derived from the read nodes (d1, d2).

To provide an A / D conversion circuit capable of performing AD conversion in high accuracy while reducing an offset.SOLUTION: An A / D conversion circuit includes a capacitance coupled amplifier 11 for amplifying an analog input signal configured by providing capacitors C1a, C1b, C3a, C3b, and amplifier OP1. A first integrator 12 in correlated double sampling type as a first stage integrator is provided following the stage of the capacitance coupled amplifier 11. The output of the capacitance coupled amplifier 11 and the input of capacitors C4a, C4b of the first integrator 12 are directly connected without through a switch. A second integrator 13 is provided following the first integrator 12. A quantizer T1 for quantizing an output value of the second integrator 13 is provided following the second integrator 13. D / A converters 20a, 20b, 220a, 220b for performing D / A conversion for the output of the quantizer T1 and feeding it back to either the capacitance coupled amplifier 11, the first integrator 12, or the second integrator 13 are provided.SELECTED DRAWING: Figure 1

An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (Vin) and a plurality of converter circuits (105l-105N). Each converter circuit (105j) comprises a comparator circuit (70j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70j). Furthermore, each converter circuit (105j) comprises a one-bit current-output DAC (110j) having an input directly controlled from the output of the comparator circuit (70j) and an output connected to the second input of the comparator circuit (70j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits (70j).

A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

An integrated circuit comprises a sigma-delta modulator coupled to a receiving electrode of a capacitive touchscreen sensor and includes a first unbalanced integrator and a second unbalanced integrator, selectively coupled to an output of the first unbalanced integrator. A latch is coupled to an output of the second unbalanced integrator and is driven by a frequency modulation signal. A compensation circuit is selectively coupled to a first input of the first unbalanced integrator and to a second input of the second unbalanced integrator.Logic is coupled to the compensation circuit and, based on the frequency modulation signal and an output value of the latch, causes the compensation circuit to do one of the following: apply a positive compensation current to the first input and a negative compensation current to the second input; or apply a positive compensation current to the second input and a negative compensation current to the first input.

A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.

A comparison circuit (10) is provided with: an adder (20) that generates an output voltage (Vadd) by means of a plurality of capacitors (Ca1, Cb2, Cth); a comparator (11) that performs a comparison operation using the output voltage (Vadd) generated by the adder (20), the comparator (11) performing the following operations: determining a reference voltage to be used in the comparison operation by the capacitance ratio of the plurality of capacitors (Ca1, Cb2, Cth); the capacitance ratio of the plurality of capacitors (Ca1, Cb2, Cth) is set such that the reference voltage becomes the reference voltage at which the signal-to-quantization noise ratio (SQNR) is maximum.

A delta-sigma analog-to-digital converter includes a first integrator, an input chopping switch, an output chopping switch, a second integrator, a sampling capacitive element, an addition capacitive element, an odd-numbered subtraction capacitive element, an even-numbered subtraction capacitive element. The first integrator includes a differential structure, and samples an input voltage according to a first clock signal. The input chopping switch performs a chopping operation by alternately switching a connection to a positive input terminal and a negative input terminal of the first integrator according to a second clock signal being an inverted phase of the first clock signal. The output chopping switch performs a chopping operation by alternately switching a connection to a positive output terminal and a negative output terminal of the first integrator according to the second clock signal. The second integrator includes a differential structure and located after the first integrator.

This technology provides advantages in reducing the circuit size of continuous-time ΔΣ type AD conversion circuits. [Solution] An AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, comprising: a continuous-time ΔΣ type AD converter including an integration circuit for integrating a difference signal; and a switching circuit that switches the supply of an analog signal to the input terminal to the continuous-time ΔΣ type AD converter during a first period, and during a second period following the first period, a voltage signal corresponding to the voltage output from the integration circuit at the end of the first period to be supplied to the continuous-time ΔΣ type AD converter, wherein the continuous-time ΔΣ type AD converter is configured to allow gain adjustment of the analog signal input to the continuous-time ΔΣ type AD converter.

To provide a Δ Σ type analog-digital converter and an optical sensor capable of suppressing an increase in sampling frequency, suppressing an increase in measurement time, and having high sensitivity.SOLUTION: An analog-to-digital conversion device includes a Δ Σ analog-to-digital converter that converts an analog signal into a digital signal having a pulse width corresponding to a magnitude of the analog signal, first to n-th delay circuits in which a first delay circuit delays the digital signal to generate a first delay signal, an i-th delay circuit delays an (i- 1) - th delay signal to generate an i-th delay signal, I is an integer of 2 or more and n or less, and n is an integer of 2 or more, and a signal processing circuit that acquires a signal value corresponding to the magnitude from the digital signal and the first to n-th delay signals.SELECTED DRAWING: Figure 1