106results about "Delta modulation" patented technology

A system, method, and non-transitory computer readable medium for in-field seismic data compression. The system includes geophones each having a 1-bit adaptive delta modulation for converting analog seismic signals to a modulated signal and transmitting the modulated signal, and a data collection center having a 1D convolutional neural network for receiving and compressing the transmitted modulated signal. The 1D CNN is configured to suppress quantization and random noise in the modulated signal.

An analog to digital converter has an input, a plurality of quantizers, a plurality of feedback loops, and a plurality of filters. The input is configured to receive an input signal. The plurality of quantizers has the Nth quantizer, and the Nth quantizer has the Nth quantizer input and the Nth quantizer output. The Nth quantizer input is connected to the input. The plurality of feedback loops has the Nth feedback loop, and the Nth feedback loop is formed around the Nth quantizer output and the Nth quantizer input and configured to reduce the difference between the signal of the Nth quantizer output and an Nth reference signal at an Nth frequency region. The plurality of filters has an Nth filter. The Nth filter is configured to select the Nth frequency region. The feedback loops provide a way to control the effect of some nonidealities such as comparator offsets.

A delta sigma type ADC (1) is provided with a quantizer (30) operating at a prescribed sampling frequency (fs), an FIR filter (40) connected to the quantizer (30), and a DAC (50). A feedback path for the quantizer (30) is structured by the FIR filter (40) and the DAC (50). A reference signal for the DAC (50) is supplied from a reference signal source (60) chopping at a frequency lower than the prescribed sampling frequency (fs).

Disclosed is a circuit including: a loop filter (105) to perform digital processing on a signal inputted from an outside; multiple quantizers (103-1 to 103-N) to output 1-bit signals corresponding to magnitude relationships with thresholds on the basis of the signal after the digital processing by the loop filter (105); and an averaging circuit (104) to calculate the average of the values shown by the signals outputted by the quantizers (103-1 to 103-N), and to feed back the average to the loop filter (105), in which the thresholds used by the quantizers (103-1 to 103-N) differ from one another.

A differential delta-sigma-modulator has an integrator (49) including a pair of single-ended amplifiers (46, 47). The differential delta-sigma-modulator comprises a sample clock (50) driving a first switchable capacitor configuration (31) and a second switchable capacitor configuration (32) at a predetermined switching cycle. The second switchable capacitor configuration (32) is adapted for sampling respective outputs from the pair of single-ended amplifiers (46, 47) on a pair of output sampling capacitors (C3, C5) in the first part of the switching cycle (P1), and charging a common mode capacitor (C4) with the average voltage of the voltage sampled by the pair of output sampling capacitors (C3, C5) in the second part of the switching cycle (P2). The voltage across the common mode capacitor (C4) represents the common mode voltage for the integrator (49).

To suppress a time difference in a conversion completion timing of an ADC within a desired range.SOLUTION: An AD conversion circuit comprises: a ΔΣAD converter 200-1 that has a ΔΣ modulator 300-1 and a digital filter 301-1; a ΔΣAD converter 200-2 that has a ΔΣ modulator 300-2 and a digital filter 301-2; a CPU 208 that outputs a conversion start request signal START_CPU at each measurement value acquisition cycle of the ΔΣAD converter 200-2; and a control unit 210 that operates the ΔΣAD converters 200-1 and 200-2 asynchronously in a normal mode, and sets the integration period of the digital filter 301-2 so that the conversion by the ΔΣAD converter 200-1 and the conversion by the ΔΣAD converter 200-2 are synchronized with each other within the measurement value acquisition cycle in a synchronous mode.SELECTED DRAWING: Figure 1

A delta-sigma modulation apparatus performs delta-sigma modulation on a first signal as an input signal and outputs a second signal; learns a parameter for a transmission path distortion model using the second signal and a third signal generated through a transmission path of the second signal; inputs the second signal to the transmission path distortion model and outputs a fourth signal that is an approximated value of a signal which is generated through at least part of the transmission path of the second signal, and performs the delta-sigma modulation on the first signal using the fourth signal and outputs the second signal.

To provide an AD conversion circuit with low distortion.SOLUTION: An AD conversion circuit (101) includes: a delta-sigma converter (1) that converts an analog input voltage into one bit digital output data; a reference voltage source (2) that outputs a reference voltage for determining a full scale of AD conversion; a detection circuit (3) that includes at least one of a first detection circuit (31) that detects from the one bit digital output data that the analog input voltage is lower than a first voltage value and a second detection circuit (32) that detects from the one bit digital output data that the analog input voltage is higher than a second voltage value, the second voltage value being higher than the first voltage value; and a correction circuit (4) that corrects the reference voltage based on detection results of the detection circuit and outputs the corrected reference voltage. The delta-sigma converter performs delta-sigma conversion based on an output of the correction circuit.SELECTED DRAWING: Figure 1

To make the initial charge amount of a holding capacitance constant.SOLUTION: A comparison circuit includes an adder that generates an output voltage, a hold capacitance that holds the output voltage output from the adder, a comparator that receives the output voltage held in the hold capacitance from one of its input terminals and performs a comparison operation using the output voltage, a cut-off switch provided in a connection path between the adder and one of the input terminals of the comparator, and a reset switch connected between the cut-off switch and the hold capacitance for resetting the potential of the hold capacitance.SELECTED DRAWING: Figure 9

In an analog / digital converter (90), a first integration circuit (10) temporally integrates a sum of an analog input signal (Vin) and a first feedback signal (V4) and includes an active element. A second integration circuit (20) temporally integrates a sum of a result of integration by the first integration circuit (10) and the first feedback signal (V4) and does not include an active element. A first signal generation circuit (34) compares a first output voltage (V5) representing a result of integration by the second integration circuit (20) with a threshold voltage (Vth) at discrete time intervals. When the first output voltage (V5) is higher than the threshold voltage (Vth), the first signal generation circuit (34) generates 1 as a first digital signal (DS), and when the first output voltage (V5) is lower than the threshold voltage (Vth), the first signal generation circuit (34) generates 0 as the first digital signal (DS). The first signal generation circuit (34) outputs a signal obtained by inverting 1 and 0 of the first digital signal (DS) as the first feedback signal (V4).

A comparison circuit is provided with: an adder that generates an output voltage; a holding capacitor that holds the output voltage output from the adder; a comparator to which the output voltage held by the holding capacitor is input from one input terminal and which performs a comparison operation using the output voltage; a cut-off switch provided in a connection path between the adder and one input terminal of the comparator; and a reset switch which is connected between the cut-off switch and the holding capacitor and resets the potential of the holding capacitor.

The total quantization noise C that occurs when quantizing the filter output for the input signal i (j) A filter circuit that searches for a candidate for a quantized output signal sequence based on the sum of quantization noise C i (j) Within the range of a threshold C set for , candidates for the output signal sequence are searched for by depth-first search of a tree structure.

To provide a delta-sigma modulator which controls magnitude of an adjustment signal.SOLUTION: A delta-sigma modulator 200 includes: an integration part for outputting an integration signal AOUT which is integration of an input signal ASIG; a quantization part having an allowable range for an inputted voltage, for outputting a quantized signal DOUTPRE which if a quantized signal of inputted signal; a feedback part 132 for subtracting a feedback signal AFB whose magnitude is according to the quantized signal from the input signal to be inputted to the integration part; an input adjustment part 114 for subtracting an adjustment signal AFBOFS having a voltage within the allowable range from the integration signal to be inputted to the quantization part; and an output correction part 150 for correcting the quantized signal according to the magnitude of the adjustment signal.SELECTED DRAWING: Figure 3

A delta-sigma modulator (110) for detecting a current input signal from a current source (120), the delta-sigma modulator (110) comprising: a first node (138) configured to connect to the current source (120) and receive the current input signal, wherein the first node (138) is an input of the delta-sigma modulator (110); a capacitive summing circuit (132) having an input connected to the first node (138) and an output connected to a second node (142), the capacitive summing circuit (132) being configured to amplify a signal at the first node (138) and deliver an amplified signal to the second node (142), the capacitive summing circuit (132) comprising (i) a first amplifier (134) having an input connected to the first node (138) and an output connected to the second node (132) and (ii) a first capacitance (136) connected between the output of the first amplifier (134) and the input of the first amplifier (134); a loop filter circuit (140) having an input connected to the second node (142) and an output connected to a third node (152), the loop filter (140) being configured to filter the amplified signal at the second node (142) and supply a filtered signal to the third node (152); a quantizer circuit (150) having an input connected to the third node (152) and an output connected to a fourth node (154), the fourth node (154) being an output of the delta-sigma modulator (110), the quantizer circuit (150) being configured to quantize the filtered signal at the third node (152) and supply a quantized signal to the fourth node (154); a first feedback path (160) connected between the fourth node (154) and the first node (138), wherein at least one second capacitor (670) is arranged in the first feedback path (160) and is configured to capacitively couple the quantized signal to the first node (138); a first switch (404) connected between the current source (120) and the first node (138); and at least one processor configured to operate the first switch (404) to (i) open a first predetermined time period before any change in the value of the quantized signal at the fourth node (154) and (ii) close a second predetermined time period after any change in the value of the quantized signal at the fourth node (154).

To provide technology that makes is possible to suppress a computation error due to discontinuity by a simple configuration.SOLUTION: A delta sigma modulator (1000, 1400, 2000) comprises: a distribution unit (110, 2010) for dividing an input signal into a plurality of signal blocks; a parallel circuit unit (120, 2020) including two or more filter circuits, each of the two or more filter circuits including two or more delta sigma modulation circuits including different initial values; and a combining unit (130, 2030) for executing combining processing to combine a plurality of output signals. The combining unit executes combining processing by using the output selection signal of the delta sigma modulation circuit for processing a leading signal block among the plurality of signal blocks and the initial values.SELECTED DRAWING: Figure 20

To suppress degradation in signal-to-quantization noise ratio (SQNR).SOLUTION: A comparator circuit includes: an adder that generates an output voltage by a plurality of capacitances; and a comparator that performs a comparison operation using the output voltage generated by the adder. In the comparator, a reference voltage used for the comparison operation is determined according to the capacitance ratio of the plurality of capacitances, and the capacitance ratio of the plurality of capacitors is set so that the reference voltage is a reference voltage at which the signal-to-quantization noise ratio is maximum.SELECTED DRAWING: Figure 4

This technology provides advantages in reducing the circuit size of ΔΣ type AD conversion circuits. [Solution] An AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, comprising: a ΔΣ type AD converter including an integration circuit for integrating a difference signal; a switching circuit that, in a first period, supplies the analog signal supplied to the input terminal to the ΔΣ type AD converter, and in a second period following the first period, switches the supply of a voltage signal corresponding to the voltage output from the integration circuit at the end of the first period to the ΔΣ type AD converter; and a holding circuit that holds the voltage signal corresponding to the voltage output from the integration circuit at the end of the first period and provides the voltage signal to the ΔΣ type AD converter via the switching circuit in the second period, wherein the integration circuit includes a continuous-time integrator and a discrete-time integrator connected to the output of the continuous-time integrator.

The problem of the present disclosure is to provide an A / D converter in which conversion errors are reduced and which is capable of subjecting a plurality of analog input voltages to A / D conversion by time division. A comparator (7) compares a comparison reference voltage (V5) to the differential voltage (V4) between a conversion target voltage (V3), which is constituted by analog input voltages (V1, V2), and a comparison voltage produced by a D / A conversion unit (5). A switching circuit (62) connects capacitance elements (C11, C12), which correspond to the analog input voltages (V1, V2) selected as the conversion target voltage (V3), to an output terminal of an integrator (61). The integrator (61) integrates the differential voltage (V4) in a state in which an A / D conversion unit (3) has carried out a conversion operation on the least significant bit. A comparison reference generation unit (6) uses, as the comparison reference voltage (V5), a charging voltage for the capacitance elements (C11, C12) corresponding to the analog input voltages (V1, V2) selected as the conversion target voltage (V3).

The present technology relates to a signal processing apparatus, a signal processing method, and a program that make it possible to cope with an output of a PCM signal using one DSD signal. A distribution apparatus includes an extraction section that, in a case where a PCM signal having a predetermined sampling frequency is generated from a DSD signal, extracts a predetermined number of samples from the DSD signal around samples at a predetermined interval determined by the predetermined sampling frequency, and a filtering section that generates the PCM signal having the predetermined sampling frequency by filtering the extracted predetermined number of samples. The present technology is applicable to, for example, a distribution apparatus, etc., that distributes the PCM signal to a client apparatus.

An ADC circuit with a comparator circuit for a neural interface is provided. The comparator circuit includes a comparator to receive a first and a second signal, and amplify the first and the second signal. A bump bias circuit of the comparator circuit receives the amplified first and second signal, and causes the comparator to operate at a higher power level when a difference between the amplified first and second signal is smaller and to operate at a lower power level when the difference between the amplified first and second signal is larger. Two comparator circuits are connected to a first and second switching circuit. A control circuit of the ADC circuit may set a capacitor state of first capacitor pairs of the first switching circuit and a capacitor state of second capacitors pairs of the second switching circuit, based on outputs of the first and second comparator circuit.

To restrain distortion that occurs in a signal output through delta-sigma modulation during a transmission process of the signal.SOLUTION: A delta-sigma modulation device 1300 performs delta-sigma modulation on a first signal as an input signal to output a second signal, learns parameters of a transmission path distortion model 1321 using the second signal and a third signal that is generated via a transmission path of the second signal, inputs the second signal to the transmission path distortion model 1321 to output a fourth signal that is an approximation value of a signal generated via at least a part of the transmission path of the second signal, and performs delta-sigma modulation on the first signal using the fourth signal to output the second signal.SELECTED DRAWING: Figure 13

Disclosed is a circuit including: a loop filter (105) to perform digital processing on a signal inputted from an outside; multiple quantizers (103-1 to 103-N) to output 1-bit signals corresponding to magnitude relationships with thresholds on the basis of the signal after the digital processing by the loop filter (105); and an averaging circuit (104) to calculate the average of the values shown by the signals outputted by the quantizers (103-1 to 103-N), and to feed back the average to the loop filter (105), in which the thresholds used by the quantizers (103-1 to 103-N) differ from one another.

To provide an isolator that can reduce signal transmission delay while simultaneously reducing power consumption. [Solution] The isolator according to the embodiment includes a ΔΣ modulated analog-to-digital converter that converts an input analog signal into a pulse train digital data signal corresponding to the amplitude and outputs it; an attribute signal detection circuit that outputs input attribute information relating to the attributes of the input analog signal; a high-speed feedback encoder that encodes the digital data signal based on the input attribute information and outputs a first encoded signal; an edge encoder that edge encodes the first encoded signal and outputs a second encoded signal; an isolated transmission circuit that outputs a transmission signal transmitted through an isolation section according to the second encoded signal; and a demodulation circuit that outputs a demodulated digital data signal obtained by demodulating the digital data signal based on the transmission signal, and / or outputs demodulated attribute information obtained by demodulating the input attribute information.

An integrated circuit comprises a sigma-delta modulator (SDM) coupled to a receiving electrode that is selectively coupled to multiple unit cell sensors. A demodulator is directly coupled to the SDM, and the demodulator is designed to generate a digital multi-bit signal by demodulating a digital pulse-density modulated (PDM) signal received by the SDM. The demodulation may involve multiplying digitized cosine values ​​by the digital PDM signal. A cascaded integrator-differentiator (CIC) filter is coupled to the demodulator and comprises a first integrator and a second integrator cascaded together to accumulate a multitude of samples of the digital multi-bit signal at the second integrator.The CIC filter includes a single-comb circuit coupled to the second integrator, whereby the single-comb circuit is intended to generate a bitstream with measured amplitude from the accumulated sample values.

According to the present invention, spurious noise is reduced in a noise reduction processing device provided with a loop filter and a quantizer.　A difference calculation unit obtains a difference between an input signal and a predetermined feedback signal, and outputs it as an error signal. A delay signal adder adds the error signal and a predetermined delay signal and outputs it as an integrated signal. An internal dither adder adds the integrated signal and a predetermined internal dither signal and outputs it as a filter output signal. A delay unit in the filter delays the filter output signal and outputs it as a delay signal. A quantizer quantizes the filter output signal and feeds it back as a feedback signal.

To make the size of full scale the same even when OSR is changed by making the full scale of the output of a digital filter a power of 2.SOLUTION: A delta-sigma modulator including an input terminal to which an input signal is input, a first amplification and integration circuit, a second amplification and integration circuit, an adder, and a quantizer, and a digital filter including a first digital integration circuit that outputs a third digital signal generated by integrating an output signal of the delta-sigma modulator and a second digital integration circuit that outputs a fourth digital signal generated by integrating the third digital signal, the digital filter outputs a fifth digital signal generated by subtracting 1 / 2 of the third digital signal from the fourth digital signal.SELECTED DRAWING: Figure 1

This disclosure relates to an ADC circuit and a comparator circuit for a neural interface. The ADC circuit can include the comparator circuit. The comparator circuit comprises a comparator to receive a first and a second signal, and internally amplify the first and the second signal. A bump bias circuit of the comparator circuit receives the amplified first and second signal, and causes the comparator to operate at a higher power level when a difference between the amplified first and second signal is smaller, and at a lower power level when the difference between the amplified first and second signal is larger. The ADC circuit comprises two comparator circuits connected to a first and second switching circuit. A control circuit of the ADC circuit can set a capacitor state of first capacitor pairs of the first switching circuit, and a capacitor state of second capacitors pairs of the second switching circuit, based on outputs of the first and second comparator circuit.

In an analog-to-digital converter (90), a first integrating circuit (10) integrates the sum of an analog input signal (Vin) and a first feedback signal (V4) with respect to time, and includes an active element. A second integrating circuit (20) integrates the sum of the integration result of the first integrating circuit (10) and the first feedback signal (V4) with respect to time, and does not include an active element. A first signal generating circuit (34) compares a first output voltage (V5) representing the integration result of the second integrating circuit (20) with a threshold voltage (Vth) in discrete time intervals, generates a 1 as a first digital signal (DS) if the first output voltage (V5) is higher than the threshold voltage (Vth), and generates a 0 as the first digital signal (DS) if the first output voltage (V5) is lower than the threshold voltage (Vth). The first signal generating circuit (34) outputs, as the first feedback signal (V4), a signal obtained by inverting the 1 or 0 of the first digital signal (DS).

A comparator circuit comprising an adder that generates an output voltage, a hold capacitor that holds the output voltage output from the adder, a comparator that receives the output voltage held in the hold capacitor from one input terminal and performs a comparison operation using the received output voltage, a cutoff switch provided in a connection path between the adder and the one input terminal of the comparator, and a reset switch that is connected between the cutoff switch and the hold capacitor and that resets the potential of the hold capacitor.

A circuit (100) includes a programmable gain amplifier (PGA 102) having a PGA output. The circuit (100) further includes a delta-sigma modulator (104) having an input coupled to the PGA output. The circuit (100) also includes a digital filter (114) and a dynamic range enhancer (DRE) circuit (110). The digital filter (114) is coupled to the delta-sigma modulator output and to the PGA (102). The DRE circuit (110) is configured to monitor a signal level of the delta-sigma modulator output. In response to the signal level being less than a DRE threshold, the DRE circuit (110) is configured to program the PGA to a gain level greater than unity gain and to cause the digital filter to implement an attenuation of the same magnitude as the gain level to be programmed into the PGA (102).