264 results about "Noise shaping" patented technology

The invention discloses a high-precision power supply output correction method based on a digital pre-distortion technology, and relates to the technical field of power electronics, and the method comprises the steps: integrating an electricity-heat-magnetism real-time combined observer, and inputting parameters including a power supply output voltage, a current, a power device junction temperature, a magnetic element surface temperature, an environment temperature, and an input voltage ripple; using a hierarchical memory depth pre-distortion compensator to generate an anti-phase pre-distortion signal containing long time domain thermal constant compensation and short time domain capacitance energy storage compensation based on modeling engine output; based on a double-ring adaptive updating module, an inner ring updates electrical parameters, including on resistance and dead time, by taking a switching period as a reference, and an outer ring updates thermomagnetic parameters, including thermal resistance and a magnetic core saturation point, in a minute-level period; and the DAC is connected in series with a pre-distortion signal output end through an anti-interference execution channel, and comprises a noise shaping DAC and a driving stage for delay matching. According to the invention, through an electric-thermal-magnetic three-field combined observation architecture, the limitation of traditional single physical field monitoring is broken through.

The invention discloses a passive feed-forward noise shaping SAR ADC structure and a quantification method thereof. The structure comprises a second-order noise shaping circuit based on a charge pump, a sampling switch circuit, a DAC capacitor array, a six-input comparator and a logic control circuit. The method comprises the following steps: sampling an input analog signal to an upper pole plate of a DAC capacitor array; carrying out inter-board capacitor voltage switching processing according to the control signal, and outputting a successive approximation voltage signal; obtaining quantization residual voltage in inter-board capacitor voltage switching processing, performing second-order noise shaping filtering processing, and outputting a first-order integral voltage signal and a second-order integral voltage signal; comparing the successive approximation voltage signal, the first-order integral voltage signal and the second-order integral voltage signal to obtain a digital code; and carrying out inter-board capacitor voltage switching according to the digital code to obtain a quantization result. According to the embodiment of the invention, the power consumption of the SAR ADC structure can be reduced, and the quantization precision of the SAR ADC structure can be improved. The circuit can be widely applied to the technical field of integrated circuits.

The noise-shaping successive-approximation-register analog-to-digital converter includes a capacitive digital-to-analog-converter, a loop filter including a plurality of integration capacitors, and a multi-input comparator. During an integration phase, the capacitive digital-to-analog converter couples to the plurality of integration capacitors to develop an integration voltage. The integration capacitors are then arranged to passively apply a first gain to the integration voltage. The multi-input comparator also provides a second gain to the integration voltage.

The invention discloses a discrete time increment type analog-to-digital converter and a control method thereof, the analog-to-digital converter comprises a modulator and a digital filter, and the modulator comprises an integrator module, a single-bit quantizer, an FIR feedback digital-to-analog converter, a first compensation path and a second compensation path. The control method comprises the following steps: carrying out noise shaping processing on an input signal and an output signal of a single-bit quantizer to obtain a preliminary output signal; and the digital filter is used for filtering the preliminary output signal to obtain an output signal of the analog-to-digital converter. According to the analog-to-digital converter, hardware consumption and digital power consumption can be reduced, the conversion precision of the analog-to-digital converter is improved, and the signal distortion degree of the analog-to-digital converter is reduced. The circuit can be widely applied to the technical field of mixed signal circuits.

A noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) (SAR ADC) including a noise-shaping (NS) filter, a comparator, a differential input path between the NS filter and the comparator, and a cross-coupled set of capacitive elements coupled to the differential input path.

A VCO-Based Continuous-Time (CT) delta-sigma modulator (DSM) with a noise-shaping (NS) successive approximation register (SAR) quantizer for a 3rd order noise transfer function (NTF) is presented. An anti-aliasing filter (AAF) enables this new hybrid architecture. The 28 nm CMOS prototype NSQ VCO CTΣΔ achieves 84.2 dB SNDR and 86.8 dB DR within a 1 MHz bandwidth while consuming 1.62 mW at 100 MS / s. The core circuit occupies only 0.024 mm2. No calibration or coefficient tuning is required.

The invention relates to an integrator circuit for eliminating thermal noise and a Delta-sigma modulator, and belongs to the technical field of electronic signal processing, the modulator comprises at least two stages of integrators, a quantizer, a feedback DAC and an adder; the integrator comprises an integrator circuit, and the integrator circuit comprises a sampling module for sampling an input signal source; the double-path multi-phase clock control pre-amplification auxiliary storage circuit module alternately samples and stores thermal noise voltage and offset voltage; the integral amplifier is used for amplifying a signal output by the double-path multi-phase clock control pre-amplification auxiliary storage circuit module; and the integrating capacitor is connected between the integrating amplifier and the two-way multi-phase clock control pre-amplification auxiliary storage circuit module, and feeds back the signal after integration processing to the two-way multi-phase clock control pre-amplification auxiliary storage circuit module to realize signal modulation and noise shaping. The thermal noise introduced in the sampling process is effectively reduced, and the area of the whole chip is reduced while the signal-to-noise ratio is improved.

The invention relates to the technical field of digital playing equipment, and provides a lossless control method for the volume of a digital player and the digital player. The method comprises the following steps of: after receiving a target volume parameter, executing dynamic multiplying power oversampling and high-order noise shaping on an input digital audio signal, and injecting preset jitter to suppress in-band quantization distortion so as to generate an optimized digital audio stream; meanwhile, a high-resolution digital reference current control instruction corresponding to the target volume is independently generated, output of a reference current source is adjusted according to the high-resolution digital reference current control instruction, and a high-precision differential current signal is obtained by combining nonlinearity, temperature excursion and quantization errors of a closed-loop feedback compensation device through a multi-bit current segmentation network; performing bias stabilization processing on the signal, and converting the signal into a differential voltage signal for suppressing common-mode noise through a precision differential resistance network; and finally, low-distortion differential analog audio signals capable of directly driving a load are output through low-distortion gain, impedance conversion and power driving, so that low-distortion, high-signal-to-noise-ratio and wide-dynamic-range output in a full-volume range is realized.

The invention relates to a full-dynamic exponential increment type low-delay high-precision analog-to-digital converter, which comprises a loop integrator used for receiving an ith-round input signal, and sequentially performing addition processing and integration processing on the ith-round input signal and a feedback signal calibrated by an (i-1) th round to obtain an ith-round integration signal; the first-order exponential increment error feedback noise shaping SAR quantizer is used for carrying out addition processing and multi-bit quantization on the ith round integral signal and the double (i-1) th round residual signal to obtain an ith round quantization signal; the digital-to-analog conversion module is used for sequentially performing format conversion, mismatch calibration and digital-to-analog conversion on the (i-1) th round of quantized signals in the process of processing the ith round of input signals to obtain feedback signals after the (i-1) th round of calibration; and the digital decimation filter module is used for carrying out digital filtering and down-sampling processing on the ith-round quantized signal to obtain an ith-round Nyquist rate output signal. The system can realize higher significant digits in shorter conversion time.

The invention relates to the technical field of integrated circuit design, in particular to a noise shaping assembly line successive approximation type analog-to-digital converter and a control method. Comprising a first stage including an auxiliary successive approximation analog-to-digital converter and a first stage voltage processing module; the second stage comprises a dual-channel noise shaping successive approximation type analog-to-digital converter and a loop filter; the input end of the residual amplifier is connected with the first-stage voltage processing module, and the output end of the residual amplifier is connected with the noise shaping successive approximation type analog-to-digital converter; the first input end of the digital code aligner is connected with the output end of the comparator of the auxiliary analog-to-digital converter, and the second input end of the digital code aligner is connected with the output end of the second-stage comparator. According to the invention, the analog-to-digital conversion speed can be accelerated, the influence of a zero point on a residual voltage amplification coefficient is reduced, the conversion time is shortened, and the input and output common-mode voltages of the time domain converter are stabilized.

An image compression device includes a discrete cosine transform (DCT) circuit, a quantization noise shaping (QNS) circuit, and an encoder circuit. The DCT circuit performs a DCT on original image data to generate first data. The QNS circuit performs QNS on block data in first data to determine, based on a first coefficient and a second coefficient of the block data, a QNS score of the first coefficient, and replace the first coefficient with the second coefficient when the QNS score is greater than zero so as to generate second data, wherein the second coefficient is obtained by decreasing an absolute value of the first coefficient. The encoder circuit encodes the second data to generate compressed image data.

The invention discloses a high-precision feed-forward noise shaping successive approximation analog-to-digital converter. The analog-to-digital converter comprises a first CDAC module, a second CDAC module, a first feed-forward capacitor, a second feed-forward capacitor, a first integrating capacitor, a second integrating capacitor, a first elimination capacitor, a second elimination capacitor, a dynamic amplifier module and a dynamic comparator module. By adopting the technical scheme of the invention, the sampling noise which cannot be optimized by noise shaping is suppressed, and a better precision effect is generated.

Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.

The invention discloses a decimal multi-modulus frequency divider circuit based on space-time averaging and phase interpolation technologies. The decimal multi-modulus frequency divider circuit comprises a third-order noise shaping modulation module, a dynamic element matching and phase selection module, a phase switching frequency divider module and a pipelined phase interpolation module. The third-order noise shaping modulation module is used for performing time averaging on the input frequency dividing ratio to generate an instantaneous frequency dividing ratio; the dynamic element matching and phase selection module is used for spatially averaging the instantaneous frequency dividing ratio and generating a frequency divider control word and a phase interpolator control word; the phase switching frequency divider module is used for generating a clock signal corresponding to a frequency dividing ratio according to the frequency divider control word; and the pipelined phase interpolation module is used for performing phase interpolation according to the clock signal to generate a final clock signal with an accurate phase. According to the embodiment of the invention, the mutual cooperation of the modules is utilized, the fusion of the space-time averaging technology and the phase interpolation technology is realized, and the limitation of the space-time averaging technology is improved.

The embodiment of the invention provides a noise shaping circuit and an analog-to-digital converter, which can be applied to the technical field of integrated circuits. The noise shaping circuit comprises a plurality of switches, a first capacitor, a second capacitor and a buffer connected between the first capacitor and the second capacitor, the plurality of switches are configured to respond to a switch control signal and alternatively enable one of the first capacitor and the second capacitor to serve as an integrating capacitor to be connected to the analog signal input end, so that the integrating capacitor provides an integrating voltage for the buffer based on a margin voltage provided by the analog signal input end and a capacitor voltage stored in the integrating capacitor; the other one of the first capacitor and the second capacitor is used as a storage capacitor, and the integral voltage flowing through the buffer is received and stored; the integrating capacitor is configured to output an integrating voltage to the output end of the noise shaping circuit, so that the digital logic circuit performs analog-to-digital conversion on the integrating voltage to obtain a margin voltage and provide the margin voltage to the analog signal input end.

The invention relates to the technical field of integrated circuit design, in particular to a multipath interleaving pipelined noise shaping analog-to-digital converter and a residual compensation method. The multipath interleaving pipelined noise shaping analog-to-digital converter comprises a first-stage analog-to-digital converter and a second-stage analog-to-digital converter. The first-stage analog-to-digital converter comprises a four-channel time-interleaved analog-to- The first-stage analog-to-digital conversion is used for acquiring an analog signal, sampling and converting the acquired analog signal, generating a residual error and amplifying the residual error; and the second-stage analog-to-digital conversion is used for acquiring the residual error processed by the first-stage analog-to-digital conversion, performing conversion, decoding and noise reduction on the residual error, and combining the residual error with the output result of the first-stage analog-to-digital conversion. The overall energy efficiency and the overall sampling rate of the analog-to-digital converter can be improved while high resolution is achieved, the noise requirement of a single-stage successive approximation type analog-to-digital converter comparator is lowered, and the problem that a successive approximation type analog-to-digital converter is low in conversion speed is solved.

The invention discloses a piecewise linear quantization mixed structure analog-to-digital converter with a noise shaping function, and belongs to the field of analog-to-digital converters, the analog-to-digital converter comprises an input control circuit, a nonlinear quantization circuit, a noise shaping modulation circuit, an output control circuit and a digital decimation filter circuit, the control circuit samples an input signal; the non-linear quantization circuit determines a non-linear section where an input signal is located and provides reference voltage for the noise shaping modulation circuit; the noise shaping modulation circuit is used for performing noise shaping and fine quantization on an input signal; the output control circuit combines the two parts of quantization output and generates a high-speed low bit code stream; the digital decimation filter circuit receives a high-speed code stream and generates a high-precision digital code through decimation filtering; according to the technology provided by the invention, suitable nonlinear quantization characteristics are provided according to different signal characteristics, and meanwhile, higher quantization precision and a wider dynamic range can be realized.

Methods and systems for tamper detection based on power network electrical characteristic by storing a reference electrical signature of a power distribution network comprising the integrated circuit, generating in the integrated circuit a current stimulus waveform by sigma-delta based noise shaping, and providing the waveform to the power distribution network comprising the integrated circuit, sampling the power distribution network with a voltage-to-digital converter in the integrated circuit and estimating based at least partially on the sampled power distribution network a response electrical signature of the power distribution network responsive to the stimulus waveform, comparing on the integrated circuit the estimated response electrical signature and the reference electrical signature, and triggering by the integrated circuit a penalty based on a comparison of the response electrical signature and the reference electrical signature.

The invention provides an incremental analog-to-digital converter based on passive noise shaping and a signal processing method, which can be applied to the technical field of quantization. The incremental analog-to-digital converter comprises: an input integrating circuit configured to generate a (j-1) th low-order integrated voltage according to an input signal from a signal input end; generating a kth high-order integral voltage according to an input signal; the passive amplification circuit is configured to obtain a kth gain voltage according to the kth high-order integral voltage based on a predetermined amplification coefficient; the passive noise shaping circuit is configured to perform passive integration on the kth high-order integration voltage to obtain kth passive integration voltage, and perform passive gain on the kth passive integration voltage by using the kth gain voltage to obtain kth high-order gain voltage; a quantization circuit configured to quantize the M1 low-order integral voltages in M1 periods, respectively, to generate M1 coarse quantization values; m2 high-order gain voltages are quantized in M2 periods respectively, and M2 fine quantized values are generated.

The invention discloses a high-precision photon digital-to-analog conversion system based on noise shaping, which is characterized in that a mode-locked laser generates an optical pulse sequence, optical pulses enter a dispersive medium, and periodic pulses are processed by using a fractional order Talbot effect, so that the pulse repetition frequency is improved; the Delta-Sigma (Delta Sigma) modulation module processes a preset target signal and shifts noise to a high frequency band based on an oversampling technology and noise shaping to realize conversion from an analog signal to a digital signal; the pulse signal with the repetition frequency increased is input into the electro-optical modulation module to serve as a sampling source, and a digital signal generated by the delta-sigma modulation module is input into the electro-optical modulation module for intensity modulation, so that the optical pulse carries the characteristics of frequency change and noise shaping of the signal, and fusion from electric signal modulation to optical signal modulation is completed; inputting the pulse signal after electro-optical modulation into a photoelectric detector, and converting an optical signal into an electric pulse signal; the electric pulse signal enters a filtering module, noise in the electric signal is filtered out, and an analog signal is obtained.

A passive noise-shaping successive-approximation analog-to-digital converter (SAR ADC) includes a SAR ADC circuit and a passive noise-shaping circuit. The SAR ADC circuit performs conversion upon an analog input signal and extracts residue at an end of the conversion. The passive noise-shaping circuit processes the residue and feeds a processed residue back to the SAR ADC circuit. The passive noise-shaping circuit includes at least one passive element with tunable capacitance that is used to perform residue amplification.

An image compression device includes a discrete cosine transform (DCT) circuit, a quantization noise shaping (QNS) circuit, and an encoder circuit. The DCT circuit performs a DCT on original image data to generate first data. The QNS circuit performs QNS on block data in first data to determine, based on a first coefficient and a second coefficient of the block data, a QNS score of the first coefficient, and replace the first coefficient with the second coefficient when the QNS score is greater than zero so as to generate second data, wherein the second coefficient is obtained by decreasing an absolute value of the first coefficient. The encoder circuit encodes the second data to generate compressed image data.

The application provides a new hybrid nested noise shaping architecture suitable for noise shaping SAR ADC, which adopts a dynamic working closed-loop cascode FIA as a residual amplifier to reduce power consumption by eliminating the static current of the amplifier and removing the gain calibration circuit; the shaping architecture performs fourth-order noise shaping through the nested second-order CIFF and second-order EF noise shaping loops to achieve high precision in noise shaping at the same oversampling rate, and integrates the sampling noise cancellation (SNC) method to reduce the capacitance of the sampling capacitor to save chip area; the architecture adopts a closed-loop cascode FIA as a residual amplifier and CIFF and EF as noise shaping loops to solve the problem that the traditional noise shaping SAR ADC is difficult to simultaneously achieve high precision and low power consumption. In addition, the sampling KT / C noise cancellation (SNC) technology is integrated to reduce the capacitance of the sampling capacitor and save chip area.

The present application discloses a joint stereo audio coding and decoding method and device, belonging to the field of audio coding and decoding technology. The method mainly includes: encoding the Bluetooth audio of the left and right channels to the time domain noise shaping module according to the standard Bluetooth coding steps, respectively, to obtain the left channel spectral coefficient and the right channel spectral coefficient corresponding to the left and right channels respectively; jointly encoding the left channel spectral coefficient and the right channel spectral coefficient, to obtain the left channel joint coding data corresponding to the left channel and the right channel joint coding data corresponding to the right channel; and performing the remaining coding steps on the left channel joint coding data and the right channel joint coding data according to the standard Bluetooth coding steps, respectively, to obtain the code streams corresponding to the left channel and the right channel respectively. Under the premise of ensuring the sound quality, the present application makes full use of the correlation between the stereo dual channels, improves the efficiency of stereo coding, greatly reduces the bit rate, saves the Bluetooth air bandwidth, thereby reducing interference and improving the user experience.

The invention relates to the technical field of sequential control, and discloses a sequential logic control circuit for a noise shaping SAR ADC (Synthetic Aperture Radar Analog to Digital Converter), which comprises an analog signal acquisition circuit for receiving and preprocessing an initial input signal; the noise shaping circuit is used for performing frequency spectrum shaping on quantization noise in the analog signal and generating the analog signal subjected to noise shaping; the successive approximation type analog-to-digital converter is used for performing bit-by-bit comparison with the analog signal subjected to noise shaping and gradually completing conversion from the analog signal to the digital signal from the highest bit to the lowest bit; and the clock control circuit is used for coordinating sequential logic among the analog signal acquisition circuit, the noise shaping circuit and the successive approximation type analog-to-digital converter. According to the method, frequency spectrum remodeling is carried out on the quantization noise in the signal, the signal-to-noise ratio of the signal is remarkably improved on the premise that the hardware complexity is not additionally increased, and then interference of the noise on follow-up analog-to-digital conversion is reduced.

The application discloses a bone conduction speech coding method, a coding and decoding method, a device, a medium and equipment, and belongs to the technical field of audio coding and decoding. The coding method comprises the following steps: updating a bandwidth detection parameter table in advance; updating a time domain noise shaping coding coefficient table in advance; in an LC3 audio coding process, the bone conduction speech is coded by using the updated bandwidth detection parameter table and the updated time domain noise shaping coding coefficient table, and a noise level estimation process of the bone conduction speech is performed on a bone conduction speech frequency band, so that the coding of the bone conduction speech is completed. The bandwidth detection parameter table and the time domain noise shaping coding coefficient table in the LC3 encoder are updated, so that when the LC3 encoder codes the bone conduction speech, the low-frequency part of the bone conduction speech can be recognized and corresponding coding processing can be performed, the coding of the bone conduction speech is realized, and the application range of the LC3 audio coding and decoding device is widened.

The present application relates to aerospace, geological exploration and micro-light detection fields, and particularly relates to a reconfigurable noise shaping successive approximation register analog-to-digital converter, which comprises a sampling unit, a capacitive digital-to-analog converter array, a comparison unit, a passive noise shaping feedback unit, a successive approximation control unit, an output unit and a mode control unit. The sampling unit samples and holds an input signal, and the capacitive digital-to-analog converter array outputs to the comparison unit. The comparison unit compares its output with a common-mode reference voltage, and the result is sent to the successive approximation control unit. In the noise shaping mode, the successive approximation control unit additionally generates an integral clock timing to activate the passive feedback unit, samples a residual voltage and feeds back to the digital-to-analog converter array. The output unit drives the conversion result to a lower circuit. The present application also contains a method. The present application can effectively suppress the capacitive parasitic effect and low-frequency noise, realize flexible switching between high-speed conventional mode and high-resolution noise shaping mode, and significantly improve the system performance.

The invention provides a coherent optical communication method and a coherent optical communication system, and the method comprises the steps: carrying out the digital signal processing including error feedback noise shaping of a digital signal, and obtaining a pre-compensated digital signal; sequentially performing digital-to-analog conversion and signal amplification on the signal to obtain an amplified first analog signal; the method comprises the following steps: receiving a signal sent by a standard single-mode optical fiber, performing coherent light modulation on the signal to obtain a modulated light signal, and transmitting the light signal to a receiving device based on the standard single-mode optical fiber, so that the receiving device generates a corresponding digital signal according to the light signal and performs digital signal processing including self-adaptive equalization based on Stokes domain depolarization to obtain a demodulated digital signal. According to the invention, on the basis that the coherent light communication cost is reduced and the calculation complexity is not obviously improved, the quality and the signal-to-noise ratio of the transmitted signal are effectively improved, the processing efficiency of the received digital signal can be improved, and thus the high-quality and high-efficiency transmission of the signal suitable for the coherent light communication scene can be realized.

The invention discloses a hybrid level crossing analog-to-digital converter circuit integrating a successive approximation type analog-to-digital converter and an event-driven analog-to-digital converter. The circuit is composed of a level cross analog-to-digital conversion module LC ADC, a logic module LOGIC and a noise shaping successive approximation analog-to-digital converter module NSSAR ADC. The architecture effectively integrates the advantages of two converters, and has the characteristic of ultra-low power consumption of a level crossing analog-to-digital converter while keeping the high precision characteristic of a successive approximation type analog-to-digital converter. The level crossing analog-to-digital conversion module LC ADC does not participate in quantization of input signals and is only used as a pre-detection circuit of level crossing, and the noise shaping successive approximation analog-to-digital conversion module NSSAR ADC is used for completing signal processing actions such as comparison, quantization and output, so that the precision of the output signals is not restricted by the level crossing analog-to-digital conversion module LC ADC. The hybrid architecture can meet the requirements of low-power-consumption and high-precision acquisition of signals of the modern mobile Internet of Things.

The invention provides a weak signal noise shaping accumulation detection system and method, and the system comprises a noise generator which is used for generating noise with a set amplitude; the first input end of the summator is used for receiving a weak signal to be detected, the second input end of the summator is connected with the noise generator, and the summator is used for superposing the weak signal and the noise to obtain a synthetic signal; the input end of the analog-to-digital converter is connected with the output end of the summator, and the analog-to-digital converter is used for converting the synthesized signal into a digital signal; the input end of the signal accumulation and detection module is connected with the output end of the analog-to-digital converter, and the signal accumulation and detection module is used for sampling and accumulating the digital signals for multiple times so as to extract information of weak signals. According to the monitoring system provided by the invention, the detection of weak signals lower than the ADC quantization threshold is realized by superposing the noise reservation information, and the structure is simple and clear and easy to realize.