55 results about "Noise shaping" patented technology

The invention relates to an integrator circuit for eliminating thermal noise and a Delta-sigma modulator, and belongs to the technical field of electronic signal processing, the modulator comprises at least two stages of integrators, a quantizer, a feedback DAC and an adder; the integrator comprises an integrator circuit, and the integrator circuit comprises a sampling module for sampling an input signal source; the double-path multi-phase clock control pre-amplification auxiliary storage circuit module alternately samples and stores thermal noise voltage and offset voltage; the integral amplifier is used for amplifying a signal output by the double-path multi-phase clock control pre-amplification auxiliary storage circuit module; and the integrating capacitor is connected between the integrating amplifier and the two-way multi-phase clock control pre-amplification auxiliary storage circuit module, and feeds back the signal after integration processing to the two-way multi-phase clock control pre-amplification auxiliary storage circuit module to realize signal modulation and noise shaping. The thermal noise introduced in the sampling process is effectively reduced, and the area of the whole chip is reduced while the signal-to-noise ratio is improved.

The invention provides an incremental analog-to-digital converter based on passive noise shaping and a signal processing method, which can be applied to the technical field of quantization. The incremental analog-to-digital converter comprises: an input integrating circuit configured to generate a (j-1) th low-order integrated voltage according to an input signal from a signal input end; generating a kth high-order integral voltage according to an input signal; the passive amplification circuit is configured to obtain a kth gain voltage according to the kth high-order integral voltage based on a predetermined amplification coefficient; the passive noise shaping circuit is configured to perform passive integration on the kth high-order integration voltage to obtain kth passive integration voltage, and perform passive gain on the kth passive integration voltage by using the kth gain voltage to obtain kth high-order gain voltage; a quantization circuit configured to quantize the M1 low-order integral voltages in M1 periods, respectively, to generate M1 coarse quantization values; m2 high-order gain voltages are quantized in M2 periods respectively, and M2 fine quantized values are generated.

The application provides a new hybrid nested noise shaping architecture suitable for noise shaping SAR ADC, which adopts a dynamic working closed-loop cascode FIA as a residual amplifier to reduce power consumption by eliminating the static current of the amplifier and removing the gain calibration circuit; the shaping architecture performs fourth-order noise shaping through the nested second-order CIFF and second-order EF noise shaping loops to achieve high precision in noise shaping at the same oversampling rate, and integrates the sampling noise cancellation (SNC) method to reduce the capacitance of the sampling capacitor to save chip area; the architecture adopts a closed-loop cascode FIA as a residual amplifier and CIFF and EF as noise shaping loops to solve the problem that the traditional noise shaping SAR ADC is difficult to simultaneously achieve high precision and low power consumption. In addition, the sampling KT / C noise cancellation (SNC) technology is integrated to reduce the capacitance of the sampling capacitor and save chip area.

The invention relates to the technical field of sequential control, and discloses a sequential logic control circuit for a noise shaping SAR ADC (Synthetic Aperture Radar Analog to Digital Converter), which comprises an analog signal acquisition circuit for receiving and preprocessing an initial input signal; the noise shaping circuit is used for performing frequency spectrum shaping on quantization noise in the analog signal and generating the analog signal subjected to noise shaping; the successive approximation type analog-to-digital converter is used for performing bit-by-bit comparison with the analog signal subjected to noise shaping and gradually completing conversion from the analog signal to the digital signal from the highest bit to the lowest bit; and the clock control circuit is used for coordinating sequential logic among the analog signal acquisition circuit, the noise shaping circuit and the successive approximation type analog-to-digital converter. According to the method, frequency spectrum remodeling is carried out on the quantization noise in the signal, the signal-to-noise ratio of the signal is remarkably improved on the premise that the hardware complexity is not additionally increased, and then interference of the noise on follow-up analog-to-digital conversion is reduced.

The application discloses a bone conduction speech coding method, a coding and decoding method, a device, a medium and equipment, and belongs to the technical field of audio coding and decoding. The coding method comprises the following steps: updating a bandwidth detection parameter table in advance; updating a time domain noise shaping coding coefficient table in advance; in an LC3 audio coding process, the bone conduction speech is coded by using the updated bandwidth detection parameter table and the updated time domain noise shaping coding coefficient table, and a noise level estimation process of the bone conduction speech is performed on a bone conduction speech frequency band, so that the coding of the bone conduction speech is completed. The bandwidth detection parameter table and the time domain noise shaping coding coefficient table in the LC3 encoder are updated, so that when the LC3 encoder codes the bone conduction speech, the low-frequency part of the bone conduction speech can be recognized and corresponding coding processing can be performed, the coding of the bone conduction speech is realized, and the application range of the LC3 audio coding and decoding device is widened.

The present application relates to aerospace, geological exploration and micro-light detection fields, and particularly relates to a reconfigurable noise shaping successive approximation register analog-to-digital converter, which comprises a sampling unit, a capacitive digital-to-analog converter array, a comparison unit, a passive noise shaping feedback unit, a successive approximation control unit, an output unit and a mode control unit. The sampling unit samples and holds an input signal, and the capacitive digital-to-analog converter array outputs to the comparison unit. The comparison unit compares its output with a common-mode reference voltage, and the result is sent to the successive approximation control unit. In the noise shaping mode, the successive approximation control unit additionally generates an integral clock timing to activate the passive feedback unit, samples a residual voltage and feeds back to the digital-to-analog converter array. The output unit drives the conversion result to a lower circuit. The present application also contains a method. The present application can effectively suppress the capacitive parasitic effect and low-frequency noise, realize flexible switching between high-speed conventional mode and high-resolution noise shaping mode, and significantly improve the system performance.

The invention discloses a hybrid level crossing analog-to-digital converter circuit integrating a successive approximation type analog-to-digital converter and an event-driven analog-to-digital converter. The circuit is composed of a level cross analog-to-digital conversion module LC ADC, a logic module LOGIC and a noise shaping successive approximation analog-to-digital converter module NSSAR ADC. The architecture effectively integrates the advantages of two converters, and has the characteristic of ultra-low power consumption of a level crossing analog-to-digital converter while keeping the high precision characteristic of a successive approximation type analog-to-digital converter. The level crossing analog-to-digital conversion module LC ADC does not participate in quantization of input signals and is only used as a pre-detection circuit of level crossing, and the noise shaping successive approximation analog-to-digital conversion module NSSAR ADC is used for completing signal processing actions such as comparison, quantization and output, so that the precision of the output signals is not restricted by the level crossing analog-to-digital conversion module LC ADC. The hybrid architecture can meet the requirements of low-power-consumption and high-precision acquisition of signals of the modern mobile Internet of Things.

The invention provides a weak signal noise shaping accumulation detection system and method, and the system comprises a noise generator which is used for generating noise with a set amplitude; the first input end of the summator is used for receiving a weak signal to be detected, the second input end of the summator is connected with the noise generator, and the summator is used for superposing the weak signal and the noise to obtain a synthetic signal; the input end of the analog-to-digital converter is connected with the output end of the summator, and the analog-to-digital converter is used for converting the synthesized signal into a digital signal; the input end of the signal accumulation and detection module is connected with the output end of the analog-to-digital converter, and the signal accumulation and detection module is used for sampling and accumulating the digital signals for multiple times so as to extract information of weak signals. According to the monitoring system provided by the invention, the detection of weak signals lower than the ADC quantization threshold is realized by superposing the noise reservation information, and the structure is simple and clear and easy to realize.

The invention discloses a noise shaping SAR ADC (Synthetic Aperture Radar Analog to Digital Converter) circuit structure based on error feedback, which relates to the technical field of integrated circuit design and comprises a time sequence control circuit used for generating and coordinating clock signals and control time sequences required by all modules; the analog signal input end is used for receiving an analog signal to be converted and is coupled to the noise shaping SAR ADC module; the noise shaping SAR ADC module is used for carrying out successive approximation type analog-to-digital conversion on the held sampling signal, outputting a digital code, integrating a noise shaping function and extracting a quantization error signal; the error feedback circuit is used for carrying out integration and gain adjustment processing on the quantization error signal and carrying out feedback superposition on the processed error feedback signal; and the digital output end is used for outputting a final digital signal after noise shaping and low-pass filtering. According to the invention, high-precision conversion is realized while the advantages of simplicity and low power consumption of the SAR ADC are maintained, and the applicability of the SAR ADC in high-end application is widened.

The invention provides a second-order noise shaping SAR ADC circuit and electronic equipment, and the circuit comprises a sampling and quantification module which is used for completing the sampling and quantification of an input signal of an nth conversion period when being controlled by a time sequence, and outputting a digital code and a residual signal; the integral amplifier is connected with the sampling quantization module and is used for accessing the residual signal under the control of a first time sequence signal, integrating the residual signal and storing an integration result in a group of feedback capacitors of the integral amplifier; and the integral amplifier is also used for accessing the voltage stored on the group of feedback capacitors under the control of a second time sequence signal so as to carry out secondary integration, and the output end of the integral amplifier is connected to the input coupling node of the sampling quantization module so as to provide correction voltage participating in the quantization process of the (n + 1) th conversion period. According to the invention, high energy efficiency and high-order noise shaping capability can be considered at the same time.

A low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) device for sensor interface is disclosed. The device includes a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC and a second stage comprising a voltage-controlled oscillator (VCO)-ADC.

For example, an apparatus may include an input to receive digital radar Receive (Rx) information corresponding to radar Rx signals, the digital radar Rx information having a first number-of-bits-per-sample; and a noise-shaping quantizer configured to generate quantized radar Rx information by quantizing the digital radar Rx information. For example, the quantized radar Rx information may have a second number-of-bits-per-sample less than the first number-of-bits-per-sample. For example, the noise-shaping quantizer may be configured to generate the quantized radar Rx information having a non-uniform quantization noise spectrum, which has a non-uniform distribution in a frequency domain. For example, the apparatus may include an output to provide the quantized radar Rx information.

The application belongs to the technical field of integrated circuits, and particularly relates to a fourth-order delta-sigma modulator design method and system based on passive stacking. The application cascades a quantizer after a third-order active loop filter, and couples capacitors in parallel on the plate of a capacitor array of the quantizer. Sampling and quantization are performed in each cycle. The quantizer quantizes the output of the current loop filter. After quantization, the plate of the capacitor array naturally forms a residual voltage and stores the coupling capacitors. In the noise injection phase of the next cycle, the quantization error stored in the coupling capacitors in the last cycle is injected into the input end of the quantizer through charge redistribution, is weighted and superimposed with the intermediate signal to form the input voltage of the quantizer, and the main path attenuation coefficient and the coupling path gain coefficient are obtained through charge conservation analysis. A gain compensation factor is preset in the front-stage active integrator to offset signal attenuation, and the capacitor ratio is optimized to realize fourth-order noise shaping. The application does not require additional active circuits, has small area and low power consumption, and improves the signal-to-noise ratio.

The application relates to the technical field of integrated circuit design, and particularly discloses a full-dynamic Delta-Sigma modulator circuit which comprises a dynamic integrator, a noise shaping analog-digital converter and a dynamic element matching calibration circuit, the input end of the dynamic integrator is connected with an analog input signal and a feedback signal respectively, the input end of the noise shaping analog-digital converter is connected with the analog input signal and the output end of the dynamic integrator respectively, and the output end of the noise shaping analog-digital converter is connected with the input end of the dynamic element matching calibration circuit; the dynamic integrator is used for integrating a signal obtained by subtracting the feedback signal from the analog input signal and outputting an integrated signal; the noise shaping analog-digital converter is used for quantizing a signal obtained by adding the integrated signal and the analog input signal and outputting a quantized digital signal; and the dynamic element matching calibration circuit is used for calibrating the quantized digital signal and outputting the feedback signal. The application can eliminate the static current of the modulator and realize a very high energy efficiency ratio.

According to the high-signal-quality physical layer encrypted free space optical communication method and system provided by the invention, quantization noise can be effectively controlled through DSM modulation, high-frequency noise is removed, so that high quality and low distortion of signals are kept in the transmission process, and especially in long-distance and severe-environment communication, the high-quality and low-distortion performance of the signals is ensured. And the signal stability can be obviously improved. Wherein in the physical layer encryption process of quantum noise stream encryption and the like, quantum noise or random phase jump is used as a means for generating an encrypted signal to introduce certain noise, the noise shaping characteristic of DSM modulation plays an important role, the noise is concentrated in a high-frequency area to reduce low-frequency interference caused by the quantum noise, and the quantum noise stream encryption is realized. The signal quality is optimized, and the bit error rate is reduced. Interference caused by quantum noise and external environment factors can be effectively eliminated in the signal transmission process, and therefore the transmission stability of a system and the reliability of signals are improved.

A digital-to-time converter circuit includes a scrambling and noise shaping circuit, a digital-to-analog converter (DAC), and a buffer circuit. The scrambling and noise shaping circuit includes an input and an output. The input is coupled to a delay input terminal. The scrambling and noise shaping circuit is configured to generate a residue value signal that scrambles and noise shapes a mismatch error. The DAC includes an input and an output. The input of the DAC is coupled to the output of the scrambling and noise shaping circuit. The DAC is configured to generate a residue timing signal based on the residue value signal that scrambles and noise shapes the mismatch error. The buffer circuit includes an input and an output. The input of the buffer circuit is coupled to the output of the DAC. The output of the buffer circuit is coupled to a signal output terminal.

This invention discloses a dual passive noise shaping and correction method for high-precision successive approximation ADCs. It combines noise shaping technology with a correction algorithm. Within a short period after chip power-on, using a limited correction DAC capacitor array and noise shaping technology, it achieves higher-precision correction codes for SAR ADC capacitor mismatch and comparator offset voltage. In normal operating mode, this invention again incorporates noise shaping technology, adding the correction codes to the main DAC in analog form, reducing the impact of non-ideal factors. This invention reuses sampling integration capacitors, resulting in a simple structure. With minimal power consumption, it significantly improves correction accuracy and increases the overall signal-to-noise ratio and spurious-free dynamic range, thereby enhancing the overall efficiency of the SAR ADC.

Embodiments of circuits and methods are described below that may provide a modulator that has an enhanced signal-to-quantization-noise ratio (SQNR) for a given sampling frequency and bandwidth or that may enable a reduced sampling frequency for a target SQNR and bandwidth. In one or more embodiments, a modulator circuit may include a first modulator including an input and a first output, and including one or more feed-forward components; an output circuit including an input coupled to the first output and including an output, the output circuit including one of a noise-shaping circuit, a noise-shaped quantizer circuit, or an integrator and feed-forward component; and coefficients of the one or more feed-forward components of the first modulator and a transfer function of the output circuit provide a higher-order modulator with a first-order roll-off at high out-of-band frequencies.

The invention discloses a third-order noise shaping successive approximation analog-to-digital converter, and belongs to the technical field of analog-to-digital converters. Comprising four parts, namely a sampling and holding and DAC circuit, a third-order loop filter, a voltage comparator and a successive approximation logic circuit, and the sampling and holding and DAC circuit is connected with an input voltage signal and the third-order loop filter, and is controlled by the successive approximation logic circuit. The third-order loop filter performs delay integral operation on a residual signal of a previous period, introduces a plurality of time sequence control switch capacitor arrays to perform charge redistribution operation, and couples an input voltage signal and a weighted residual signal generated by the third-order loop filter to the input end of the voltage comparator through a capacitor; a noise shaping technology is introduced in the voltage comparison and conversion process, and the voltage is output to an analog-digital conversion circuit to complete the whole circuit conversion work; the device is simple in structure and has good PVT characteristics.

Embodiments of the present application provide a signal processing method, circuit and chip, and an electronic device. The signal processing method comprises: processing an inputted digital signal on the basis of a PWM synchronous clock signal to obtain an analog differential signal; performing chopping processing on an intermediate common-mode voltage signal on the basis of a chopping clock signal to obtain a common-mode voltage signal, wherein the intermediate common-mode voltage signal is used for stabilizing a common-mode voltage of the analog differential signal, and an edge of a pulse comprised in the chopping clock signal and an edge of a pulse comprised in the PWM synchronous clock signal are not aligned in timing; performing noise shaping on the analog differential signal and then performing PWM to obtain a PWM signal; and performing voltage domain conversion on the PWM signal to obtain an output signal. The present solution can improve performance of signal processing.

The application provides a new error feedback noise shaping SAR ADC circuit structure based on Buffer-in-loop, which comprises a noise feedback connection connected to a CDAC capacitor input end and an input signal sampling capacitor close to a sampling switch side, the noise feedback connection comprises a gain amplifier and a residual voltage sampling capacitor, and the residual voltage sampling capacitor is connected with the gain amplifier output through a switch; the CDAC capacitor is connected with the residual voltage sampling capacitor through a switch; the input end of the gain amplifier is connected with the output end of the input signal sampling capacitor; a voltage input end is connected with the input end of a unit gain buffer, the output end of the unit gain buffer is connected with the input signal sampling capacitor; and the output end of the CDAC capacitor is connected with the unit gain buffer input end in series through a switch. Through decoupling of the CDAC and the sampling capacitor in the NS-SAR ADC loop, noise shaping is realized by using the noise feedback connection, and the noise shaping is fused with other shaping modes.

The present invention relates to a successive approximation register (SAR) analog-to-digital converter and the SAR analog-to-digital converter according to an example embodiment includes an input unit including at least one SAR capacitor; a recycling integrator connected to the input unit and including k integration capacitors configured to store the respective residue information generated in an integration process performed k times, respectively, (where k denotes a positive integer of 2 or more) using a single amplifier; a comparator connected to an output terminal of the recycling integrator; and a SAR controller connected to an output terminal of the comparator and configured to generate a digital signal corresponding to output of the comparator.

Delta-sigma analog-to-digital converter (ADC), which includes the following: a delta-sigma modulator that includes the following: a first summing node for summing an analog input signal and a feedback signal and outputting a first summed analog signal; a loop filter that filters the first summed analog signal according to a noise shaping function and outputs a filtered analog signal; a quantizer that quantizes the filtered analog signal and outputs a quantized output signal; a feedback path that connects an output of the quantizer to an input of the summing node; and a feedback DAC in the feedback path that receives the quantized output signal and converts the quantized output signal into the feedback signal that is delivered to the first summing node, and wherein the feedback DAC includes a switch-capacitor circuit, wherein the switch-capacitor circuit includes several unit elements, wherein the switch-capacitor circuit is configured to selectively connect each of the respective unit elements into different connection states depending on a DAC code of the quantized output signal, wherein the different connection states include the following: a first connection state in which the respective unit element is connected to deliver a first signal to an output of the feedback DAC, wherein the first connection state corresponds to a first signal level; a second connection state in which the respective unit element is connected to supply a second signal to the output of the feedback DAC, the second connection state corresponding to a second signal level; and a third connection state in which the respective unit element is disconnected from the output of the feedback DAC, wherein the third connection state corresponds to a third signal level characterized by the fact that The switching network is configured in the third connection state to connect the unit element to a common-mode voltage.

The application discloses a noise shaping analog-digital converter circuit, which comprises a residual voltage extraction amplification circuit, a residual voltage integration circuit and an analog-digital conversion unit. The residual voltage extraction amplification circuit is connected with the analog-digital conversion unit through the residual voltage integration circuit. In the overall structure, the residual voltage extraction amplification circuit is connected with a CDAC top plate, the residual voltage integration circuit performs integral processing on the residual voltage and outputs the residual voltage to the analog-digital conversion circuit to complete the overall circuit conversion work. The application adopts a combination of a dynamic amplifier and a switched capacitor to realize noise shaping, and has the advantages of small static power consumption, simple structure, good PVT stability and strong noise shaping capacity.

Split low noise amplifier (LNA) architectures providing an improved tradeoff between the noise figure (NF) and the output-to-output isolation are disclosed. The described LNAs include cascode transistors in two amplification paths and an inductive element including a pair of inductors and a common inductor. The inductance values of the inductors and the common inductor can be selected to obtain an improved tradeoff between the NF and isolation while meeting the output matching conditions.

The invention relates to a continuous time three-order Sigma-delta ADC (Analog to Digital Converter) modulator. The continuous time three-order Sigma-delta ADC modulator comprises a loop filter and a quantizer, the loop filter adopts a first-order differential active integrator, and an input signal is subjected to first-order integration of the first-order differential active integrator to generate an output signal; the quantizer comprises a passive second-order noise shaping and feedback DAC (Digital-to-Analog Converter), and the passive second-order noise shaping performs second-order passive noise shaping and quantization to realize second-order integration and third-order integration of the modulator and output a digital signal; the feedback DAC converts the digital signal into a continuous-time analog signal, the analog signal is fed back to the input end of the loop filter, the analog signal is subtracted from the output of the feedback DAC, and then the analog signal enters the loop filter to be accumulated and filtered. By adopting the first-order differential active integrator and combining passive second-order noise shaping, second-order and third-order integrals are realized, and the method has the advantages that the signal to quantization noise ratio is improved, the loop stability is ensured, and the circuit complexity and power consumption are reduced.

The invention relates to the technical field of wireless communication and digital signal processing, and provides a modulation signal receiving and transmitting system and method based on IQ domain maximum ratio merging, and particularly, a Delta-Sigma modulation technology is adopted at a transmitting end, a high-order modulation signal is converted into a low bit stream, and the precision requirement for a data converter is remarkably reduced; an IQ domain maximum ratio merging mechanism is introduced at a receiving end, after IQ imbalance is corrected through digital preprocessing, dynamic weighted merging is carried out according to the signal-to-noise ratio of each receiving branch, and diversity gain is effectively utilized. Through collaborative design of the transmitting end and the receiving end, the signal-to-noise ratio of a combined signal can be remarkably improved and the influence of channel fading and noise can be effectively suppressed under high-frequency and long-distance transmission conditions, so that the signal-to-noise ratio of a Delta-Sigma modulation signal can be effectively improved on the premise of ensuring that the noise shaping characteristic of the Delta-Sigma modulation signal is not destroyed, and the signal-to-noise ratio of the Delta-Sigma modulation signal can be effectively improved. And the demodulation reliability and the overall robustness of the system are greatly enhanced.

Methods, systems, and devices for wireless communications are described. A transmitting device may determine channel quality, and may shape frequency domain noise (e.g., crest factor reduction (CFR) related noise) to locations in which channel quality is poor. For example, by shaping channel noise to frequency resources with poor channel quality (e.g., instead of uniformly distributing such channel noise), transmissions may be more reliable, and quality on other frequency resources may be improved (e.g., without negatively impacting the quality of communications via frequency resources that already have a low channel quality), resulting in improved dynamic range of the signal (e.g., peak to average power ratio (PAPR)), which means that power efficiency is improved.

Disclosed are a power-efficient continuous-discrete time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement and an operation method thereof. The power-efficient continuous-discrete time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement proposed in the present invention comprises: a continuous-time capacitance-to-voltage converter which reduces a total noise bandwidth by using anti-aliasing characteristics, and converts an input capacitor value into a voltage; a discrete-time switched-capacitor integrator which receives the voltage, increases power efficiency by using a floating inverter amplifier (FIA), and performs an integration operation; a second-order noise-shaping SAR ADC which quantizes an output of the discrete-time switched-capacitor integrator; and a DSM C-DAC which provides third-order noise-shaping characteristics, increases resolution, and constitutes a DSM loop.

A two-stage pipeline delta-sigma modulator, by extracting the residual signal of the overall first-stage delta-sigma loop, amplifying and leading to the input end of the second-stage delta-sigma loop module, and finally directly subtracting the digital outputs of the two-stage delta-sigma loop modules through a weighted subtractor to obtain the final output of the modulator. The two-stage pipeline delta-sigma modulator avoids the noise leakage problem caused by the mismatch between the analog and digital filters in the traditional double-loop multi-stage noise shaping (MASH) architecture delta-sigma modulator, greatly reducing the precision requirement for the analog domain coefficients.