46 results about "Ramp generator" patented technology

Circuits are disclosed for controlling voltage regulators. In general, one aspect disclosed features an electric circuit comprising: a digital ramp generator configured to generate a digital voltage ramp; a digital low-pass filter having an input electrically coupled to an output of the digital ramp generator and configured to low-pass filter the digital voltage ramp; a digital-to-analog converter having an input electrically coupled to an output of the digital low-pass filter and configured to generate an analog control signal based on the filtered digital voltage ramp; and a voltage regulator having an input electrically coupled to an output of the digital-to-analog converter and configured to regulate an output voltage based on the analog control signal and an input voltage of the voltage regulator.

This invention discloses a high-precision ramp generator and a two-step single-slope analog-to-digital converter. The ramp generator includes a bandgap reference source circuit, a voltage-to-current conversion circuit, a weighted current DAC current source array, a charge / discharge current regulation circuit, a mode switching circuit, and a bias circuit. In this invention, the quantization process of the ramp generator is decomposed into two stages: coarse quantization and fine quantization, significantly reducing quantization time. Furthermore, a single output stage can combine a DAC-type ramp generator and a capacitor-integrating ramp generator, saving area and power consumption in chip design, improving the compatibility of the ramp generator, solving the linearity and stability problems introduced by stepped ramps in high-speed, high-precision applications, and reducing design complexity.

A ramp generator for generating a ramp signal from an image sensor is disclosed. The ramp generator includes a bias voltage generator configured to generate a bias voltage, and a plurality of ramp cells configured to generate a ramp signal based on the bias voltage. Each of the plurality of ramp cells includes a local sampling circuit configured to adjust a sampling timing point of the bias voltage.

This invention provides a circuit and method for sampling and transmitting telemetry data from a cochlear implant, belonging to the field of telemetry technology for cochlear implants. The method amplifies the analog signal under test using a programmable gain amplifier, converts the signal into a pulse width signal using a voltage ramp generator and comparator, and then generates a short-duration step signal on the coil via an output driver to form a ringing pattern. An external device detects the interval between the step signals to reconstruct the signal magnitude. This invention eliminates the need for an analog-to-digital converter, significantly reducing power consumption and chip area, and improving data transmission efficiency. It is suitable for telemetry systems in various implantable medical devices such as cochlear implants. This invention significantly reduces the power consumption and layout area of ​​the implanted chip and shortens the single data transmission time to 48μs, improving efficiency by approximately 10 times, making it suitable for low-power implantable devices such as cochlear implants.

An image sensor including: a pixel array including first to N-th pixel circuits to generate first to N-th pixel signals; an ADC connected to the pixel circuits; a system clock generator to generate a system clock signal; an internal clock generator to generate first to N-th clock signals and (N+1)-th to 2N-th clock signals based on the system clock signal; a ramp generator to generate first to N-th ramp signals based on the first to N-th clock signals; and a counter clock generator to generate first to N-th counter clock signals based on the (N+1)-th to 2N-th clock signals, the ADC includes: a comparator to generate first to N-th comparison signals based on comparison operations of the first to N-th pixel signals and the first to N-th ramp signals; and a counter to generate first to N-th digital signals based on the comparison signals and the counter clock signals.

An image sensing apparatus includes: a pixel array including a plurality of pixels connected to a plurality of row lines and a plurality of column lines, and configured to output a plurality of pixel signals through the plurality of column lines; a ramp generator configured to generate a first ramp signal and a second ramp signal; an analog-to-digital converter (ADC) configured to convert the plurality of pixel signals into digital signals in response to the first ramp signal and the second ramp signal; and a column line controller configured to selectively connect the plurality of column lines to the ADC.

An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.

A voltage ramp generator includes unit cells (331) electrically connected in parallel. Each unit cell switches between an on-state and an off-state in response to a cell-specific select signal (S1-Sn). A current mirror circuit (350) copies a reference current controlled by the unit cells at a predefined current ratio into a first detector current flowing in a first detection branch. An error detection circuit (390) generates an active first error signal (ERR) if the first detector current falls below a lower threshold current or exceeds an upper threshold current.

The application discloses a comparator, an image sensor readout circuit and a readout method, the comparator is used for receiving a ramp signal from a ramp generator and receiving an output signal from a dual conversion gain pixel circuit, the comparator comprises a first differential input pair tube and a second differential input pair tube in parallel, the comparator receives the ramp signal and a low conversion gain reset signal or a low conversion gain pixel signal through the first differential input pair tube to output a comparison signal, and the comparator receives the ramp signal and a high conversion gain pixel signal or a high conversion gain reset signal through the second differential input pair tube to output a comparison signal. The application realizes frame rate doubling under the condition that the number of comparators used in the image sensor is unchanged.

A readout analog-to-digital converter (ADC) circuit system converts analog image signals received by bit lines into digital signals through an ADC comparator and presets a presettable ramp driver and an image sensing system using the same. The ADC comparator compares the image signal voltage at the first input with the ramp voltage at the second input to trigger the latch and cause the ADC to output a digital signal. A pixel voltage is coupled to one comparator at a first input of the one comparator only through a sampling capacitor. The ramp generator generates a global ramp voltage as an input to the plurality of presettable ramp drivers. A ramp driver may be preset to output a buffered ramp voltage to simultaneously drive the plurality of ADC comparators at a second input of the plurality of ADC comparators. A model circuit of the presettable ramp driver presents a corresponding program that presets the presettable ramp driver to show how to adjust the characterized presettable ramp driver to drive a plurality of ADC comparators of the ADC.

The invention provides an image sensor, an analog-to-digital conversion method thereof and electronic equipment, and belongs to the technical field of electronic circuits. The image sensor at least comprises a pixel array, wherein an effective pixel region outputs an effective pixel voltage; the dark current offset voltage acquisition module is used for acquiring simulated dark current offset voltage formed by dark current; the ramp generator is used for generating an original ramp voltage, the output end of the ramp generator is electrically connected to the output end of the dark current offset voltage acquisition module, and the analog dark current offset voltage is superposed to the original ramp voltage to form an additional ramp voltage; one end of the comparator inputs the effective pixel voltage, the other end of the comparator inputs the additional ramp voltage generated by the output end of the ramp generator, and the comparator compares the effective pixel voltage with the additional ramp voltage; and the counter is used for counting the effective pixel voltages to obtain quantized effective pixel voltages. According to the image sensor provided by the invention, the time required for pixel voltage quantification can be saved.

A system includes an inverter configured to convert DC power from a battery to AC power, wherein the inverter includes: a duty cycle adjustor including: a rising edge detector to detect a rising edge of a periodic signal; a ramp generator connected to the rising edge detector; a first comparator connected to the ramp generator; a duty cycle trimmer connected to the first comparator; and a bidirectional current trimmer connected to the duty cycle trimmer and the ramp generator.

An image sensor device may include an image pixel configured to generate a pixel signal based on a light, a ramp generator including a ramp source circuit configured to generate a raw ramp signal, a driving source circuit configured to generate a driving source signal, and a bandwidth control circuit configured to generate a driving signal by adjusting a bandwidth of the driving source signal, and a ramp buffering circuit configured to generate a ramp signal corresponding to the raw ramp signal based on the driving signal, a comparative amplifier configured to generate a comparison output signal based on the pixel signal and the ramp signal, and an analog-to-digital conversion circuit generating a digital signal corresponding to the light based on the comparison output signal.

The present application relates to the technical field of power plant production process automation, and discloses a coal mill air distribution warm grinding control method and device, electronic equipment and a storage medium. The method comprises the following steps: in the automatic mode, in response to the mill closing signal, the inlet cold air volume of the mill is increased by using a slope generator, and the outlet temperature of the mill is adjusted by a first PID regulator; when the inlet air volume is greater than or equal to a first air volume threshold, the inlet air volume and the outlet temperature are adjusted by the first PID regulator and a second PID regulator in a push-pull balance mode; when the inlet air volume is greater than or equal to a second air volume threshold and the outlet temperature is greater than or equal to a temperature threshold, the outlet temperature of the mill is adjusted by using a third PID regulator to schedule cold air, and the inlet air volume of the mill is adjusted by using a fourth PID regulator to schedule hot air. The present application realizes full-automatic control from the start to the normal operation of the coal layer burner, and eliminates the hidden danger of "misoperation" that may occur in the complex operation process by manual operation.

A circuit includes a first capacitance array formed by n nominally equal capacitive elements. A first electrode of each capacitive element is coupled, via respective switches to either a reference voltage or ground. A differential amplifier has a first input coupled to an output of a first capacitance array, a second input grounded, and an output generating a voltage ramp. A capacitive feedback circuit couples the output of the differential amplifier to the first input. A second capacitance array has an output coupled to the first input of the differential amplifier. The capacitive elements of the first capacitance array are organized in sets. The circuit operates by controllably coupling, set by set, second electrodes of the capacitive elements of the first capacitance array to the first input of the differential amplifier.

Provided are an artificial neural network apparatus and a method for operating the same. The artificial neural network apparatus may include: a synaptic device; an integrator operatively connected to the synaptic device and integrating a current generated based on that an input pulse voltage is applied to the synaptic device into a voltage, and outputting a first voltage; a ramp generator operatively connected to the integrator and generating a ramp signal based on the first voltage and a second voltage output from a digital-analog converter; and an output circuit operatively connected to the ramp generator and storing an output of the ramp generator and transmitting the output to the outside.

An image sensing device includes a pixel array including a plurality of pixels connected to a plurality of row lines and a plurality of column lines and configured to output a plurality of pixel signals through the plurality of column lines; a ramp generator configured to generate a first ramp signal and a second ramp signal; an analog-to-digital converter (ADC) configured to convert the plurality of pixel signals into digital signals in response to the first ramp signal and the second ramp signal; and a column line controller configured to selectively connect the plurality of column lines to the ADC.

A controller for controlling a power stage having one or more phases is presented. The controller includes a reference circuit that generates a reference signal; a ramp generator generating a feedback ramp signal based on a feedback signal of the power stage; and a modulator generating a control signal for controlling at least one phase of the power stage. The control signal may include a series of pulses in which each pulse is associated with a corresponding phase of the power stage.

An apparatus is disclosed that includes a PWM ramp generator coupled between a switch node of a power converter and a first input of a comparator. The PWM ramp generator includes a first resistor and a first capacitor connected in series between the switch node and the first input of the comparator, and a second resistor and a second capacitor connected in parallel between the first input of the comparator and a feedback node. A PFM control circuit includes an error amplifier and a current zero-crossing detection comparator, where the error amplifier is coupled between a second input of the comparator and a reference node. The PFM control circuit is configured to generate a gate drive signal for the power converter when the power converter is configured to operate in a PFM mode.

The invention provides an artificial cochlea telemetry data sampling and returning circuit and method, and belongs to the technical field of artificial cochlea telemetry. According to the method, a to-be-detected analog signal is amplified through a programmable gain amplifier, the signal is converted into a pulse width signal through a voltage ramp generator and a comparator, a step signal with short duration is generated on a coil through an output driver, and ringing is formed. The extracorporeal machine detects the interval time of the step signal to restore the signal size. An analog-to-digital converter is not needed, the power consumption and the chip area are remarkably reduced, the data transmission efficiency is improved, and the method is suitable for telemetering systems of various implantable medical devices such as artificial cochlea and the like. According to the invention, the power consumption and the layout area of the implanted chip are obviously reduced, the single data transmission time is shortened to 48 microseconds, the efficiency is improved by about 10 times, and the method is suitable for low-power-consumption implanted equipment such as artificial cochlea and the like.

A switching converter circuit for converting an input voltage to an output voltage includes: a feedback compensation circuit for producing a feedback compensation signal according to a difference between a feedback signal related to the output voltage and a reference signal; a modulation circuit for generating a modulation signal in accordance with the feedback compensation signal and a ramp signal; a power stage circuit for switching an inductor according to the modulation signal; and a ramp generator circuit for producing the ramp signal according to the input voltage, the output voltage and the modulation signal. The ramp signal includes: an anterior ramp signal and a posterior ramp signal. An absolute value of a slope of the posterior ramp signal gradually decreases as time increases. A starting time point of the modulation signal is decided by an intersection time point between the posterior ramp signal and the feedback compensation signal.

The invention relates to a sampling gear soft switching circuit, and the circuit comprises a sampling resistor array which comprises a plurality of sampling resistors with different resistance values; the soft switching devices and the sampling resistors are connected in series one by one to form sampling branches which are connected in parallel; the soft switching device includes a transistor component as a switch; the output end of the slope generator is electrically connected with the control end of the transistor assembly, and the slope generator is used for outputting a driving signal with voltage changing in a slope mode; the control unit communicates with the ramp generator and is configured to control the ramp generator to output a driving signal to the soft switching device corresponding to the target sampling branch according to the gear switching instruction; when the transistor assembly receives the driving signal, the voltage at the control end of the transistor assembly changes according to the slope of the driving signal, so that the transistor assembly works in a linear region. The method has the advantages that continuous and smooth transition of impedance in the sampling gear switching process is achieved, and therefore generation of voltage burrs is restrained from the source.

The invention relates to a distributed ramp linearity compensation circuit. An imaging system includes a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column of unit cells includes at least one of a plurality of comparators, wherein each comparator is coupled to receive a ramp signal from a ramp generator through a ramp signal line. Each column of unit cells further comprises a compensation current unit coupled to the ramp signal line, and each compensation current unit comprises a compensation current source and a compensation current switch coupled to the compensation current source. Wherein the compensation current source and the compensation current switch are coupled between a first node and a second node on the ramp signal line.

The present disclosure relates to an arrangement of comparators (120). The comparators (120) of the arrangement are configured to operate in parallel, with one input terminal of each of the comparators (120) connected to a common ramp generator (110). The arrangement further comprises a kickback compensation circuit (105) for subtracting a kickback compensation value from a digital value output by each of the comparators (120).

Disclosed is an analog-to-digital converter (ADC) circuit for digitizing a pixel signal into a digital signal of positive integer (N) bits. The ADC includes a ramp generator, a clock, a comparator, and a counter. A system clock signal allows the ramp generator to generate a ramp signal and the clock generator to generate first to N-th clock signals. The comparator generates a comparison signal based on a comparison of the pixel signal, received from a pixel array, and the ramp signal. The counter includes an additional latch circuit and first to N-th latch circuits. The additional latch circuit generates an additional binary signal based on the system clock signal and the comparison signal, and the first to N-th latch circuits generate first to N-th latch signals based on the comparison signal and corresponding clock signal.

This disclosure relates to the field of image sensor technology, specifically to a high-linearity, low-power CMOS image sensor readout circuit. The readout circuit includes a ramp generator, a comparator, and a counter. The counter includes a first D flip-flop, a signal separation circuit, a high-order counter (MSB), and a low-order counter (LSB). The signal separation circuit separates the output signal of the first D flip-flop into a low-order high-frequency signal and a high-order low-frequency signal. The low-order counter (LSB) receives the low-order high-frequency signal, and the high-order counter (MSB) receives the high-order low-frequency signal. The high-order counter (MSB) and the low-order counter (LSB) each include several cascaded LS-type sampling counters. The LS-type sampling counter includes a first D flip-flop and a CDS circuit, wherein the CDS circuit is an OR gate circuit.

Image sensors and methods for reading out image sensors. The image sensor includes a pixel array, a ramp generator, a gain circuit, a comparator, a digital counter, and a controller. The ramp generator is configured to generate a ramp signal. The gain circuit is configured to apply a first gain to the ramp signal when a pixel is reset and a selected gain to the ramp signal when the pixel is read out. The comparator is configured to compare a pixel output when the pixel is reset to the ramp signal. The comparator is also configured to compare the pixel output when the pixel is read out to the ramp signal. The digital counter is also configured to determine a digital signal value based on the outputs of the comparator. The controller is configured to determine a pixel value for the pixel based on the digital signal value.

According to one aspect, system for generating bias pulsed waveforms includes: an inverter stage configured to generate a signal having bias pulses from a direct current (DC) supply voltage; a ramp generator configured to introduce, into the signal, a negative voltage ramp after each bias pulse; and at least one inductive element configured to allow soft switching of the inverter stage. According to another aspect, a system for generating bias pulsed waveforms includes: a multi-level inverter stage configured to produce, from one or more direct current (DC) voltages, three or more different voltage levels used for generating bias pulses, the bias pulses having a maximum voltage level and a minimum voltage level from the three or more voltage levels produced; and a transformer configured to step up the bias pulses to provide high-voltage output pulses.

This invention provides a pixel column readout circuit and an image sensor. The pixel column readout circuit includes: a subtraction circuit, comprising a reset voltage sampling capacitor and a signal voltage sampling capacitor, one end of which is electrically connected to the output of a pixel signal generation circuit via two switches, and one end of which is connected via a third switch, and the other end via a fourth switch; a ramp generator, the output of which is connected to the subtraction circuit; a comparator circuit, including a first comparator, the negative input of which is electrically connected to the connection point of the reset voltage sampling capacitor and the fourth switch, and the positive input of which receives a fixed voltage; and a counter, electrically connected to the output of the comparator circuit. The ramp generator provided by this invention ensures linear output of the analog-to-digital conversion.

An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.