216 results about "Ramp generator" patented technology

An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.

The invention discloses a parallel-serial conversion circuit based on a composite dielectric gate photosensitive detector, and belongs to the field of integrated circuits. The parallel-serial conversion circuit comprises a composite dielectric gate photosensitive detector pixel, a ramp generator, a clamping circuit, a switch S1, a pre-charging circuit, a comparator, a counter, 8-256 decoders, a first AND gate, 256 second AND gates and a 256 input OR gate. According to the parallel-serial conversion circuit, all digital circuit parts are converted into analog circuits, so that the circuit design complexity is reduced, the circuit simulation and layout design iteration period is shortened, the power consumption and the area of a chip are effectively reduced, and the design of a subsequent miniaturized system is facilitated.

An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.

A local ramp buffer includes a deep N− well layer disposed in a P− substrate beneath a surface of the P− substrate, a P− well disposed between the surface of the P− substrate and the deep N− well layer, and an N− well structure disposed in the P− substrate and coupled to the deep N− well layer. The N− well structure is disposed between the surface of the P− substrate and the deep N− well layer. The P− well is disposed inside an opening in the N− well structure. The N− well structure and the deep N− well layer are configured to isolate the P− well within the opening. A source follower transistor is disposed in the P− well. The source follower transistor includes a gate terminal coupled to the N− well structure and a ramp generator.

Disclosed is an analog-to-digital converter (ADC) circuit for digitizing a pixel signal into a digital signal of positive integer (N) bits. The ADC includes a ramp generator, a clock, a comparator, and a counter. A system clock signal allows the ramp generator to generate a ramp signal and the clock generator to generate first to N-th clock signals. The comparator generates a comparison signal based on a comparison of the pixel signal, received from a pixel array, and the ramp signal. The counter includes an additional latch circuit and first to N-th latch circuits. The additional latch circuit generates an additional binary signal based on the system clock signal and the comparison signal, and the first to N-th latch circuits generate first to N-th latch signals based on the comparison signal and corresponding clock signal.

A ramp driver includes a ramp generator for generating a reference ramp signal, and a ramp delayer for sequentially outputting ramp signals based on the reference ramp signal, and including delay blocks including k output terminals, k being an integer greater than or equal to 2, wherein the delay blocks include k delay circuits sequentially connected to each other, respectively connected to the output terminals, and configured to receive an input ramp signal from a previous one of the delay circuits, receive an input gate clock signal from a previous delay circuit, output an output ramp signal by delaying the input ramp signal, and output an output gate clock signal by inverting the input gate clock signal.

The utility model discloses a frequency offset error control device for the distance measurement of a responder, and mainly solves the problem that the modulation frequency offset error is increased in the prior art. The system comprises a transmitting channel, a receiving channel, a frequency synthesizer source module, a ramp generator loop module and a high frequency mixing module. The frequency synthesizer source module outputs in two paths, one path is connected with the ramp generator loop module through a first power divider, a frequency divider and a second power divider, and the other path is connected with the high frequency mixing module through the first power divider, a first filter and a frequency multiplier; the slope generator loop module is connected with the high frequency mixing module through the low frequency mixer and the third filter; the high frequency mixing module mixes the signal output by the frequency multiplier and the signal output by the third filter and then inputs the mixed signal to a transmitting channel for transmission; and the receiving channel receives a transmitted signal and outputs a constant difference frequency signal for distance measurement. According to the utility model, the modulation frequency offset error of the linear frequency modulation signal can be reduced, the frequency stability of the transmitted signal can be improved, and the device can be used for distance measurement based on the linear frequency modulation continuous wave signal responder.

A controller includes a current-mode control device configured to determine a turn-on edge of a first gate-drive signal, an on-time timer that includes a first ramp generator having a first current source, a first capacitor, and a first ramp-generation switch, the first ramp generator configured to generate a first ramp signal, and a first logic circuit having an output coupled to a control terminal of the first ramp-generation switch, the first logic circuit configured to control the first ramp-generation switch based at least in part on the first gate-drive signal and on a feedback signal received from the current-mode control device, thereby resetting the first ramp signal, wherein the on-time timer is further configured to determine a turn-off edge of the first gate-drive signal by comparing the first ramp signal with a first threshold voltage that is proportional to an output voltage of the power converter.

A voltage ramp generator includes a resistor network, electronic switches and at least one reference voltage circuit. The resistor network includes resistor elements electrically connected in series between a first supply node (VDD) and a second supply node (VSS), wherein circuit nodes are formed between neighboring resistor elements. Each electronic switch is operable to connect one of the circuit nodes with a switch arrangement output. The at least one reference voltage circuit supplies a reference voltage to one of the circuit nodes.

The invention belongs to the field of CMOS (Complementary Metal Oxide Semiconductor) devices, and particularly relates to a monoclinic ADC (Analog to Digital Converter) and CIS (Contact Image Sensor) chip based on a look-ahead adaptive CMS ( The CMS quantization module comprises each CMS quantization module connected to each column in a pixel array and a dynamic slope generation module; the CMS quantization module comprises a comparator, a counter, a column level judgment module and an adder-subtractor. The dynamic slope generation module comprises a slope generator, a slope modulation module and a global judgment module. The ramp generator is used for generating a ramp signal corresponding to a standard ramp, a full-scale ramp or a self-adaptive ramp according to the received modulation signal, and sending the ramp signal to the comparator in the corresponding row. And the global judgment module is used for identifying the maximum value and the minimum value of the primary quantization results of the pixel units in the same row, and further determining the swing interval of the adaptive slope in the secondary quantization. The slope modulation module is used for outputting modulation signals capable of generating three types of slopes. According to the invention, the problem that an existing monoclinic ADC is difficult to give consideration to quantization precision and quantization time at the same time is solved.

The invention provides a current source circuit, a ramp generator, an analog-to-digital converter and a chip, the current source circuit is provided with a reference current generating circuit, a current mirror circuit and a clamping circuit, the current of a reference current source is mirrored through n mirror image branches, and the current generated by a current mirror is further clamped and shunted through the clamping circuit; the mirror image branch connected with the first input end or the second input end of the clamping circuit determines the magnitude of the output current of the current source circuit, the circuit is simple and easy to implement, the precision of the output current can be accurately controlled through gating of the mirror image branch, and the reliability of the current source circuit is improved. Meanwhile, the problem that in an existing scheme, when the adjustment digit of the needed output current is high, the number of transistors needing to be stacked is increased in an exponential mode can be solved, the balance between the current adjustment precision and the chip layout area can be achieved, and therefore the performance of the slope generator, the analog-digital converter and the chip designed based on the current source circuit is improved.

The invention relates to a column ramp buffer design to improve ADC range in a CIS. An imaging system includes an array of pixels and readout circuitry coupled to the array of pixels. The readout circuitry includes a ramp generator and a plurality of column unit cells, each column unit cell including a column ramp buffer and a column comparator, and each column of ramp buffers includes an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator; and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit includes a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.

Circuits are disclosed for controlling voltage regulators. In general, one aspect disclosed features an electric circuit comprising: a digital ramp generator configured to generate a digital voltage ramp; a digital low-pass filter having an input electrically coupled to an output of the digital ramp generator and configured to low-pass filter the digital voltage ramp; a digital-to-analog converter having an input electrically coupled to an output of the digital low-pass filter and configured to generate an analog control signal based on the filtered digital voltage ramp; and a voltage regulator having an input electrically coupled to an output of the digital-to-analog converter and configured to regulate an output voltage based on the analog control signal and an input voltage of the voltage regulator.

The invention discloses a low-power-consumption column parallel monoclinic ADC (Analog to Digital Converter) circuit adopting a floating comparator circuit, a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor reading circuit and a CMOS image sensor. The low-power-consumption column parallel monoclinic ADC circuit adopting the floating comparator circuit comprises a floating comparator, an M-bit calculator, an M-bit latch and a parallel-serial conversion circuit which are connected in sequence, and the floating comparator is provided with a pixel signal input end and a ramp signal input end and is connected with a ramp generator through the ramp signal input end. According to the low-power-consumption column parallel monoclinic ADC circuit of the floating comparator circuit, the topological structure of a traditional floating comparator is improved, and an input overturning point of the comparator is kept on a set level; in the comparison stage of the monoclinic ADC, the voltage reduction amplitude of the floating capacitor is reduced, and it is ensured that the comparator is in a normal working state in the whole comparison stage.

An electronic device includes a ramp generator configured to generate a ramp signal used to detect data, the ramp signal increasing or decreasing with a certain slope; a main circuit configured to perform at least one predefined function by detecting the data based on the ramp signal; a monitoring circuit configured to output a verify signal indicating whether the ramp signal is faulty; and a controller configured to control execution of the at least one predefined function based on the verify signal.

An oscillator circuit (200) includes a ring oscillator (202) and a ramp generator (204). The ring oscillator (202) includes a first inverter (214) and a second inverter (218). The first inverter (214) has a first inverter input, a first inverter output, and a first power terminal. The second inverter (218) has a second inverter input, a second inverter output, and a second power terminal. The second inverter input is coupled to the first inverter output, and the second inverter output is coupled to the first inverter input. The ramp generator circuit (204) has a ramp output coupled to the first power terminal and the second power terminal.

Voltage Ramp Generator This description relates to a circuit, or a process in a circuit, comprising: a first network of capacitors (3) comprising n nominally equal capacitive elements (Ci) each having a first electrode connected, via respective switches (Ki), either to a reference voltage (VREF) or to ground; a differential amplifier having a first input (-) connected to an output (21) of said first converter, a second input (+) connected to ground, and an output (28) providing a voltage ramp (VRAMP); a capacitive feedback circuit connecting the output of said differential amplifier to said first input;and a second network of capacitors (4) one output of which is connected to the first input (-) of the differential amplifier (25), the capacitive elements being arranged in sets and the method further comprising the controlled coupling, set by set, of second electrodes of the capacitive elements to said first input of the amplifier. Abstract figure: Fig. 3;

This invention discloses a high-precision ramp generator and a two-step single-slope analog-to-digital converter. The ramp generator includes a bandgap reference source circuit, a voltage-to-current conversion circuit, a weighted current DAC current source array, a charge / discharge current regulation circuit, a mode switching circuit, and a bias circuit. In this invention, the quantization process of the ramp generator is decomposed into two stages: coarse quantization and fine quantization, significantly reducing quantization time. Furthermore, a single output stage can combine a DAC-type ramp generator and a capacitor-integrating ramp generator, saving area and power consumption in chip design, improving the compatibility of the ramp generator, solving the linearity and stability problems introduced by stepped ramps in high-speed, high-precision applications, and reducing design complexity.

The invention discloses a modulation pulse width generation circuit for an electromagnetic resonance high-frequency fatigue testing machine, and relates to the field of material fatigue tests. The circuit comprises a load sensor, a signal conditioning unit, a summing amplifier, a polarity detection circuit, a peak detection circuit, a sampling level unit, a ramp generator, a modulation square wave circuit, a delay synchronization unit and a modulation pulse width output unit. The method comprises the following steps: acquiring a force value borne by a metal material in an electromagnetic resonance high-frequency fatigue testing machine through a load sensor; through amplification and filtering of the signal conditioning unit, comparison of the summing amplifier, polarity judgment of the polarity detection circuit, peak detection of the peak detection circuit, sampling of the sampling level unit, oblique wave processing of the oblique wave generator, modulation of the modulation square wave circuit, and filtering and shaping of the delay synchronization unit, the delay synchronization unit can be used to carry out synchronization. Finally, modulation pulse width is generated through the modulation pulse width output unit. The real-time performance, the stability and the response speed of excitation of the electromagnetic resonance high-frequency fatigue testing machine can be improved.

A ramp generator for generating a ramp signal from an image sensor is disclosed. The ramp generator includes a bias voltage generator configured to generate a bias voltage, and a plurality of ramp cells configured to generate a ramp signal based on the bias voltage. Each of the plurality of ramp cells includes a local sampling circuit configured to adjust a sampling timing point of the bias voltage.

A ramp generator includes an operational amplifier having an output to generate a ramp signal. An integration current source is coupled to a first input and a reference voltage is coupled to a second input of the operational amplifier. A feedback capacitor and a reset switch are coupled between the first input and the output of the operational amplifier. The reset switch is turned on to reset the ramp generator. A ramp event is configured to be generated in the ramp signal at the output of the operational amplifier in response to the reset switch being turned off. An assist current source is coupled between the output of the operational amplifier and ground. The assist current source is configured to conduct an assist current from the output of the operational amplifier to ground in response to the reset switch being turned off.

A circuit includes a first capacitance array formed by n nominally equal capacitive elements. A first electrode of each capacitive element is coupled, via respective switches to either a reference voltage or ground. A differential amplifier has a first input coupled to an output of a first capacitance array, a second input grounded, and an output generating a voltage ramp. A capacitive feedback circuit couples the output of the differential amplifier to the first input. A second capacitance array has an output coupled to the first input of the differential amplifier. The capacitive elements of the first capacitance array are organized in sets. The circuit operates by controllably coupling, set by set, second electrodes of the capacitive elements of the first capacitance array to the first input of the differential amplifier.

This invention provides a circuit and method for sampling and transmitting telemetry data from a cochlear implant, belonging to the field of telemetry technology for cochlear implants. The method amplifies the analog signal under test using a programmable gain amplifier, converts the signal into a pulse width signal using a voltage ramp generator and comparator, and then generates a short-duration step signal on the coil via an output driver to form a ringing pattern. An external device detects the interval between the step signals to reconstruct the signal magnitude. This invention eliminates the need for an analog-to-digital converter, significantly reducing power consumption and chip area, and improving data transmission efficiency. It is suitable for telemetry systems in various implantable medical devices such as cochlear implants. This invention significantly reduces the power consumption and layout area of ​​the implanted chip and shortens the single data transmission time to 48μs, improving efficiency by approximately 10 times, making it suitable for low-power implantable devices such as cochlear implants.

An image sensing device capable of operating in various modes is disclosed. The image sensing device includes a pixel array configured to generate a pixel signal; a first ramp generator configured to generate a first ramp signal; a second ramp generator configured to generate a second ramp signal; an analog-to-digital converter (ADC) circuit including a comparator configured to compare the pixel signal with one of the first ramp signal and the second ramp signal, and to generate image data based on a result of the comparison; and a processor configured to control the ADC circuit to input the first ramp signal to the comparator in a first mode and to input the second ramp signal to the comparator in a second mode.

An image sensor including: a pixel array including first to N-th pixel circuits to generate first to N-th pixel signals; an ADC connected to the pixel circuits; a system clock generator to generate a system clock signal; an internal clock generator to generate first to N-th clock signals and (N+1)-th to 2N-th clock signals based on the system clock signal; a ramp generator to generate first to N-th ramp signals based on the first to N-th clock signals; and a counter clock generator to generate first to N-th counter clock signals based on the (N+1)-th to 2N-th clock signals, the ADC includes: a comparator to generate first to N-th comparison signals based on comparison operations of the first to N-th pixel signals and the first to N-th ramp signals; and a counter to generate first to N-th digital signals based on the comparison signals and the counter clock signals.

A method to operate an analog to digital converter. The method may storing a sampled signal of an input voltage on capacitors, of an up ramp generator and of a down ramp generator to obtain a sampled signal, enabling one of the up ramp generator and the down ramp generator based on a sign of the sampled signal, detecting, on the capacitors, a zero crossing of a stepped ramp that is generated in the one of the up ramp generator and the down ramp generator, and generating a digital representation of the sampled signal based on a number of steps in the stepped ramp.

A voltage converter (100) includes a power stage circuit (110), a compensator circuit (130), and a modulator circuit (120). The power stage circuit (110) has an input voltage terminal, an output voltage terminal, and a pulse width modulation (PWM) control input. The compensator circuit (130) has a voltage input coupled to the output voltage terminal, and has a compensation output. The modulator circuit (120) has a compensation voltage input and a PWM control output. The compensation voltage input is coupled to the compensation output, and the PWM control output is coupled to the PWM control input. The modulator circuit (120) includes a slope compensation ramp generator circuit (122) configured to generate a slope compensation voltage ramp having a slope that decreases during at least a portion of a switching period.

A DC-DC converter includes a ramp generator, a threshold voltage circuit, and a control circuit. The ramp generator is configured to generate a voltage ramp. The threshold voltage circuit is configured to generate a threshold voltage. The control circuit is coupled to the ramp generator and the threshold voltage circuit. The control circuit includes a digital pulse width modulator (DPWM) circuit and a loop compensation circuit coupled to the DPWM circuit. The DPWM circuit is configured to generate a power stage switch control signal responsive to a loop compensation value. The loop compensation circuit is coupled to the DPWM circuit. The loop compensation circuit is configured to calculate the loop compensation value responsive to the voltage ramp exceeding the threshold voltage.

An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.

The invention discloses an asynchronous counter, a ramp generator, an analog-to-digital converter and an image sensor, and relates to the field of integrated circuits. The asynchronous counter comprises a plurality of cascaded D triggers; the clock input end and the inverted output end of each odd-level trigger are respectively connected to the first input end and the second input end of the OR logic gate, and the output end of the OR logic gate is connected to the clock input end of the next even-level trigger; the forward output end of each even-level trigger and the forward output end of the last odd-level trigger are connected to the first input end and the second input end of the NAND logic gate respectively, and the clock input end of the last odd-level trigger is connected to the third input end of the NAND logic gate through the phase inverter. And the output end of the NAND logic gate is connected to the clock input end of the next odd-level trigger. Therefore, by optimizing the generation logic of the clock input signal in the odd-level trigger, the delay time of the output signal under different bits is reduced.