154 results about "Ramp generator" patented technology

A local ramp buffer includes a deep N− well layer disposed in a P− substrate beneath a surface of the P− substrate, a P− well disposed between the surface of the P− substrate and the deep N− well layer, and an N− well structure disposed in the P− substrate and coupled to the deep N− well layer. The N− well structure is disposed between the surface of the P− substrate and the deep N− well layer. The P− well is disposed inside an opening in the N− well structure. The N− well structure and the deep N− well layer are configured to isolate the P− well within the opening. A source follower transistor is disposed in the P− well. The source follower transistor includes a gate terminal coupled to the N− well structure and a ramp generator.

A ramp driver includes a ramp generator for generating a reference ramp signal, and a ramp delayer for sequentially outputting ramp signals based on the reference ramp signal, and including delay blocks including k output terminals, k being an integer greater than or equal to 2, wherein the delay blocks include k delay circuits sequentially connected to each other, respectively connected to the output terminals, and configured to receive an input ramp signal from a previous one of the delay circuits, receive an input gate clock signal from a previous delay circuit, output an output ramp signal by delaying the input ramp signal, and output an output gate clock signal by inverting the input gate clock signal.

A controller includes a current-mode control device configured to determine a turn-on edge of a first gate-drive signal, an on-time timer that includes a first ramp generator having a first current source, a first capacitor, and a first ramp-generation switch, the first ramp generator configured to generate a first ramp signal, and a first logic circuit having an output coupled to a control terminal of the first ramp-generation switch, the first logic circuit configured to control the first ramp-generation switch based at least in part on the first gate-drive signal and on a feedback signal received from the current-mode control device, thereby resetting the first ramp signal, wherein the on-time timer is further configured to determine a turn-off edge of the first gate-drive signal by comparing the first ramp signal with a first threshold voltage that is proportional to an output voltage of the power converter.

Circuits are disclosed for controlling voltage regulators. In general, one aspect disclosed features an electric circuit comprising: a digital ramp generator configured to generate a digital voltage ramp; a digital low-pass filter having an input electrically coupled to an output of the digital ramp generator and configured to low-pass filter the digital voltage ramp; a digital-to-analog converter having an input electrically coupled to an output of the digital low-pass filter and configured to generate an analog control signal based on the filtered digital voltage ramp; and a voltage regulator having an input electrically coupled to an output of the digital-to-analog converter and configured to regulate an output voltage based on the analog control signal and an input voltage of the voltage regulator.

The invention discloses a low-power-consumption column parallel monoclinic ADC (Analog to Digital Converter) circuit adopting a floating comparator circuit, a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor reading circuit and a CMOS image sensor. The low-power-consumption column parallel monoclinic ADC circuit adopting the floating comparator circuit comprises a floating comparator, an M-bit calculator, an M-bit latch and a parallel-serial conversion circuit which are connected in sequence, and the floating comparator is provided with a pixel signal input end and a ramp signal input end and is connected with a ramp generator through the ramp signal input end. According to the low-power-consumption column parallel monoclinic ADC circuit of the floating comparator circuit, the topological structure of a traditional floating comparator is improved, and an input overturning point of the comparator is kept on a set level; in the comparison stage of the monoclinic ADC, the voltage reduction amplitude of the floating capacitor is reduced, and it is ensured that the comparator is in a normal working state in the whole comparison stage.

An electronic device includes a ramp generator configured to generate a ramp signal used to detect data, the ramp signal increasing or decreasing with a certain slope; a main circuit configured to perform at least one predefined function by detecting the data based on the ramp signal; a monitoring circuit configured to output a verify signal indicating whether the ramp signal is faulty; and a controller configured to control execution of the at least one predefined function based on the verify signal.

An oscillator circuit (200) includes a ring oscillator (202) and a ramp generator (204). The ring oscillator (202) includes a first inverter (214) and a second inverter (218). The first inverter (214) has a first inverter input, a first inverter output, and a first power terminal. The second inverter (218) has a second inverter input, a second inverter output, and a second power terminal. The second inverter input is coupled to the first inverter output, and the second inverter output is coupled to the first inverter input. The ramp generator circuit (204) has a ramp output coupled to the first power terminal and the second power terminal.

This invention discloses a high-precision ramp generator and a two-step single-slope analog-to-digital converter. The ramp generator includes a bandgap reference source circuit, a voltage-to-current conversion circuit, a weighted current DAC current source array, a charge / discharge current regulation circuit, a mode switching circuit, and a bias circuit. In this invention, the quantization process of the ramp generator is decomposed into two stages: coarse quantization and fine quantization, significantly reducing quantization time. Furthermore, a single output stage can combine a DAC-type ramp generator and a capacitor-integrating ramp generator, saving area and power consumption in chip design, improving the compatibility of the ramp generator, solving the linearity and stability problems introduced by stepped ramps in high-speed, high-precision applications, and reducing design complexity.

The invention discloses a modulation pulse width generation circuit for an electromagnetic resonance high-frequency fatigue testing machine, and relates to the field of material fatigue tests. The circuit comprises a load sensor, a signal conditioning unit, a summing amplifier, a polarity detection circuit, a peak detection circuit, a sampling level unit, a ramp generator, a modulation square wave circuit, a delay synchronization unit and a modulation pulse width output unit. The method comprises the following steps: acquiring a force value borne by a metal material in an electromagnetic resonance high-frequency fatigue testing machine through a load sensor; through amplification and filtering of the signal conditioning unit, comparison of the summing amplifier, polarity judgment of the polarity detection circuit, peak detection of the peak detection circuit, sampling of the sampling level unit, oblique wave processing of the oblique wave generator, modulation of the modulation square wave circuit, and filtering and shaping of the delay synchronization unit, the delay synchronization unit can be used to carry out synchronization. Finally, modulation pulse width is generated through the modulation pulse width output unit. The real-time performance, the stability and the response speed of excitation of the electromagnetic resonance high-frequency fatigue testing machine can be improved.

A ramp generator for generating a ramp signal from an image sensor is disclosed. The ramp generator includes a bias voltage generator configured to generate a bias voltage, and a plurality of ramp cells configured to generate a ramp signal based on the bias voltage. Each of the plurality of ramp cells includes a local sampling circuit configured to adjust a sampling timing point of the bias voltage.

A ramp generator includes an operational amplifier having an output to generate a ramp signal. An integration current source is coupled to a first input and a reference voltage is coupled to a second input of the operational amplifier. A feedback capacitor and a reset switch are coupled between the first input and the output of the operational amplifier. The reset switch is turned on to reset the ramp generator. A ramp event is configured to be generated in the ramp signal at the output of the operational amplifier in response to the reset switch being turned off. An assist current source is coupled between the output of the operational amplifier and ground. The assist current source is configured to conduct an assist current from the output of the operational amplifier to ground in response to the reset switch being turned off.

This invention provides a circuit and method for sampling and transmitting telemetry data from a cochlear implant, belonging to the field of telemetry technology for cochlear implants. The method amplifies the analog signal under test using a programmable gain amplifier, converts the signal into a pulse width signal using a voltage ramp generator and comparator, and then generates a short-duration step signal on the coil via an output driver to form a ringing pattern. An external device detects the interval between the step signals to reconstruct the signal magnitude. This invention eliminates the need for an analog-to-digital converter, significantly reducing power consumption and chip area, and improving data transmission efficiency. It is suitable for telemetry systems in various implantable medical devices such as cochlear implants. This invention significantly reduces the power consumption and layout area of ​​the implanted chip and shortens the single data transmission time to 48μs, improving efficiency by approximately 10 times, making it suitable for low-power implantable devices such as cochlear implants.

An image sensing device capable of operating in various modes is disclosed. The image sensing device includes a pixel array configured to generate a pixel signal; a first ramp generator configured to generate a first ramp signal; a second ramp generator configured to generate a second ramp signal; an analog-to-digital converter (ADC) circuit including a comparator configured to compare the pixel signal with one of the first ramp signal and the second ramp signal, and to generate image data based on a result of the comparison; and a processor configured to control the ADC circuit to input the first ramp signal to the comparator in a first mode and to input the second ramp signal to the comparator in a second mode.

An image sensor including: a pixel array including first to N-th pixel circuits to generate first to N-th pixel signals; an ADC connected to the pixel circuits; a system clock generator to generate a system clock signal; an internal clock generator to generate first to N-th clock signals and (N+1)-th to 2N-th clock signals based on the system clock signal; a ramp generator to generate first to N-th ramp signals based on the first to N-th clock signals; and a counter clock generator to generate first to N-th counter clock signals based on the (N+1)-th to 2N-th clock signals, the ADC includes: a comparator to generate first to N-th comparison signals based on comparison operations of the first to N-th pixel signals and the first to N-th ramp signals; and a counter to generate first to N-th digital signals based on the comparison signals and the counter clock signals.

A method to operate an analog to digital converter. The method may storing a sampled signal of an input voltage on capacitors, of an up ramp generator and of a down ramp generator to obtain a sampled signal, enabling one of the up ramp generator and the down ramp generator based on a sign of the sampled signal, detecting, on the capacitors, a zero crossing of a stepped ramp that is generated in the one of the up ramp generator and the down ramp generator, and generating a digital representation of the sampled signal based on a number of steps in the stepped ramp.

A voltage converter (100) includes a power stage circuit (110), a compensator circuit (130), and a modulator circuit (120). The power stage circuit (110) has an input voltage terminal, an output voltage terminal, and a pulse width modulation (PWM) control input. The compensator circuit (130) has a voltage input coupled to the output voltage terminal, and has a compensation output. The modulator circuit (120) has a compensation voltage input and a PWM control output. The compensation voltage input is coupled to the compensation output, and the PWM control output is coupled to the PWM control input. The modulator circuit (120) includes a slope compensation ramp generator circuit (122) configured to generate a slope compensation voltage ramp having a slope that decreases during at least a portion of a switching period.

An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.

The invention discloses an asynchronous counter, a ramp generator, an analog-to-digital converter and an image sensor, and relates to the field of integrated circuits. The asynchronous counter comprises a plurality of cascaded D triggers; the clock input end and the inverted output end of each odd-level trigger are respectively connected to the first input end and the second input end of the OR logic gate, and the output end of the OR logic gate is connected to the clock input end of the next even-level trigger; the forward output end of each even-level trigger and the forward output end of the last odd-level trigger are connected to the first input end and the second input end of the NAND logic gate respectively, and the clock input end of the last odd-level trigger is connected to the third input end of the NAND logic gate through the phase inverter. And the output end of the NAND logic gate is connected to the clock input end of the next odd-level trigger. Therefore, by optimizing the generation logic of the clock input signal in the odd-level trigger, the delay time of the output signal under different bits is reduced.

The invention relates to reduction of click and flip-flop noise in amplifiers. In an example, a system (100) includes a loop filter (104) that includes one or more integrators (106). The system (100) includes a ramp generator (108). The system (100) includes a comparator (110) having a first input coupled to an output of the loop filter (104), a second input coupled to an output of the ramp generator (108), and having an output. The system (100) includes a muting loop (128) coupled to an input of the loop filter (104) and the output of the comparator (110). The system (100) includes a power stage (116) having an input coupled to the output of the comparator (110) and having an output. The system (100) includes a major loop (132) coupled to the output of the power stage (116) and the input of the loop filter (104). The system (100) includes an integral error detector having an input coupled to the loop filter (104) and having an output. The system (100) includes a dual comparator having an input coupled to the output of the integral error detector.

In an example, a system includes a loop filter including one or more integrators. The system includes a ramp generator. The system includes a comparator having a first input coupled to an output of the loop filter, a second input coupled to an output of the ramp generator, and having an output. The system includes a mute loop coupled to an input of the loop filter and the output of the comparator. The system includes a power stage having an input coupled to the output of the comparator, and having an output. The system includes a main loop coupled to the output of the power stage and the input of the loop filter. The system includes an integrated error detector having an input coupled to the loop filter, and having an output. The system includes a dual comparator having an input coupled to the output of the integrated error detector.

An image sensing apparatus includes: a pixel array including a plurality of pixels connected to a plurality of row lines and a plurality of column lines, and configured to output a plurality of pixel signals through the plurality of column lines; a ramp generator configured to generate a first ramp signal and a second ramp signal; an analog-to-digital converter (ADC) configured to convert the plurality of pixel signals into digital signals in response to the first ramp signal and the second ramp signal; and a column line controller configured to selectively connect the plurality of column lines to the ADC.

The invention discloses a ramp generator, an analog-to-digital converter and an image sensor, the ramp generator comprises a ramp generation circuit and a correction circuit, and the ramp generation circuit is used for generating a ramp signal; the input end of the correction circuit is connected with the output end of the slope generation circuit, the output end of the correction circuit is connected with the slope signal slope adjusting end of the slope generation circuit, and the correction circuit is used for generating a slope adjusting signal so as to adjust the slope of the slope signal of each slope generation period of the slope generation circuit to be a set value. According to the slope generator, the slope of the slope signal can be dynamically adjusted, the deviation of the slope signal caused by process or environmental factors is reduced, and the precision of the slope signal is improved.

An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.

To provide an image sensing device which operates in a plurality of modes.SOLUTION: The image sensing device includes a pixel array configured to generate a pixel signal, a first rampgenerator configured to generate a first ramp signal, a second rampgenerator configured to generate a second ramp signal, and an analog-to-digital converter (ADC) circuit including a comparator configured to compare the pixel signal with one of the first ramp signal and the second ramp signal and configured to generate image data based on a result of the comparison. And a processor configured to control the ADC circuit.SELECTED DRAWING: Figure 1

An arrangement of a pulse-width controlled vector-matrix multiplication unit and a method for its operation are disclosed. The system includes an input block connected to word lines of a matrix formed from non-volatile adjustable capacitors, and output blocks including amplifiers with inverting inputs and feedback capacitors with parallel switches. A voltage ramp generator is coupled to the word lines via switches that are controlled by the input pulse width. The amplifier in the output block operates as a non-inverting amplifier in conjunction with the matrix capacitors. A second phase of operation involves a reference capacitor and a reverse voltage ramp generator connected to the inverting input of the amplifier. The arrangement can improve energy efficiency and analog computation accuracy by implementing a comparator design within a dual-ramp timing architecture.

A voltage ramp generator includes unit cells (331) electrically connected in parallel. Each unit cell switches between an on-state and an off-state in response to a cell-specific select signal (S1-Sn). A current mirror circuit (350) copies a reference current controlled by the unit cells at a predefined current ratio into a first detector current flowing in a first detection branch. An error detection circuit (390) generates an active first error signal (ERR) if the first detector current falls below a lower threshold current or exceeds an upper threshold current.

A multi-channel Class D audio amplifier is provided to substantially reduce channel-to-channel crosstalk by employing in each channel a local triangle ramp generator controlled by a single global digital timing signal. The noise critical timing / integrating capacitor for the triangle ramp generator resides locally in each channel and adjacent to the PWM comparator of that channel and referenced to the local ground of that channel. The amplifier can also include a duty cycle limitation circuit to limit output power availability depending on the impedance of any attached loads (speakers).

An electric machine controller arranged to direct a power converter to cause a pulsed operation of an electric machine in selected operational ranges to deliver a desired output and to cause a continuous operation of the electric machine in selected operational ranges is provided. A ramp generator is adapted to provide a ramping between the pulsed operation and the continuous operation. In some embodiments, the ramp generator utilizes a quadratic, cubic or higher order ramping function. In some embodiments, during a first portion of the transitional period, the ramp generator causes pulsing between a first ramped transitional torque level and a second ramped transitional torque level that is lower than the first transitional torque level, and during a second portion of the transitional period, the ramp generator causes the electric machine to generate substantially zero torque in intervals between transitional pulses while ramping the first ramped transitional torque level.

An image sensor includes a pixel array including pixels arranged in first and directions, samplers connected to the pixels through column lines extending in the first direction, and a ramp generator including first and second ramp generators output first and second ramp voltages. The column lines include first and second column lines adjacent to each other in the second direction. The samplers include first and second samplers disposed adjacently in the first direction. In a first mode, the first and second samplers are electrically connected to the first ramp generator and electrically separated from the second ramp generator. In a second mode, the first sampler is electrically connected to the first ramp generator among the first ramp generator and the second ramp generator, and the second sampler is electrically connected to the second ramp generator among the first ramp generator and the second ramp generator.

To reduce sub-harmonic oscillations in a Switched-Mode Power Supply (SMPS). a ramp generator circuit of the SMPS produces a ramp signal having an amplitude corresponding to a sensed current through an energy storage device, such as an inductor, of the SMPS. The ramp signal is used to control a duty cycle of the SMPS. The ramp generator circuit may include a reference current circuit, a ramp capacitor, and a discharge circuit to periodically discharge the ramp capacitor. The ramp capacitor may be charged using a charging current produced by combining a feedback current corresponding to the sensed current with a reference current produced by the reference current circuit and may be periodically discharged at a fixed frequency, or may be charged using the reference current and discharged at a time determined according to the feedback current.