332 results about "Ramp generator" patented technology

A DC-DC converter including a Pulse Width Modulation (PWM) controller for converting an input voltage into an output voltage is provided. The PWM controller includes an error amplifier, a comparator, a PWM generator and a ramp generator. The error amplifier generates an error signal according to a difference between a reference voltage and the output voltage. The comparator compares the error signal with a ramp signal to generate a trigger signal. The PWM generator generates a PWM signal with a fixed turn-on time, wherein a frequency of the PWM signal is adjusted according to the trigger signal, the input and output voltages. The ramp generator generates the ramp signal according to the PWM signal, the input voltage and the output voltage.

A ramp generator includes a resistance ladder supplied with a constant current. Switches are closed in sequence by a shift register to provide a stepped ramp output. The constant current is controlled by referencing an on-chip bandgap voltage that is used as an input to a feedback circuit controlling current through a reference resistor ladder.

Synchronously stackable double-edge modulated pulse width modulation generators are disclosed. An example pulse width modulation generator includes a ramp generator to generate first and second ramp signals that interact to form a virtual ramp signal; and a comparator module coupled to the ramp generator configured to produce a pulse width modulated signal based on a comparison between the virtual ramp signal and an input signal.

A Class D amplifier comprises a ramp generator that generates a first reference signal and a second reference signal. A signal generator generates a first signal as the first reference signal exceeds an input signal to the Class D amplifier and generates the first signal as the second reference signal exceeds the input signal. The signal generator generates a second signal as the first reference signal falls below the input signal and generates the second signal as the second reference signal falls below the input signal.

A current replication circuit that avoids the LEB period restriction of a DC-DC boost converter. The DC-DC boost converter regulates an output voltage by switching an input voltage through an inductor and a diode using a switch controller employing current feedback control and providing a PWM signal to control a switch coupled to the inductor. The current replication circuit includes a current sensor, a ramp generator, and a summing device. The current sensor samples current through the inductor while the switch is off and provides a sample voltage indicative of inductor current just before the switch is turned on. The ramp generator provides a ramp voltage replicating current increase of the inductor while the switch is on. The summing device adds the sample voltage to the ramp voltage to develop a replication voltage used for feedback current control by the switch controller.

A control device for a switching power supply includes an frequency-hopping oscillator for generating an oscillating signal and an indication signal, an SR flip flop for outputting a driving signal according to the oscillating signal and the indication signal, to control a primary winding of a transformer of the switching power supply, a comparator for comparing a current sense signal of the primary winding and a subtraction result, to output the comparison result to the SR flip flop, a ramp generator for generating ramp signals with time-varying slopes, and a subtraction unit for performing a subtraction operation on a feedback signal and the ramp signals, to generate the subtraction result for the comparator.

The invention relates to the field of digital-analog hybrid integrated circuit design, aims to increase the conversion rate of a monoclinic ADC and provides the analog-digital converter which is simple in structure and low in power consumption. According to the adopted technical scheme of a low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and a converter, the converter is composed of a ramp generator, a counter, comparators, multiplexer switches and a register; the ramp generator generates a ramp voltage Vramp and k reference voltages VrefK, wherein K=1, 2, 3..., K; each of the k reference voltages VrefK is supplied to the corresponding comparator through one of the corresponding multiplexer switches; the ramp voltage Vramp is supplied to each comparator. The low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and the converter are mainly applied to digital-analog hybrid integrated circuit design.

The invention is directed to an amplifier circuit based on the principle of a class D amplifier. To avoid unwanted convolution effects and to improve the power supply rejection ratio, provision is made for the amplitude of the ramp signal used for pulse width modulation to track proportionally the supply voltage for the amplifier circuit. For this purpose, the ramp signal generator has an amplitude control input suitably connected to supply and reference potentials. This ensures a constant duty ratio which is independent of the supply voltage. The present circuit may be used, for example, as a DC/DC converter or as an audio amplifier.

Methods and structures for ensuring the highly linear discharge of a capacitor used for slew rate control of a power driving stage from a maximum voltage to a minimum supply voltage, such as ground. A voltage ramp generator uses a single cascoded current source to achieve the linear ramp-down.

A control system that can accommodate the wide variations in the output of a generator, such as a permanent magnet alternator, while providing an output with relatively uniform phase ripple. The control system includes a zero crossing detector and variable ramp generator for generating control signals to a switching rectifier to generate a regulated DC signal.

A one cycle power factor correction converter circuit comprising a switch for controlling a DC output voltage of the converter circuit, the switch being switched by a drive signal having a frequency determined by a clock signal; the converter circuit being provided with a DC input voltage and producing the DC output voltage, the DC input voltage being rectified from an AC input; a controller circuit for controlling an on-time or off-time of the switch to set the output voltage and to achieve power factor correction at the AC input; the controller circuit comprising an error amplifier receiving a feedback voltage from the output of the converter circuit and a reference voltage and producing an error signal; a ramp generator receiving the error signal and generating a first ramp signal by integrating a signal related to the error signal; a pulse width modulation circuit receiving the first ramp signal and a signal related to the error signal and producing a pulse width modulated signal by comparing the first ramp signal and the signal related to the error signal; the pulse width modulated signal determining the on-time or off-time of the switch to control the output voltage with power factor correction; further comprising a circuit for terminating the first ramp signal when a predetermined inequality exists between the first ramp signal and a reference signal and for developing the clock signal from the first ramp signal.

The invention discloses a column parallel analog-to-digital converter, a pixel photosensitive value output method and a CMOS image sensor. The column parallel analog-to-digital converter comprises a ramp generator, a counting unit and multiple column analog-to-digital converters, each column analog-to-digital converter corresponds to one row of pixel units of a pixel array and comprises a comparison processing unit and a storage unit, and each comparison processing unit comprises a capacitor, a switching module and a comparator. The column parallel analog-to-digital converter can shorten analog-to-digital conversion time and improve conversion efficiency.