108results about "Pulse generator" patented technology

The invention discloses an eddy current displacement sensor sine constant current source excitation method, and belongs to the technical field of sensor measurement and control. The method comprises the following steps: S1, generating positive and negative symmetric reference voltages through a reference voltage source circuit; s2, outputting a square wave control signal with adjustable frequency by the control chip, and driving a switching circuit to generate a square wave taking the positive and negative reference voltage as a level; s3, processing the square wave through a filter circuit to obtain a standard sine wave voltage signal; and S4, converting the sine voltage signal into sine constant current source excitation through a Howland current source circuit, and outputting the sine constant current source excitation to a sensor probe coil. According to the invention, through combination of digital control and analog conversion, the circuit structure is simplified, the cost is significantly reduced, and convenient adjustment of the output frequency and high stability and precision of the output current are realized at the same time.

The invention provides a ramp signal generation circuit and a ramp signal generation method for a power converter. The ramp signal generating circuit compensates the slope of the ramp signal according to the slope compensation curve, and non-linearly adjusts the slope of the ramp signal in a predetermined duty ratio interval of a current ripple offset point of the power converter. The ramp signal generation circuit disclosed by the invention is particularly suitable for a multi-phase power converter and a multi-level power converter, and can effectively solve the problem of gate pulse mixing near a current ripple offset point. By adopting the slope modulation technology, the circuit optimizes the dynamic response performance while keeping the stability of the system. In a working interval of a non-current ripple offset point, the circuit maintains a lower slope signal slope to ensure the system bandwidth. In the preset duty ratio interval near the current ripple offset point, the slope of the ramp signal is smoothly improved in a nonlinear adjustment mode, so that the problem of system oscillation caused by sudden change of the slope in a traditional scheme is avoided.

The invention provides a driving circuit, a fast charge protocol chip and electronic equipment, and relates to the technical field of power management chips, the circuit comprises a ramp voltage generation circuit and a class AB operational amplifier circuit, the ramp voltage generation circuit comprises a controllable current source circuit, a first capacitor and a clamping circuit, and the controllable current source circuit comprises a current branch; the controllable current source circuit obtains a first current and a second current according to the first digital signal, and the magnitude of the first current and the magnitude of the second current are in positive correlation with the number of the current branches; the first capacitor charges itself according to the first current and discharges itself according to the second current to obtain a ramp voltage signal; the clamping circuit clamps the ramp voltage signal according to the first digital signal and the reference voltage to enable the ramp voltage signal to be lower than the reference voltage; the class AB operational amplifier circuit amplifies the ramp voltage signal to obtain a second digital signal. Therefore, the circuit is suitable for wide-range load capacitance, and has a high power supply rejection ratio.

Provided is a buffer circuit that can realize a wide dynamic range, a reduced area, and a reduced power consumption amount while maintaining low output impedance. The buffer circuit includes a first transistor, a current source, a second transistor, an output terminal, and first and second capacitors. The first transistor has a gate to which an input signal is input. The current source is connected to one terminal of the first transistor. The second transistor is connected to the other terminal of the first transistor. The output terminal is connected to the one terminal or the other terminal of the first transistor. The first and second capacitors are between the current source and the gate of the second transistor. The first transistor, the second transistor, and the first capacitor form a first feedback circuit. The first transistor, the current source, and the second capacitor form a second feedback circuit.

A ramp driver includes a ramp generator for generating a reference ramp signal, and a ramp delayer for sequentially outputting ramp signals based on the reference ramp signal, and including delay blocks including k output terminals, k being an integer greater than or equal to 2, wherein the delay blocks include k delay circuits sequentially connected to each other, respectively connected to the output terminals, and configured to receive an input ramp signal from a previous one of the delay circuits, receive an input gate clock signal from a previous delay circuit, output an output ramp signal by delaying the input ramp signal, and output an output gate clock signal by inverting the input gate clock signal.

The invention provides a digital isolator with both high-speed communication and high common-mode transient immunity. The digital isolator comprises a transmitter, a coupling inductor and a receiver, the transmitter comprises an oscillator, a modulation capacitor assembly and a common-mode transient immunity enhancement module; the oscillator is configured to receive a data signal and generate a first differential signal based on the data signal; the modulation capacitor assembly is configured to modulate a code element 0 into a first frequency and modulate a code element 1 into a second frequency; the common-mode transient immunity enhancement module is configured to determine a bias control signal according to the first differential signal; the receiver is configured to receive the second differential signal and obtain a square wave signal based on the second differential signal; obtaining a triangular wave signal based on the square wave signal; obtaining the maximum value of a triangular wave signal according to the falling edge signal of the square wave signal; and obtaining a target data signal based on the maximum value, so as to solve the problem of low communication and common-mode transient immunity performance of the existing digital isolator.

Devices and methods may include receiving a square wave having a frequency at an input of a harmonic-cancellation (HC) sine-wave generator; receiving a clock signal having a clock frequency at a clock input of the HC sine-wave generator; generating one or more delayed square waves based on the received square wave and the clock signal using one or more delay components of the HC sine-wave generator; and amplitude-scaling the square wave and the one or more delayed square waves using a plurality of taps of the HC sine-wave generator to produce a plurality of amplitude-scaled square waves. The method may include adding the plurality of amplitude-scaled square waves using summing circuitry of the HC sine-wave generator to produce a sine wave having tone at the frequency with suppressed signal strength at selected harmonics of the frequency of the square wave at an output terminal of the HC sine-wave generator.

This invention discloses a high-precision ramp generator and a two-step single-slope analog-to-digital converter. The ramp generator includes a bandgap reference source circuit, a voltage-to-current conversion circuit, a weighted current DAC current source array, a charge / discharge current regulation circuit, a mode switching circuit, and a bias circuit. In this invention, the quantization process of the ramp generator is decomposed into two stages: coarse quantization and fine quantization, significantly reducing quantization time. Furthermore, a single output stage can combine a DAC-type ramp generator and a capacitor-integrating ramp generator, saving area and power consumption in chip design, improving the compatibility of the ramp generator, solving the linearity and stability problems introduced by stepped ramps in high-speed, high-precision applications, and reducing design complexity.

Reduce radiated noise through frequency spreading of clock signals. [Solution] The clock signal generation circuit (10) includes a first modulation signal generation circuit (11) that generates a first modulation signal (Sm1) having a first frequency (f1), a second modulation signal generation circuit (12) that generates a second modulation signal (Sm2) having a second frequency (f2) lower than the first frequency, a signal synthesis circuit (13) that generates a synthetic modulation signal (Smc) by synthesizing the first modulation signal and the second modulation signal, and an oscillator (14) that generates a clock signal (CLK) having a frequency corresponding to the synthetic modulation signal.

A control apparatus includes a first signal generator configured to generate a first reset signal for determining an on-time of a high-voltage side switch of a first phase of a multi-phase power converter; a first comparator configured to generate a first set signal for determining a conduction moment of the high-voltage side switch of the first phase based on comparing the first current sensing signal and the voltage control signal; a first zero-crossing detection circuit configured to detect a zero-crossing point of the inductive current of the first phase; and a first phase bias voltage generator configured to generate a first bias voltage for configuring the first phase to exit the first continuous conduction mode when a zero crossing point of the inductive current of the first phase is detected.

A ramp generator is provided that allows for an increase in the swing range of the ramp signal. [Solution] The lamp generator 10 has multiple control signals CON <n:0>Based on this, the current value of the reference current IREF applied to the first node ND1 is adjusted, and multiple control signals CON are used. <n:0>The system may include a current control unit 300 that controls the current value of the current applied to the second node ND2 based on some of the control signals, a bias voltage generation unit 500 that generates bias voltages VBIAS1 and VBIAS2 based on currents mirrored according to the first node ND1 and the second node ND2, and a ramp signal generation unit 600 that generates a ramp signal VRAMP based on the bias voltages VBIAS1 and VBIAS2.< / n:0>

The present invention relates to a digital amplifier for outputting a pulse-width-modulated output switching signal by amplifying a pulse-width-modulated digital input signal, the amplifier minimizing pulse error between the pulse-width-modulated digital input signal and a PWM pulse signal at the rear of a comparison unit according to audio information so that the distortion rate of an output audio signal can be alleviated and error amplifier characteristics can be enhanced, and being capable of minimizing wafer area and production costs when implemented as a semiconductor integrated circuit.

A voltage converter includes a conversion circuit having an inductor connected to a switching node, a first switching element connected between the switching node and a ground voltage, and a second switching element connected between the switching node and an output node, and a switching control circuit configured to adjust a feedback voltage divided from an output voltage of the output node based on a current state of the inductor, and configured to generate a switching control signal based on a sense signal according to a current of the inductor and the adjusted feedback voltage, for charging the inductor with an input voltage and discharging a voltage charged in the inductor.

The invention relates to an electronic circuit (10) configured to generate a ramp current signal for a receiver circuit (30), the electronic circuit (1) comprising: a first current unit (20) comprising a first current source (55), a trigger input (25) for activating the first current source (55), and a trigger output (26); a second current unit (21) comprising a second current source (55 '), a trigger input (25) for activating the second current source (55'), and a trigger output (26), the trigger output (26) of the first current unit (20) being connected to the trigger input (25) of the second current unit (21); and a current supply module (24) connected to an input of the receiver circuit (30) and selectively connectable to any one of the first current source (55) and the second current source (55 ').

A waveform generator includes: a system control unit (2) and a plurality of channels, (3.1, ..., 3.N) controlled by the system control unit (2) and configured to supply driving signals (V1, ..., VM) for driving an array of transducers (5.1, ..., 5.N). Each channel includes: a sequential access memory (10) having a plurality of rows, each containing instruction words (W) for generating a respective step of a respective one of a plurality of waveforms, and a memory output (10a) defined by an output row at a fixed location. The sequential access memory (10) contains blocks of instruction words (W), each defining a respective waveform. Each channel also includes an internal control unit (12), configured to sequentially move the content of the sequential access memory (10), based on the instruction word (W) currently at the memory output (10a), so that sequences of instruction words (W) are provided at the output row (10a). A starting instruction word (W) of each block of instruction words (W) defining the waveform contains an identification tag (WT) identifying the waveform. The internal control unit (12) receives a reference tag (TR) from the system control unit (2) and sequentially shifts the sequential access memory (10) until one of the starting instruction words (W) that contains an identification tag (WT) matching the received reference tag (TR) is moved to the memory output (10a).

System for generating customized waveforms include a plurality of DC-DC converter cells coupled in series to form a stack; and a controller to generate control signals to drive the DC-DC converter cells in the stack to generate a customized waveform at a node, the controller comprising a lookup table to store at least one characteristic affecting the customized waveform, wherein the control signals to each of the plurality of DC-DC converter cells are based at least in part on the at least one characteristic.

The present disclosure relates to techniques for measuring slew rate in a current integrating phase interpolator. An apparatus is described that includes a current integrating phase interpolator core having a programmable bias current; an inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal containing a periodic sawtooth waveform therefrom; a digital-to-analog (D / A) converter for setting an input common mode voltage of the inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuit; and a circuit for calculating a difference between a first state of the DCD of the clock signal corresponding to the inverter circuit being set to a high voltage input common mode voltage and a second state of the DCD of the clock signal corresponding to the inverter circuit being set to a low voltage input common mode voltage.

The utility model relates to the technical field of power electronics, and discloses a signal generating circuit which comprises a square wave generating circuit, a triangular wave generating circuit and a trapezoidal wave generating circuit, an external power supply voltage is input into the power supply end of the square wave generating circuit, and a driving signal is input into the input end of the square wave generating circuit. The output end of the square wave generation circuit is connected with the input end of the triangular wave generation circuit; the output end of the triangular wave generation circuit is connected with the input end of the trapezoidal wave generation circuit, a first power supply end of the triangular wave generation circuit inputs first power supply voltage, and a second power supply end of the triangular wave generation circuit inputs external power supply voltage; the power supply end of the trapezoidal wave generation circuit inputs second power supply voltage; the external supply voltage is greater than the second supply voltage. The signal generating circuit is high in reliability, high in integration level and suitable for multi-path output scenes.

The invention provides a ripple signal generation circuit and a switching converter, and the ripple signal generation circuit comprises a first signal unit which comprises a first adjustment module and a first output module; the second signal unit comprises a second adjusting module and a second output module, and an output node of the second output module is connected with a second node of the first output module; in the switching period, the first adjusting module and the second adjusting module work cooperatively to adjust the voltage of the first node and the output node of the first output module, and a ripple signal is obtained according to the voltage difference value of the first node and the output node. The ripple signal generation circuit provided by the invention mixes the triangular wave signal and the sawtooth wave signal to generate the ripple signal. Therefore, the ripple signal not only has the advantages of the triangular wave signal to ensure the stability of the system, but also has the advantages of the sawtooth wave signal to improve the dynamic response performance of the system.

Embodiments of the present disclosure relate to an oscillator. A series of first ramps and second ramps are generated. A circuit delivers a first signal representing a comparison of each first ramp to a setpoint, and delivers a second signal representing a comparison of each second ramp to the setpoint. Based on the first and second signals: when a first ramp reaches the setpoint, the first ramp is stopped and a second ramp is started; and when a second ramp reaches the setpoint, the second ramp is stopped and a first ramp is started. The setpoint is modulated in response to a maximum of the first / second ramps compared to the setpoint.

Provided are a display drive circuit and a display device capable of curbing fluctuation of a signal line voltage. A display drive circuit includes a ramp wave voltage generation circuit that generates a ramp wave voltage whose voltage level changes with time, and a signal line voltage generation circuit that holds the voltage level of the ramp wave voltage at a timing corresponding to a signal level of a pixel signal and generates a signal line voltage. The ramp wave voltage generation circuit includes an amplifier that outputs the ramp wave voltage, a load circuit arranged on a feedback path of the amplifier, and a current generation circuit that controls a current flowing through the load circuit such that the ramp wave voltage matches a reference voltage.

An electronic device may include an inverter. The inverter may receive the switching signal based on the jitter clock signal and output a corresponding AC signal to the wireless power transfer coil. The dithered clock signal may have a plurality of frequency steps during a repetition period of the dithered clock signal. The repetition period of the jitter clock signal may include a step function that approximates a triangular waveform, wherein the step has a unique magnitude of frequency during the repetition period.

The application provides a clock signal sinusoidal jitter calculation method, a computer device and a readable storage medium. The method comprises the following steps: obtaining frequency spectrum information of a to-be-tested clock signal injected with a sinusoidal jitter signal; identifying a plurality of target frequency points in the frequency spectrum information of the to-be-tested clock signal with a period of the sinusoidal jitter signal as a time interval, and determining amplitudes of the to-be-tested clock signal at the target frequency points; determining orders of the target frequency points according to the amplitudes of the to-be-tested clock signal at the target frequency points, and calculating an amplitude of the sinusoidal jitter signal by using the amplitudes corresponding to the target frequency points of each order based on a preset target function. The application also provides a computer device and a readable storage medium for implementing the above method. The application can reduce the amplitude calculation cost of the sinusoidal jitter signal and improve the accuracy of the amplitude calculation of the sinusoidal jitter signal.

A voltage ramp generator includes unit cells (331) electrically connected in parallel. Each unit cell switches between an on-state and an off-state in response to a cell-specific select signal (S1-Sn). A current mirror circuit (350) copies a reference current controlled by the unit cells at a predefined current ratio into a first detector current flowing in a first detection branch. An error detection circuit (390) generates an active first error signal (ERR) if the first detector current falls below a lower threshold current or exceeds an upper threshold current.

A switching voltage generating device includes an amplifier configured to generate an error voltage, based on a adjusting target voltage of the voltage converting circuit and a detection voltage of the voltage converting circuit, a clock voltage generating circuit configured to generate a clock voltage having a frequency corresponding to the error voltage, based on the error voltage, a first fold reference voltage, and a second fold reference voltage, and to generate a clock switching voltage based on the error voltage and the switching reference voltage, a triangular voltage generating circuit configured to generate one or more triangular voltages having a cycle corresponding to a cycle of the clock voltage based on the clock switching voltage and the clock voltage, and a switching voltage generating circuit configured to generate the switching voltage based on the one or more triangular voltages and the error voltage.

Provided is a novel semiconductor device. In this semiconductor device, a first terminal of a first transistor is connected to a first terminal of a second transistor, a gate of a third transistor, and a first terminal of a first capacitive element. A first terminal of the third transistor is connected to a first terminal of a fourth transistor. A second terminal of the first transistor is connected to a first terminal of a fifth transistor. The channel length of the first transistor is greater than the channel length of the third transistor. The channel length of the third transistor is greater than the channel length of the second transistor. Signals of mutually inverted logic are applied to a gate of the second transistor and a gate of the fifth transistor.

A clock signal generation circuit (10) includes: a first modulation signal generation circuit (11) that generates a first modulation signal (Sm1) having a first frequency (f1); a second modulation signal generation circuit (12) that generates a second modulation signal (Sm2) having a second frequency (f2) lower than the first frequency; a signal combining circuit (13) that generates a composite modulation signal (Smc) by combining the first modulation signal and the second modulation signal; and an oscillator (14) that generates a clock signal (CLK) having a frequency according to the composite modulation signal.

The invention provides a triangular wave generation circuit, a D-type audio power amplifier, a chip and electronic equipment, and relates to the technical field of electronic circuits. The circuit comprises a logic generation circuit, an overvoltage detection circuit and a triangular wave generation sub-circuit, the logic generation circuit generates a triangular wave reference clock signal according to an external clock signal, and generates a first switching reference signal when the bridge switching signal generates a first switching action; the overvoltage detection circuit switches a triangular wave amplitude threshold according to the first switching reference signal, and sends an overvoltage indication signal to the logic generation circuit when determining that the triangular wave signal is overvoltage based on the threshold, so that the logic generation circuit outputs a triangular wave switching signal to the triangular wave generation sub-circuit; and when the triangular wave generation sub-circuit receives the triangular wave switching signal, the voltage of the triangular wave signal is frozen under the control of the triangular wave reference clock signal until the direction is changed when the next trigger edge of the external clock signal arrives. According to the invention, smooth switching of triangular waves can be realized.