15results about "Pulse generator" patented technology

A ramp generator is provided that allows for an increase in the swing range of the ramp signal. [Solution] The lamp generator 10 has multiple control signals CON <n:0>Based on this, the current value of the reference current IREF applied to the first node ND1 is adjusted, and multiple control signals CON are used. <n:0>The system may include a current control unit 300 that controls the current value of the current applied to the second node ND2 based on some of the control signals, a bias voltage generation unit 500 that generates bias voltages VBIAS1 and VBIAS2 based on currents mirrored according to the first node ND1 and the second node ND2, and a ramp signal generation unit 600 that generates a ramp signal VRAMP based on the bias voltages VBIAS1 and VBIAS2.< / n:0>

An electronic device may include an inverter. The inverter may receive the switching signal based on the jitter clock signal and output a corresponding AC signal to the wireless power transfer coil. The dithered clock signal may have a plurality of frequency steps during a repetition period of the dithered clock signal. The repetition period of the jitter clock signal may include a step function that approximates a triangular waveform, wherein the step has a unique magnitude of frequency during the repetition period.

Provided is a novel semiconductor device. In this semiconductor device, a first terminal of a first transistor is connected to a first terminal of a second transistor, a gate of a third transistor, and a first terminal of a first capacitive element. A first terminal of the third transistor is connected to a first terminal of a fourth transistor. A second terminal of the first transistor is connected to a first terminal of a fifth transistor. The channel length of the first transistor is greater than the channel length of the third transistor. The channel length of the third transistor is greater than the channel length of the second transistor. Signals of mutually inverted logic are applied to a gate of the second transistor and a gate of the fifth transistor.

An output buffer includes a first transistor, a second transistor, and a pad tracking circuit. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad tracking circuit is coupled to the first transistor and is configured to generate a gate control signal to a gate of the first transistor. The output buffer is selectively operable in an input mode and a failsafe mode, and the pad tracking circuit generates the gate control signal to the gate of the first transistor based on a voltage of the pad when the voltage of the pad is a high voltage level.

Methods and devices for performing ablation. In some examples an ablation delivery system is configured to allow separate voltage levels of a capacitor stack to be accessed for use in therapy delivery. Ablation therapy systems switchable between current and voltage controlled output are described. Methods of treating a patient using adjustable interphase or interpulse delay are disclosed as well.

The utility model discloses a kind of circuit structure of receiving FSK modulated signal, it is related to network communication technical field, the circuit structure includes FSK modulated signal filter circuit, square wave conversion circuit;The square wave conversion circuit includes comparator, voltage reference chip;The comparator is provided with voltage input end and signal input end;The reference voltage chip is connected to the voltage input end, the FSK modulated signal filter circuit is connected to the signal input end, the output end of the comparator is connected to square wave signal output end;Reference voltage chip and the voltage input end between being provided with voltage dividing resistor, to convert sine wave signal.

The present application relates to a class-D amplifier. The class-D amplifier includes a loop filter configured to receive first and second feedback signals, and receive first and second input signals through first and second resistors, respectively, and filter the first and second input signals and the first and second feedback signals to generate first and second filtered signals; a triangle wave generator configured to generate a triangle wave based on first and second reference voltages; first and second comparators configured to compare the first and second filtered signals to the triangle wave to generate first and second pulse width modulation signals, respectively; first and second driver circuits configured to generate first and second output signals based on the first and second pulse width modulation signals, respectively; and a reference voltage generator circuit configured to generate the first and second reference voltages based on a control signal.

A waveform generator includes: a system control unit (2) and a plurality of channels, (3.1, ..., 3.N) controlled by the system control unit (2) and configured to supply driving signals (V1, ..., VM) for driving an array of transducers (5.1, ..., 5.N). Each channel includes: a sequential access memory (10) having a plurality of rows, each containing instruction words (W) for generating a respective step of a respective one of a plurality of waveforms, and a memory output (10a) defined by an output row at a fixed location. The sequential access memory (10) contains blocks of instruction words (W), each defining a respective waveform. Each channel also includes an internal control unit (12), configured to sequentially move the content of the sequential access memory (10), based on the instruction word (W) currently at the memory output (10a), so that sequences of instruction words (W) are provided at the output row (10a). A starting instruction word (W) of each block of instruction words (W) defining the waveform contains an identification tag (WT) identifying the waveform. The internal control unit (12) receives a reference tag (TR) from the system control unit (2) and sequentially shifts the sequential access memory (10) until one of the starting instruction words (W) that contains an identification tag (WT) matching the received reference tag (TR) is moved to the memory output (10a).

A signal generation circuit includes: a reference voltage generation circuit configured to generate a reference voltage; a ramp voltage generation circuit configured to generate a ramp voltage that varies within a predetermined voltage range; and a comparison circuit configured to output a comparison result signal that indicates the magnitude relationship between the reference voltage and the ramp voltage. The reference voltage generation circuit gives the reference voltage a waveform of a triangular wave and varies the frequency of the triangular wave.

According to one aspect, a wireless charging transmitter device is proposed comprising: - a generation circuit comprising at least one circuit (ECRCT1, ECRT2) for producing a square signal comprising: - a first switching circuit (PCOM) with PMOS type transistors comprising a group of transistors (PMOSP) with PMOS type performance and at least one transistor (PMOSF) with PMOS type functionality, - a second switching circuit (NCOM) with NMOS type transistors comprising a group of connected NMOS type performance transistors (NMOSP) and at least one NMOS type functionality transistor (NMOSF).

The application discloses a kind of full-automatic hardware intervention method and device of pulse width modulation signal, method includes: S1, the extreme point of triangular carrier signal is set as absolute center;S2, by bottom hardware logic gate, an absolute symmetrical time execution window is automatically demarcated to two sides of absolute center;S3, when the count value enters time execution window, bottom hardware logic gate is configured to ignore current main duty cycle setting and carry out forced operation, for the level of PWM output channel is set or cleared;S4, carry out hardware level automatic flip: in successive PWM period, carry out hardware level automatic flip, for in fundamental center seamless superimposed alternating high-frequency square wave signal.The application introduces independent physical execution window and polarity automatic flip mechanism in the bottom digital logic of microcontroller timer, realizes high-frequency alternating voltage injection and accurate waveform clipping under zero CPU computing power consumption, completely eliminates phase distortion and risk of magnetic bias.

The present disclosure relates to an LED driver electromagnetic interference mitigation. An apparatus includes a digital ramp generator comprising a delay line including one or more delay elements and an oscillator, wherein the digital ramp generator is configured to generate a code based on respective outputs of the one or more delay elements; a digital-to-analog converter coupled to the digital ramp generator, wherein the digital-to-analog converter is configured to generate a reference signal, wherein the reference signal is generated based at least in part on the code; and a driver coupled to the digital-to-analog converter, the driver configured to generate a drive current based at least in part on the reference signal.

A ramp generator, capable of generating a ramp signal from an image sensor, includes a current controller, a bias voltage generator, and a ramp signal generator. The current controller adjusts a value of a reference current applied to a first node based on a plurality of control signals, and it adjusts a value of a current applied to a second node based on some control signals from among the plurality of control signals. The bias voltage generator generates a bias voltage based on a current mirrored according to the first node and the second node. The ramp signal generator generates a ramp signal based on the bias voltage.