109 results about "FLOPS" patented technology

The invention discloses a large language model progressive field fine tuning and knowledge fusion method for shield engineering. The method comprises the following steps: constructing a layered shield training course containing a wide-area academic theory and a proprietary enterprise construction method; parallelly training a plurality of physically isolated parameter efficient adapters based on the frozen base; performing singular value decomposition on the adapter, extracting a geometric feature subspace representing knowledge distribution, and calculating a conflict correlation degree; based on this, a uniform adaptation mechanism of resource awareness is constructed. The mechanism not only can generate a static fusion model for conflict removal, but also can dynamically activate a specific rank slice of an adapter through a routing network based on real-time hardware resource budget (video memory / FLOPs) and geometry-resource signature. According to the method, multi-source knowledge is reserved, and adaptive dynamic scheduling of edge hardware resources by model reasoning is realized.

The invention discloses a lightweight ViT based on image feature cutting and cloud edge knowledge distillation, belongs to the technical field of computer vision and edge computing, is used for efficiently deploying a ViT model on an edge device with limited computing power, and comprises the steps of designing a lightweight ViT Block and a sub-sampling Block. The method comprises the following steps: designing an image feature cutting module, collecting images by edge equipment, screening highly uncertain samples in the images as a knowledge distillation data set, and transmitting the knowledge distillation data set and local model parameters to a cloud end. A ViT model is deployed for the edge equipment with limited resources and weaker performance to carry out an image processing task, and the ViT is subjected to lightweight processing; therefore, the Flops of the model is reduced while the accuracy of the model is ensured.

An apparatus, including: a first multiplexer including inputs configured to receive an input data signal and a scan signal, and a select input configured to receive shift control signal; a first latch including an input coupled to an output of the first multiplexer, and a complementary (e.g., inverting) clock input configured to receive a clock signal; a second latch including an input coupled to the output of the first multiplexer, and a non-complementary clock input configured to receive the clock signal; and a second multiplexer including inputs coupled to outputs of the first and second latches, respectively, a select input configured to receive the clock signal, and an output configured to generate an output data or scan signal.

A clock domain crossing (CDC) circuit receives a first data. The CDC circuit includes a first buffer and a second buffer. The first buffer includes a single-clock static random-access memory. The second buffer includes a plurality of data flip-flops. Logic coupled to the first buffer and the second buffer can determine that first buffer is not full at a first time. Responsive to the determination that the second buffer is not full at the first time, the processing logic can bypass the first buffer to write the first data to the second buffer according to the first clock domain. The processing logic can provide the first data as output from the second buffer according to the second clock domain.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The invention discloses a computing resource evaluation method for a meteorological large model. The method comprises the following steps: step (1), computing and evaluating parameters of the meteorological large model; step (2), calculating and evaluating the meteorological large model FLOPs; (3) calculating and evaluating the occupation of the video memory of the meteorological large model; and step (4), distributed communication evaluation of the meteorological large model. According to the invention, a multi-granularity computing resource joint evaluation framework is proposed for the first time, and the framework establishes a parameter quantity calculation model, a space-time perception FLOPs evaluation model, a video memory occupation model and a distributed communication analysis model through sub-modules and combines space-time heterogeneity characteristics of meteorological data to realize quantification of hardware resources by a meteorological large model.

The invention provides a video target segmentation method and system based on instance-level enhancement, and belongs to the field of computer visual perception of artificial intelligence. On the basis of an existing SAM2 baseline model, an instance-level query and interaction module and a memory encoder are added, so that the algorithm can form overall cognition on a target from top to bottom. Compared with a traditional pixel-level identification method, the method can remarkably improve the target tracking and segmentation accuracy in a complex scene. The method has excellent generalization ability, and can maintain excellent zero sample learning performance even in extreme scenes such as shadow tracking and target disappearance reproduction. According to the method, a lightweight instance-level module is adopted, the calculation overhead is effectively reduced, the overall FLOPs is only increased by 3.5% compared with a baseline model SAM2, the theoretical reasoning time is infinitely long, and the design ensures that high performance is kept while excessive calculation burden is avoided.

A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path_failure_signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.

The invention belongs to the technical field of artificial intelligence neural networks, and particularly relates to a pure pulse-driven Transform neural network automatic architecture search method. A TransSpikingform network structure is combined, a pulse word segmentation device, a pulse Transform block and a classification head are included, and efficient feature extraction is achieved through a self-attention mechanism and pulse neuron characteristics. The invention further provides a method based on non-training neural architecture search, an optimal model is quickly screened by defining a search space and generating a candidate architecture and taking FLOPs as an index, and an evolutionary algorithm is combined for iterative optimization, so that the method adapts to different resource constraints. The method shows higher accuracy and remarkable energy consumption advantages on different data sets, can automatically search for an optimal model structure according to resource constraints, and is suitable for various equipment resource conditions. Through an innovative SN-ConvBN pulse residual connection structure, non-pulse calculation in traditional residual connection is avoided, it is ensured that all operations conform to the event-driven principle, and energy consumption is remarkably reduced.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The application provides a scan test method, comprising: constructing a single stuck-at fault scan forest, the scan forest comprising a plurality of scan inputs and a plurality of scan trees, each scan input being driven by an ATE; each pin of the ATE driving a plurality of demodulators, each demodulator driving a plurality of scan trees, each scan tree corresponding to each demodulator being controlled by different clock signals of a gate logic, each scan tree comprising a plurality of scan chains, and each scan chain comprising a plurality of scan flip-flops; and based on the constructed single stuck-at fault scan forest, placing a test. The method can effectively reduce the calculation time and memory overhead.

This application relates to a power estimation system. A method for power estimation for integrated circuit design includes loading a test vector into a first sequence of flip-flops in scan mode, evaluating the test vector in scan mode and saving the results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vector is received from an automatic test pattern generator.

The present invention relates to a radiation-resistant D-type flip-flop based on interconnect crosstalk calculation. The flip-flop comprises a cascaded structure of a master latch module and a slave latch module. The master latch module converts input signals into dual-node redundant signals via a first interconnect crosstalk circuit (CC1), utilizing L1-L3 and L2-L3 capacitive coupling to implement logical storage where only two high-level inputs trigger high-level outputs. The slave latch module generates redundant signals L4 / L5 via a second interconnect crosstalk circuit and uses a Muller C unit to perform error correction on CC2 outputs and direct transmission signals. The D-type flip-flop requires only 16 minimum-size transistors, a 67% reduction compared to conventional TMR flip-flops. It supports asynchronous reset, forcing L3 / L6 to charge to a high level during reset. The capacitive coupling strength is controlled through metal layer routing, significantly improving the reliability of aerospace electronic systems in radiation environments.

The invention discloses a discrete dung beetle optimized adaptive scanning VMama image denoising method, and relates to the field of image processing. In order to solve the problems of computation redundancy and denoising detail loss caused by a fixed scanning path of an existing VMama network, a hybrid coding space containing the number of network layers, state dimensions and binary scanning masks is constructed. According to the method, an S-type transfer function is introduced to improve a discrete dung beetle algorithm, an optimal architecture is adaptively searched by using behaviors such as rolling and dancing of a dung beetle population, a scanning path of an SS2D module is dynamically pruned according to a binary mask, performance is evaluated by fusing a fitness function of PSNR and FLOPs, and finally, a de-noised image is output based on the optimal architecture. According to the method, the balance between the denoising quality and the reasoning speed is effectively realized, and the model calculation amount is reduced.

The invention relates to a single-particle selective reinforcement method based on machine learning. The method comprises the steps of reading basic information and structural information of a trigger in a target circuit; part of triggers are randomly extracted for fault injection, and the soft error rate and the function masking rate of the triggers are counted to obtain a gold model; respectively training weight factors of different features for the soft error rate and the function masking rate through a golden model; clustering all triggers in the circuit by using a feature weighted K-Means classifier for the soft error rate and the function masking rate respectively; sensitive triggers in the circuit are determined and selectively reinforced by arranging the product of the soft error rate and the function masking rate. According to the method, the frequency of fault injection required by the circuit is reduced, so that the efficiency is improved, and the method can be used for selective design reinforcement for coping with single-particle soft errors in integrated circuit design.

A test circuit includes a plurality of normal flip-flops and a modified flip-flop. Each of the plurality of normal flip-flops includes a first input pin, a second input pin, and a first output pin, and is configured to selectively store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip-flop includes a third input pin, a fourth input pin, and a second output pin respectively coupled to a black box circuit, the plurality of normal flip-flops, and a plurality of combinational logic circuits, and is configured to selectively store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

This document describes technology for sequential logic circuitry with a topology of integrated clock gates (iCGs) that reduces clock logic depth by coalescing flip-flops with a low-depth fan-in cone and a high-depth fan-out cone. This technology includes sequential logic circuitry, including a first group of one or more flip-flops, which is coupled to and driven by a first cluster of one or more iCGs. The sequential logic further includes a first group of one or more target flip-flops, each target flip-flop having a low-depth fan-in cone and a high-depth fan-out cone and a first cluster of one or more clone iCGs coupled to the first group of target flip-flops and the first cluster of one or more iCGs. The first cluster of one or more clone iCGs configured to coalesce with the first cluster of one or more iCGs and drive the first group of one or more target flip-flops.

The present invention belongs to the field of electronic design automation technology and specifically discloses a method for optimizing the merging of D-type flip-flops. The method comprises: obtaining and classifying D-type flip-flops in a circuit by type; selecting pairs of D-type flip-flops of the same type and determining whether their preset control signals are from the same source; if the control signals are from the same source, performing an iterative structural comparison of the driving logic cones of their data input terminals; the iterative comparison is performed by initializing a source instance container and comparing the number and type of source instances in the container layer by layer, as well as the sources of their input signals; if the iterative comparison results indicate that the logic cone structures are equivalent, the D-type flip-flop pairs are determined to be equivalent and the circuits are merged and updated. The present invention can effectively cover complex logic structures, improve operational efficiency, and handle loops, thereby more effectively reducing design area and power consumption.

A system and a method of pattern selection are provided for use by an electronic design automation (EDA) automatic test pattern generator (ATPG) for improved intermediate resistance (IR) drop analysis. The method includes identifying, for each of a plurality of transitional delay fault (TDF) patterns, flip-flops (FFs) toggling during a capture window; identifying coordinates on a grid for each of the toggled FFs; generating a boundary around the toggled FFs; generating tiles within the boundary; determining a number of toggled FFs included within each of the tiles; and ranking the plurality of TDF patterns based on the number of toggled FFs included within each of the tiles of each of the plurality of TDF patterns.

The invention specifically discloses a clock tree synthesis method based on clustering and reinforcement learning collaborative optimization, and relates to the technical field of integrated circuit design and electronic design automation. The method comprises the following steps: firstly reading a trigger coordinate, a clock source position and a design constraint parameter in a circuit; secondly, performing clustering grouping on triggers in the circuit through a clustering method, generating an initial hierarchical clock tree topology and determining candidate insertion positions of buffers; constructing a reinforcement learning environment, and defining a state space, an action space and a multi-target reward function; then, respectively learning a trigger relocation strategy and a buffer insertion and removal strategy by maintaining an independent movement Q table and action Q table within the displacement constraint; and finally, evaluating clock skew, delay and other performances, generating a comprehensive performance evaluation result, and performing iterative optimization judgment through a closed-loop feedback mechanism. According to the method, the clock skew and delay are effectively controlled, the local optimum problem of a traditional method is avoided, and the comprehensive quality and the automation efficiency of the clock tree are improved.

A synchronizer with flip-flops has a reduced number of flip-flops coupled in series, receiving as an input data of a first clock domain and supplying as an output data in the second clock domain. The second clock signal is at a variable frequency adjusted to a target frequency, by a division factor. The flip-flops are timed by a clock signal subsampling the second clock signal by a factor k1. The subsampled clock signal is generated by a frequency divider propagating a pulse of the signal every k1 clock pulses, while keeping the edges aligned.

The invention discloses a circuit aging overcoming method based on a post-silicon regulation technology, and relates to the field of digital integrated circuit reliability design, and the circuit aging overcoming method comprises the steps: determining a slow path in a plurality of data paths in a monitored circuit, the target trigger in each low-speed path is connected with an establishment time violation early-warning unit, and the establishment time violation early-warning unit generates an establishment time early-warning signal when monitoring that the connected trigger is about to generate an establishment time violation; the target triggers of the multiple low-speed paths are divided into multiple trigger groups, each trigger group corresponds to one clock adjusting unit, and the target trigger of each low-speed path in each trigger group is connected with the corresponding clock adjusting unit; and the clock adjusting unit configures the clock edge delay arrival time of the connected trigger based on the establishment time early warning signal so as to realize the effect of overcoming circuit aging. The method can effectively overcome circuit aging and improve circuit reliability.

An example operation may include one or more of receiving a logical model of a circuit written in a hardware description language (HDL), the logical model of the circuit comprising normalized and ratioed clocks, and simulation-efficient edge-triggered latches or flip-flops, translating the logical model of the circuit into a physical model of the circuit in the HDL via a software application, wherein the translating comprises replacing the normalized and ratioed clocks in the logical model of the circuit with a base system clock, divider logic generating hold waveforms to achieve ratioed behavior, and pulse-enabled latches, and replacing the edge-triggered latches or flip-flops with pulse-generation logic and pulse-enabled latches, executing a formal verification which determines whether the logical model of the circuit is functionally equivalent to the physical model of the circuit, and displaying results of the formal verification via a graphical user interface (GUI) of the software application.

A system includes a memory that stores instructions and a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a circuit layout module that generates an initial circuit layout in response to a circuit netlist. The circuit netlist includes functional logic, the test-point nodes interconnecting portions of the functional logic, and a plurality of test-point flops associated with scan-chains. The EDA application also includes a test-point flop allocation module that divides the test-point nodes into test-point sharing groups based on a physical location of the test-point nodes and based on a test-point allocation parameter. The module relocates each of the test-point flops proximal to a test-point sharing group to generate an adjusted circuit layout associated with the circuit design. The adjusted circuit layout is employable to fabricate an integrated circuit (IC) chip.

A key generation technology of the present disclosure does not additionally set a combinational logic circuit on an original path of a scanning flip-flop, but utilizes a plurality of existing combinational logic circuits in a circuit system to generate multiple values of a key. Correspondingly, a key generation unit used in the key generation technology has two data flip-flops. One of the data flip-flops is used as a data flip-flop in one of a plurality of scanning flip-flops. The other data flip-flop is to obtain a node data signal of a node in the corresponding combinational logic circuit as one of the values of the key.

The application discloses a temperature measuring method based on Gaussian noise in the technical field of temperature measurement, and comprises the following steps: mixing a voltage signal output by a thermistor in a circuit with a Gaussian noise signal to obtain a mixed signal, amplifying the mixed signal through an amplifier, and dividing the mixed signal into two paths to obtain a first signal and a second signal which are completely same; the first signal is compared with a first threshold voltage through a first comparator, and the second signal is compared with a second threshold voltage through a second comparator; signals output by the comparators are sent to a digital circuit for sampling through flip-flops or latches, and then temperature values are obtained by calculation or table lookup in the digital circuit. The method superimposes Gaussian noise on the output signal of the thermistor, and then carries out code value probability statistics on the single-bit sampled data, so that the temperature measurement is realized, high-precision ADC is not needed, and the precision of temperature measurement can be improved by controlling the sampling frequency and sampling time.

The present invention proposes a multi-objective neural architecture search method and system based on a gradient similarity supernet. The method includes: constructing a supernet and generating shared weights through training. During the training process, a gradient norm importance sampling strategy is adopted to dynamically optimize the sampling probabilities of paths and data, and architectures and data that have a greater impact on weight updates are preferentially selected to improve efficiency. To address the gradient conflict in multi-objective optimization, the PCGrad projection method is introduced to calculate the gradient similarity dynamic dominant direction selection and gradient projection, reduce conflicts, and stabilize the optimization process. After the supernet is trained, the initial population inherits the shared weights, obtains performance on the target dataset, and performs non-dominated sorting and optimization through an evolutionary algorithm to ensure balanced performance on objectives such as accuracy, floating-point operations per second (FLOPS), and number of parameters. The present invention effectively reduces the computational cost and improves the efficiency and performance of neural network architecture search while ensuring balanced multi-objective optimization.

The invention discloses a generation method, device and system suitable for a hybrid-driven multi-bit trigger. The generation method comprises the following steps: acquiring all single triggers in a digital chip of which the initial layout design is completed; mapping each single trigger into a ternary trigger vector comprising a transistor size, a threshold voltage and a number, and generating a trigger matrix; splitting the trigger matrix into a plurality of independent sub-matrixes according to the clustering result of the single trigger, wherein each sub-matrix corresponds to one multi-bit trigger; repeating the following steps until the Pareto front is stable and meets a preset layout legalization verification condition to obtain a multi-bit trigger: by taking the normalized total negative margin and power consumption minimization as optimization objectives, optimizing each sub-matrix by adopting a proxy auxiliary differential evolution algorithm and a non-dominated sorting evolution algorithm to obtain a Pareto optimal solution set; and if the multi-bit trigger corresponding to the Pareto optimal solution set does not meet the layout legalization verification condition, re-dividing the trigger matrix. The clock network power consumption can be reduced, and the time sequence convergence rate is improved.

The present application relates to the field of voltage monitoring, and particularly to a voltage change monitoring system. The system includes: N series-connected delay units and their corresponding D flip-flops, a processor, and a memory storing a computer program. When the computer program is executed by the processor, different delay sampling values are output by the multiple series-connected delay units under different voltages, and thus reference positions corresponding to different voltages are obtained. According to the comparison of the reference positions, the monitoring result of the voltage change is determined, realizing the indirect monitoring of the voltage, improving the flexibility of voltage monitoring, and effectively improving the accuracy of voltage monitoring by configuring the number M of target edges corresponding to the reference positions.

An electronic system, comprising a critical logic circuit, various scan chains, and a control circuit, is provided. The critical logic circuit includes a critical path. One or more scan chains of the electronic system are coupled to the critical logic circuit and are associated with sensitization of the critical path. The control circuit may receive one or more configuration datasets, where each configuration dataset includes a scan chain identifier and a test pattern. For each received configuration dataset, the control circuit may identify a scan chain, of the one or more scan chains, that is associated with the scan chain identifier, and load the identified scan chain with the test pattern. Some scan flip-flops of the loaded one or more scan chains are utilized to sensitize the critical path.