42 results about "FLOPS" patented technology

This application relates to a power estimation system. A method for power estimation for integrated circuit design includes loading a test vector into a first sequence of flip-flops in scan mode, evaluating the test vector in scan mode and saving the results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vector is received from an automatic test pattern generator.

The invention discloses a discrete dung beetle optimized adaptive scanning VMama image denoising method, and relates to the field of image processing. In order to solve the problems of computation redundancy and denoising detail loss caused by a fixed scanning path of an existing VMama network, a hybrid coding space containing the number of network layers, state dimensions and binary scanning masks is constructed. According to the method, an S-type transfer function is introduced to improve a discrete dung beetle algorithm, an optimal architecture is adaptively searched by using behaviors such as rolling and dancing of a dung beetle population, a scanning path of an SS2D module is dynamically pruned according to a binary mask, performance is evaluated by fusing a fitness function of PSNR and FLOPs, and finally, a de-noised image is output based on the optimal architecture. According to the method, the balance between the denoising quality and the reasoning speed is effectively realized, and the model calculation amount is reduced.

The invention relates to a single-particle selective reinforcement method based on machine learning. The method comprises the steps of reading basic information and structural information of a trigger in a target circuit; part of triggers are randomly extracted for fault injection, and the soft error rate and the function masking rate of the triggers are counted to obtain a gold model; respectively training weight factors of different features for the soft error rate and the function masking rate through a golden model; clustering all triggers in the circuit by using a feature weighted K-Means classifier for the soft error rate and the function masking rate respectively; sensitive triggers in the circuit are determined and selectively reinforced by arranging the product of the soft error rate and the function masking rate. According to the method, the frequency of fault injection required by the circuit is reduced, so that the efficiency is improved, and the method can be used for selective design reinforcement for coping with single-particle soft errors in integrated circuit design.

A system and a method of pattern selection are provided for use by an electronic design automation (EDA) automatic test pattern generator (ATPG) for improved intermediate resistance (IR) drop analysis. The method includes identifying, for each of a plurality of transitional delay fault (TDF) patterns, flip-flops (FFs) toggling during a capture window; identifying coordinates on a grid for each of the toggled FFs; generating a boundary around the toggled FFs; generating tiles within the boundary; determining a number of toggled FFs included within each of the tiles; and ranking the plurality of TDF patterns based on the number of toggled FFs included within each of the tiles of each of the plurality of TDF patterns.

A synchronizer with flip-flops has a reduced number of flip-flops coupled in series, receiving as an input data of a first clock domain and supplying as an output data in the second clock domain. The second clock signal is at a variable frequency adjusted to a target frequency, by a division factor. The flip-flops are timed by a clock signal subsampling the second clock signal by a factor k1. The subsampled clock signal is generated by a frequency divider propagating a pulse of the signal every k1 clock pulses, while keeping the edges aligned.

The invention discloses a circuit aging overcoming method based on a post-silicon regulation technology, and relates to the field of digital integrated circuit reliability design, and the circuit aging overcoming method comprises the steps: determining a slow path in a plurality of data paths in a monitored circuit, the target trigger in each low-speed path is connected with an establishment time violation early-warning unit, and the establishment time violation early-warning unit generates an establishment time early-warning signal when monitoring that the connected trigger is about to generate an establishment time violation; the target triggers of the multiple low-speed paths are divided into multiple trigger groups, each trigger group corresponds to one clock adjusting unit, and the target trigger of each low-speed path in each trigger group is connected with the corresponding clock adjusting unit; and the clock adjusting unit configures the clock edge delay arrival time of the connected trigger based on the establishment time early warning signal so as to realize the effect of overcoming circuit aging. The method can effectively overcome circuit aging and improve circuit reliability.

An example operation may include one or more of receiving a logical model of a circuit written in a hardware description language (HDL), the logical model of the circuit comprising normalized and ratioed clocks, and simulation-efficient edge-triggered latches or flip-flops, translating the logical model of the circuit into a physical model of the circuit in the HDL via a software application, wherein the translating comprises replacing the normalized and ratioed clocks in the logical model of the circuit with a base system clock, divider logic generating hold waveforms to achieve ratioed behavior, and pulse-enabled latches, and replacing the edge-triggered latches or flip-flops with pulse-generation logic and pulse-enabled latches, executing a formal verification which determines whether the logical model of the circuit is functionally equivalent to the physical model of the circuit, and displaying results of the formal verification via a graphical user interface (GUI) of the software application.

The application discloses a temperature measuring method based on Gaussian noise in the technical field of temperature measurement, and comprises the following steps: mixing a voltage signal output by a thermistor in a circuit with a Gaussian noise signal to obtain a mixed signal, amplifying the mixed signal through an amplifier, and dividing the mixed signal into two paths to obtain a first signal and a second signal which are completely same; the first signal is compared with a first threshold voltage through a first comparator, and the second signal is compared with a second threshold voltage through a second comparator; signals output by the comparators are sent to a digital circuit for sampling through flip-flops or latches, and then temperature values are obtained by calculation or table lookup in the digital circuit. The method superimposes Gaussian noise on the output signal of the thermistor, and then carries out code value probability statistics on the single-bit sampled data, so that the temperature measurement is realized, high-precision ADC is not needed, and the precision of temperature measurement can be improved by controlling the sampling frequency and sampling time.

This application provides a synthesis method, storage medium, and program product for H-type clock trees, relating to the field of chip design. The method classifies each clock unit in the clock structure according to the number of flip-flops it covers; determines the number of H-type clock trees and their generation order based on different types of clock units and clock source types; uses a weighted clustering algorithm to determine the starting point and mounting point position of each H-type clock tree according to the number of H-type clock trees and their generation order; and constructs the corresponding H-type clock tree according to the starting point and mounting point position of each H-type clock tree. The H-type clock tree structure design of this application can effectively reduce unnecessary clock buffers and wiring capacitors, controlling power consumption at its source. It is applicable to clock structures with multiple clock sources and complex clock logic, and is suitable for large-scale high-performance integrated circuit design, providing a more efficient and reliable clock design solution for related design work.

The present disclosure relates to a data dump circuit, a sensing and latching circuit, and a debug circuit. A data dump circuit is coupled to a combinational logic circuit and includes a sensing and latching circuit and a scan chain circuit. The sensing and latching circuit senses a characteristic value of the combinational logic circuit and generates a scan enable signal upon determining that the characteristic value changes. The scan chain circuit is coupled to a plurality of flip-flops and operates in a scan mode in response to the scan enable signal. In the scan mode, the scan chain circuit sequentially outputs values stored in the flip-flops as dump data.

This application provides a command processing circuit and a data processing circuit, including: multiple flip-flops, the output of one flip-flop being connected to the input of the next flip-flop, used to sample internal write commands input to the command processing circuit according to the switching of a data strobe signal to obtain a sampling command for data sampling processing. The output of a target flip-flop is connected to the target terminal of the first flip-flop. The target flip-flop is a flip-flop whose output effective level overlaps with the target time, where the target time is the start and end time of the internal write command pulse. The target flip-flop is used to reset the internal write command in the first flip-flop by outputting an effective level. This application uses the target flip-flop to reset the start and / or end position of the internal write command in the first flip-flop, which can avoid repeated sampling of the internal write command due to rising edge or falling edge variations, thus improving the accuracy of data writing.

This invention discloses a post-mapping optimization method for RSFQ circuits based on path balancing, comprising: parsing the topological connection relationships of nodes in the netlist and presetting the number of iterations; constructing candidate supergates and calculating P-class truth tables, classifying and storing them after P-class transformations, with each P-class truth table storing only the candidate supergate with the fewest JJs, forming a supergate library; perturbing the node hierarchy of the netlist, randomly assigning logic levels, and inserting DFFs; traversing the netlist in reverse to extract fan-out free cones, calculating Boolean function truth tables and performing P-class transformations, matching equivalent structures, and if the number of JJs in the library is smaller, performing an inverse P-class transformation and replacing them in the netlist; performing retiming optimization on the netlist, deleting D flip-flops and continuing iterations or outputting the final netlist. This method has significant advantages in reducing the number of JJs, reducing DFF overhead, and improving the optimization space and efficiency of the mapped RSFQ circuit netlist.

An FPGA is disclosed, which includes a first delay line section to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input, a code conversion section that converts the order of the elements of a thermometer code output by the first delay line section and outputs it, and a calculation section that uses the converted code output by the code conversion section to determine the occurrence time difference, wherein the converted code is obtained by arranging the order of the elements of the thermometer code according to a predetermined standard, and the predetermined standard is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the first delay line section.

This invention discloses a progressive domain fine-tuning and knowledge fusion method for a large language model in tunnel boring machine (TBM) engineering. The method includes: constructing a hierarchical TBM training curriculum encompassing broad-domain academic theories and proprietary enterprise construction methods; training multiple parameter-efficient adapters with physical isolation based on a frozen base in parallel; performing singular value decomposition on the adapters to extract geometric feature subspaces representing knowledge distribution and calculating conflict correlations; and constructing a resource-aware unified adaptation mechanism based on this. This mechanism can generate conflict-free static fusion models or dynamically activate specific rank slices of the adapters through a routing network based on real-time hardware resource budgets (GPU memory / FLOPs) and geometry-resource signatures. This invention achieves adaptive dynamic scheduling of edge hardware resources for model inference while preserving multi-source knowledge.

Redundancy bits can be used to more effectively manage address translation cache (ATC) in data storage devices. The data storage device maintains a table of redundancy bits. When a request for an address translation arrives, the redundancy bits are calculated and compared to redundancy bits in the table. If there is a match, then the relevant ATC entry is retrieved and compared to the untranslated addresses. The same process is repeated for each redundancy bits match until finding a match in the ATC. In so doing, the translated address can be requested much earlier than normal by requesting the translated address upon the redundancy bits not matching. The earlier retrieval reduces throughput of the memory device without reducing performance. Furthermore, the unique structure of the internal ATC allows most of the ATC to be located in SRAM / DRAM while simply the redundancy bits are stored in flops.

The invention relates to a data transmission circuit, a chip, a data transmission method, a medium and a program product. The data transmission circuit comprises a first-stage trigger used for outputting data to a second-stage trigger module under the control of a clock signal output by a clock source; the second-stage trigger module comprises N + 1 second triggers, the updating cycle of output data of each second trigger is the clock cycle of N + 1 clock sources, and the triggered clock cycles of the second triggers are different; n + 1 is a natural number greater than or equal to 1; the third-stage trigger module comprises a data selector and a third trigger which are connected, and the data selector is used for selecting one path of data from the multiple paths of data output by the second-stage trigger module in each clock period of the clock source and outputting the selected path of data to the third trigger; and the third trigger is used for outputting data output by the data selector. According to the data transmission circuit, the path length is reduced, so that the path delay is reduced.

A test apparatus, a method for operating the test apparatus, and an integrated circuit are provided for testing combinational logic circuits configured to communicate electrically with analog circuits. The test apparatus includes: a plurality of flip-flops, each connected to the combinational logic circuit; and one or more processors connected to the flip-flops and configured to test the combinational logic circuit based on a scan signal. The one or more processors are configured to: input an input pattern to the combinational logic circuit via the plurality of flip-flops; obtain a first output value output from a first output node of the combinational logic circuit; determine whether a short-circuit current occurs in the analog circuit by inputting the first output value; and, based on the determination that no short-circuit current has occurred, connect a first unit circuit corresponding to the first output value between the first output node and the analog circuit.

This invention belongs to the field of integrated circuit technology and relates to a method for fabricating a radiation-hardened fault-tolerant trigger. The method includes constructing a radiation-hardened fault-tolerant trigger using three conventional D flip-flops, an XOR gate, a 2-to-1 selector, and two delay circuits. Input data is simultaneously written to both the primary and backup D flip-flops. After a specified delay, the input data is written to the third D flip-flop and compared with the data stored in the primary D flip-flop. If they match, the data stored in the primary D flip-flop is correct, and the 2-to-1 selector chooses the data stored in the primary D flip-flop as the output data. If they differ, the data stored in the primary D flip-flop is incorrect, and the 2-to-1 selector chooses the data stored in the backup D flip-flop as the output data. With this invention, regardless of which D flip-flop malfunctions due to radiation, the radiation-hardened fault-tolerant trigger can still output the correct value.

Aspects of the subject disclosure address the traditional trade-off between performance and area, in relation to circuit and system design, together with power as an additional factor of consideration. Circuits and systems of this disclosure may realize a datapath of data in respect of memory state elements (e.g., registers, flops, etc.) that is dependent on multiple qualifiers. Aspects of this disclosure enhance (e.g., optimize) area and reduce leakage power associated with circuits and systems. Furthermore, aspects of this disclosure enable and enhance an insertion of clock-gating circuits or mechanisms to reduce dynamic-power consumption depending on states of the qualifiers.

This provides a scan test circuit that can reduce the time and cost associated with testing. [Solution] The scan test circuit of the present disclosure comprises a logic circuit and an analog circuit, the logic circuit having a selection circuit and a logic circuit block, each logic circuit block having first to fourth flip-flops (FFs) and first and second combinational circuits, the selection circuit is connected to the first and third FFs, the first and second FFs are connected, the third and fourth FFs are connected, the second FF is connected to the first combinational circuit, the first combinational circuit and the third combinational circuit are connected, the fourth FF is connected to the second combinational circuit, the second combinational circuit and the fourth combinational circuit are connected, the third combinational circuit is connected to the fourth FF, and the fourth combinational circuit is connected to the third FF.

A method and an apparatus for processing image data based on a Mama model are provided. The method comprises the following steps: receiving a data sequence corresponding to image data; processing the data sequence by using a Mamba model to obtain a data sequence processing result; and outputting a classification result corresponding to the image data based on the data sequence processing result. The Mama model comprises a Mama trunk block for processing a data sequence based on a selective state space model; and the plurality of calculation blocks are positioned behind the Mamba main block. Each of the plurality of calculation blocks includes: a global scoring unit performing a global evaluation to obtain an importance score; a context holding unit that generates relative position information of the token; and a slow-fast scanning unit performing a first selective state space update and a second selective state space update. Therefore, the Mama model can significantly reduce the number of floating point operations per second in the reasoning stage on the premise of not sacrificing the precision basically.

A data dumping circuit is coupled to a combinational logic circuit, and includes a sensing and locking circuit and a scan chain circuit. The sensing and locking circuit is arranged to sense a characteristic value of the combinational logic circuit, and generate a scan enabling signal in response to the characteristic value being determined to be changed. The scan chain circuit is coupled to multiple flip-flops, and operates in a scan mode in response to the scan enabling signal, wherein in the scan mode, the scan chain circuit sequentially outputs a value stored in each of the multiple flip-flops for acting as dumping data.

The invention provides a multi-modal large model adaptive reasoning and pruning method based on evidence consistency, which is used for image-text questions and answers, reducing FLOPs and video memories and finely controlling calculation budget under the condition of not changing backbone parameters. The method comprises the following steps: firstly, extracting image and problem features by using a multi-modal basic model, and generating a structure sensing Top-k mask through QCEG-SA; evidence perturbation is carried out under the three views, evidence gain, consistency and unified uncertainty characteristics are obtained, and lightweight alignment is carried out with UAEL-mm; and in combination with short chain self-consistency (SCSC) and lightweight verification (CAV), off-line evaluation is performed on different pruning rates and reasoning actions, and an AARC adaptive resource scheduler is trained. In the online reasoning process, the AARC automatically selects the pruning rate, the SCSC chain number and the CAV configuration for each sample, structural perception pruning and multi-modal reasoning are executed, and efficient deployment of resource limited scenes such as a single-card GPU is achieved while the precision is basically not reduced or even slightly increased.

A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path failure signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.

The embodiments of the present disclosure provide a random number generation circuit, including: a random number generator, including a feedback module and a plurality of sequentially connected flip-flops, where an output terminal of a previous flip-flop being connected to an input terminal of a next flip-flop, the output terminal of each of the flip-flops serving as an output terminal of the random number generator, and an output terminal of the feedback module being connected to the input terminal of one of the flip-flops; the feedback module being configured to receive selection signals and select, on the basis of the selection signals, the output terminals of two of the flip-flops as input terminals of the feedback module; and the random number generator being configured to output a plurality of first random numbers corresponding to corresponding selection signals in each counting cycle.

A memory apparatus includes a domain crossing circuit including a plurality of first flip-flops operating based on the internal clock and a plurality of second flip-flops operating based on a data clock, the plurality of first flip-flops being initialized by the system domain reset signal, the plurality of second flip-flops being initialized by the data domain reset signal.

A system (300) includes a memory (206) configured to store test patterns. A first lockstep core (102) and a second lockstep core (104) are configured to receive a same set of test patterns. During a reset of the first lockstep core and the second lockstep core, a first scan output is generated from the first lockstep core (102) and a second scan output is generated from the second lockstep core (104). A comparator (306) can be coupled to the first lockstep core and the second lockstep core and configured to compare the first scan output and the second scan output. If the first and second scan outputs are the same, the first and second lockstep cores (102, 104) can be initialized to a similar state. The first and second lockstep cores can comprise non-resettable flip-flops.

The invention provides an anti-machine learning attack circuit for a PUF (Physical Unclonable Function), and belongs to the field of PUFs, the anti-machine learning attack circuit comprises two SAC-PUF circuits, each SAC-PUF circuit comprises an arbiter D1 and n path exchange switches, n control ends of the n path exchange switches are respectively connected to values of n triggers, output ends of the jth and kth path exchange switches are respectively connected to arbiters D3 and D2, output ends of D1, D2 and D3 are connected to a confusion circuit, and the output ends of D1, D2 and D3 are respectively connected to the output ends of n triggers. The output end of the mixing circuit in the first SAC-PUF circuit is connected to the first control end of the tap unit and the first input end of the post-processing circuit, and the output end of the mixing circuit in the second SAC-PUF circuit is connected to the second control end of the tap unit and the second input end of the post-processing circuit. The output end of the post-processing circuit is connected to the second input end of each tap unit, and the first input end of each tap unit is connected to the value of the nth trigger; and the machine learning attack resistance is improved.

An SPUF based on combinational logic and scan chain comprises an external stimulus source, a combinational logic circuit module, a scan chain circuit module, a data processing module and n switch circuits SW0, SW1, . . . , SWn−1, n=2m, and m is an integer greater than or equal to 1; combinational logic circuit module comprises n switch circuits S0, S1, . . . , Sn−1 and a combinational logic circuit; the scan chain circuit module comprises n scan flip-flops (SFFs) SFF0, SFF1, . . . , SFFn−1; each of the n switch circuits SW0, SW1, . . . , SWn−1 and the n switch circuits S0, S1, . . . , Sn−1 is implemented by a 2-to-1 multiplexer. The SPUF based on combinational logic and scan chain has high uniqueness and randomness, requires a few clock frequency changes, and has high reliability, more bits of responses and high security.