72 results about "FLOPS" patented technology

The invention discloses a large language model progressive field fine tuning and knowledge fusion method for shield engineering. The method comprises the following steps: constructing a layered shield training course containing a wide-area academic theory and a proprietary enterprise construction method; parallelly training a plurality of physically isolated parameter efficient adapters based on the frozen base; performing singular value decomposition on the adapter, extracting a geometric feature subspace representing knowledge distribution, and calculating a conflict correlation degree; based on this, a uniform adaptation mechanism of resource awareness is constructed. The mechanism not only can generate a static fusion model for conflict removal, but also can dynamically activate a specific rank slice of an adapter through a routing network based on real-time hardware resource budget (video memory / FLOPs) and geometry-resource signature. According to the method, multi-source knowledge is reserved, and adaptive dynamic scheduling of edge hardware resources by model reasoning is realized.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The invention provides a video target segmentation method and system based on instance-level enhancement, and belongs to the field of computer visual perception of artificial intelligence. On the basis of an existing SAM2 baseline model, an instance-level query and interaction module and a memory encoder are added, so that the algorithm can form overall cognition on a target from top to bottom. Compared with a traditional pixel-level identification method, the method can remarkably improve the target tracking and segmentation accuracy in a complex scene. The method has excellent generalization ability, and can maintain excellent zero sample learning performance even in extreme scenes such as shadow tracking and target disappearance reproduction. According to the method, a lightweight instance-level module is adopted, the calculation overhead is effectively reduced, the overall FLOPs is only increased by 3.5% compared with a baseline model SAM2, the theoretical reasoning time is infinitely long, and the design ensures that high performance is kept while excessive calculation burden is avoided.

A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path_failure_signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The application provides a scan test method, comprising: constructing a single stuck-at fault scan forest, the scan forest comprising a plurality of scan inputs and a plurality of scan trees, each scan input being driven by an ATE; each pin of the ATE driving a plurality of demodulators, each demodulator driving a plurality of scan trees, each scan tree corresponding to each demodulator being controlled by different clock signals of a gate logic, each scan tree comprising a plurality of scan chains, and each scan chain comprising a plurality of scan flip-flops; and based on the constructed single stuck-at fault scan forest, placing a test. The method can effectively reduce the calculation time and memory overhead.

This application relates to a power estimation system. A method for power estimation for integrated circuit design includes loading a test vector into a first sequence of flip-flops in scan mode, evaluating the test vector in scan mode and saving the results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vector is received from an automatic test pattern generator.

The present invention relates to a radiation-resistant D-type flip-flop based on interconnect crosstalk calculation. The flip-flop comprises a cascaded structure of a master latch module and a slave latch module. The master latch module converts input signals into dual-node redundant signals via a first interconnect crosstalk circuit (CC1), utilizing L1-L3 and L2-L3 capacitive coupling to implement logical storage where only two high-level inputs trigger high-level outputs. The slave latch module generates redundant signals L4 / L5 via a second interconnect crosstalk circuit and uses a Muller C unit to perform error correction on CC2 outputs and direct transmission signals. The D-type flip-flop requires only 16 minimum-size transistors, a 67% reduction compared to conventional TMR flip-flops. It supports asynchronous reset, forcing L3 / L6 to charge to a high level during reset. The capacitive coupling strength is controlled through metal layer routing, significantly improving the reliability of aerospace electronic systems in radiation environments.

The invention discloses a discrete dung beetle optimized adaptive scanning VMama image denoising method, and relates to the field of image processing. In order to solve the problems of computation redundancy and denoising detail loss caused by a fixed scanning path of an existing VMama network, a hybrid coding space containing the number of network layers, state dimensions and binary scanning masks is constructed. According to the method, an S-type transfer function is introduced to improve a discrete dung beetle algorithm, an optimal architecture is adaptively searched by using behaviors such as rolling and dancing of a dung beetle population, a scanning path of an SS2D module is dynamically pruned according to a binary mask, performance is evaluated by fusing a fitness function of PSNR and FLOPs, and finally, a de-noised image is output based on the optimal architecture. According to the method, the balance between the denoising quality and the reasoning speed is effectively realized, and the model calculation amount is reduced.

The invention relates to a single-particle selective reinforcement method based on machine learning. The method comprises the steps of reading basic information and structural information of a trigger in a target circuit; part of triggers are randomly extracted for fault injection, and the soft error rate and the function masking rate of the triggers are counted to obtain a gold model; respectively training weight factors of different features for the soft error rate and the function masking rate through a golden model; clustering all triggers in the circuit by using a feature weighted K-Means classifier for the soft error rate and the function masking rate respectively; sensitive triggers in the circuit are determined and selectively reinforced by arranging the product of the soft error rate and the function masking rate. According to the method, the frequency of fault injection required by the circuit is reduced, so that the efficiency is improved, and the method can be used for selective design reinforcement for coping with single-particle soft errors in integrated circuit design.

A system and a method of pattern selection are provided for use by an electronic design automation (EDA) automatic test pattern generator (ATPG) for improved intermediate resistance (IR) drop analysis. The method includes identifying, for each of a plurality of transitional delay fault (TDF) patterns, flip-flops (FFs) toggling during a capture window; identifying coordinates on a grid for each of the toggled FFs; generating a boundary around the toggled FFs; generating tiles within the boundary; determining a number of toggled FFs included within each of the tiles; and ranking the plurality of TDF patterns based on the number of toggled FFs included within each of the tiles of each of the plurality of TDF patterns.

The invention specifically discloses a clock tree synthesis method based on clustering and reinforcement learning collaborative optimization, and relates to the technical field of integrated circuit design and electronic design automation. The method comprises the following steps: firstly reading a trigger coordinate, a clock source position and a design constraint parameter in a circuit; secondly, performing clustering grouping on triggers in the circuit through a clustering method, generating an initial hierarchical clock tree topology and determining candidate insertion positions of buffers; constructing a reinforcement learning environment, and defining a state space, an action space and a multi-target reward function; then, respectively learning a trigger relocation strategy and a buffer insertion and removal strategy by maintaining an independent movement Q table and action Q table within the displacement constraint; and finally, evaluating clock skew, delay and other performances, generating a comprehensive performance evaluation result, and performing iterative optimization judgment through a closed-loop feedback mechanism. According to the method, the clock skew and delay are effectively controlled, the local optimum problem of a traditional method is avoided, and the comprehensive quality and the automation efficiency of the clock tree are improved.

A synchronizer with flip-flops has a reduced number of flip-flops coupled in series, receiving as an input data of a first clock domain and supplying as an output data in the second clock domain. The second clock signal is at a variable frequency adjusted to a target frequency, by a division factor. The flip-flops are timed by a clock signal subsampling the second clock signal by a factor k1. The subsampled clock signal is generated by a frequency divider propagating a pulse of the signal every k1 clock pulses, while keeping the edges aligned.

The invention discloses a circuit aging overcoming method based on a post-silicon regulation technology, and relates to the field of digital integrated circuit reliability design, and the circuit aging overcoming method comprises the steps: determining a slow path in a plurality of data paths in a monitored circuit, the target trigger in each low-speed path is connected with an establishment time violation early-warning unit, and the establishment time violation early-warning unit generates an establishment time early-warning signal when monitoring that the connected trigger is about to generate an establishment time violation; the target triggers of the multiple low-speed paths are divided into multiple trigger groups, each trigger group corresponds to one clock adjusting unit, and the target trigger of each low-speed path in each trigger group is connected with the corresponding clock adjusting unit; and the clock adjusting unit configures the clock edge delay arrival time of the connected trigger based on the establishment time early warning signal so as to realize the effect of overcoming circuit aging. The method can effectively overcome circuit aging and improve circuit reliability.

An example operation may include one or more of receiving a logical model of a circuit written in a hardware description language (HDL), the logical model of the circuit comprising normalized and ratioed clocks, and simulation-efficient edge-triggered latches or flip-flops, translating the logical model of the circuit into a physical model of the circuit in the HDL via a software application, wherein the translating comprises replacing the normalized and ratioed clocks in the logical model of the circuit with a base system clock, divider logic generating hold waveforms to achieve ratioed behavior, and pulse-enabled latches, and replacing the edge-triggered latches or flip-flops with pulse-generation logic and pulse-enabled latches, executing a formal verification which determines whether the logical model of the circuit is functionally equivalent to the physical model of the circuit, and displaying results of the formal verification via a graphical user interface (GUI) of the software application.

A system includes a memory that stores instructions and a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a circuit layout module that generates an initial circuit layout in response to a circuit netlist. The circuit netlist includes functional logic, the test-point nodes interconnecting portions of the functional logic, and a plurality of test-point flops associated with scan-chains. The EDA application also includes a test-point flop allocation module that divides the test-point nodes into test-point sharing groups based on a physical location of the test-point nodes and based on a test-point allocation parameter. The module relocates each of the test-point flops proximal to a test-point sharing group to generate an adjusted circuit layout associated with the circuit design. The adjusted circuit layout is employable to fabricate an integrated circuit (IC) chip.

The application discloses a temperature measuring method based on Gaussian noise in the technical field of temperature measurement, and comprises the following steps: mixing a voltage signal output by a thermistor in a circuit with a Gaussian noise signal to obtain a mixed signal, amplifying the mixed signal through an amplifier, and dividing the mixed signal into two paths to obtain a first signal and a second signal which are completely same; the first signal is compared with a first threshold voltage through a first comparator, and the second signal is compared with a second threshold voltage through a second comparator; signals output by the comparators are sent to a digital circuit for sampling through flip-flops or latches, and then temperature values are obtained by calculation or table lookup in the digital circuit. The method superimposes Gaussian noise on the output signal of the thermistor, and then carries out code value probability statistics on the single-bit sampled data, so that the temperature measurement is realized, high-precision ADC is not needed, and the precision of temperature measurement can be improved by controlling the sampling frequency and sampling time.

The invention discloses a generation method, device and system suitable for a hybrid-driven multi-bit trigger. The generation method comprises the following steps: acquiring all single triggers in a digital chip of which the initial layout design is completed; mapping each single trigger into a ternary trigger vector comprising a transistor size, a threshold voltage and a number, and generating a trigger matrix; splitting the trigger matrix into a plurality of independent sub-matrixes according to the clustering result of the single trigger, wherein each sub-matrix corresponds to one multi-bit trigger; repeating the following steps until the Pareto front is stable and meets a preset layout legalization verification condition to obtain a multi-bit trigger: by taking the normalized total negative margin and power consumption minimization as optimization objectives, optimizing each sub-matrix by adopting a proxy auxiliary differential evolution algorithm and a non-dominated sorting evolution algorithm to obtain a Pareto optimal solution set; and if the multi-bit trigger corresponding to the Pareto optimal solution set does not meet the layout legalization verification condition, re-dividing the trigger matrix. The clock network power consumption can be reduced, and the time sequence convergence rate is improved.

An electronic system, comprising a critical logic circuit, various scan chains, and a control circuit, is provided. The critical logic circuit includes a critical path. One or more scan chains of the electronic system are coupled to the critical logic circuit and are associated with sensitization of the critical path. The control circuit may receive one or more configuration datasets, where each configuration dataset includes a scan chain identifier and a test pattern. For each received configuration dataset, the control circuit may identify a scan chain, of the one or more scan chains, that is associated with the scan chain identifier, and load the identified scan chain with the test pattern. Some scan flip-flops of the loaded one or more scan chains are utilized to sensitize the critical path.

The invention discloses a bit stream random number generator, a random multiplication circuit and a calculation method, and belongs to the technical field of integrated circuits. A reverse signal end of a highest-bit D trigger Ln of a linear feedback shift register is respectively connected with a NOR gate and a NAND gate, and output signal ends of n-1 low-bit triggers in the linear feedback shift register are respectively connected with a comparator; a sign bit xn of an n-bit binary number corresponding to the target numerical value is input into the NOR gate and the NAND gate respectively; bits corresponding to the amplitude bits of the n-bit binary number are input to the comparator; the comparator and the NOR gate are connected with the OR gate; the OR gate and the NAND gate are connected with the AND gate. In the application, the two bit stream random number generators can generate two bit streams with low correlation, so that the numerical value shown by the bit stream obtained by carrying out multiplication (namely XNOR operation) on the two bit streams is closer to the product result of two target numerical values.

This application provides a synthesis method, storage medium, and program product for H-type clock trees, relating to the field of chip design. The method classifies each clock unit in the clock structure according to the number of flip-flops it covers; determines the number of H-type clock trees and their generation order based on different types of clock units and clock source types; uses a weighted clustering algorithm to determine the starting point and mounting point position of each H-type clock tree according to the number of H-type clock trees and their generation order; and constructs the corresponding H-type clock tree according to the starting point and mounting point position of each H-type clock tree. The H-type clock tree structure design of this application can effectively reduce unnecessary clock buffers and wiring capacitors, controlling power consumption at its source. It is applicable to clock structures with multiple clock sources and complex clock logic, and is suitable for large-scale high-performance integrated circuit design, providing a more efficient and reliable clock design solution for related design work.

The present disclosure relates to a data dump circuit, a sensing and latching circuit, and a debug circuit. A data dump circuit is coupled to a combinational logic circuit and includes a sensing and latching circuit and a scan chain circuit. The sensing and latching circuit senses a characteristic value of the combinational logic circuit and generates a scan enable signal upon determining that the characteristic value changes. The scan chain circuit is coupled to a plurality of flip-flops and operates in a scan mode in response to the scan enable signal. In the scan mode, the scan chain circuit sequentially outputs values stored in the flip-flops as dump data.

A set of payload flip-flops receives an input instance of a payload, and outputs an output instance from which a first instance of an error check signal is generated. One or more error check flip-flops receive the first instance and output a second instance. The input payload instance is clocked into the payload flip-flops if a payload enable signal is asserted, and the first error-check signal instance is clocked into the error check flip-flops if an error check enable signal is asserted. The input payload instance is input to the set of payload flip-flops over two clock cycles, and the payload enable signal is asserted for the two clock cycles. The error check enable signal is asserted on the second cycle. The first instance of the error check signal is compared with the second instance and an error signal is asserted if they do not match.

This application provides a command processing circuit and a data processing circuit, including: multiple flip-flops, the output of one flip-flop being connected to the input of the next flip-flop, used to sample internal write commands input to the command processing circuit according to the switching of a data strobe signal to obtain a sampling command for data sampling processing. The output of a target flip-flop is connected to the target terminal of the first flip-flop. The target flip-flop is a flip-flop whose output effective level overlaps with the target time, where the target time is the start and end time of the internal write command pulse. The target flip-flop is used to reset the internal write command in the first flip-flop by outputting an effective level. This application uses the target flip-flop to reset the start and / or end position of the internal write command in the first flip-flop, which can avoid repeated sampling of the internal write command due to rising edge or falling edge variations, thus improving the accuracy of data writing.

A scan reset control circuit includes a single scan reset input configured to receive a reset signal, a plurality of scan reset outputs configured to be coupled to a plurality of circuit blocks in a one-to-one ratio, a plurality of writable non-scan test data registers including register outputs configured to assert or deassert the reset signal, and a plurality of reset enable circuits coupled to the plurality of scan reset outputs in a one-to-one ratio. Each of the scan reset outputs is configured to simultaneously reset a set of scan flip-flops of the corresponding circuit block. Each of the plurality of reset enable circuits includes an input coupled to the single scan reset input, a selector input coupled to the register outputs, and an output coupled to the corresponding scan reset output.

Systems or methods described herein may relate to latch-independent clock gating techniques to enable or disable an internal clock of an integrated circuit device. A programmable logic device includes a clock gating circuit that receives a clock signal and is latch independent. The clock gating circuit includes gating signal circuitry that generates a gating signal based on the clock signal and an enable signal. The clock gating circuit also includes a logic gate that generates a control signal based on the gating signal. The clock gating circuit also includes gated clock generation circuitry that generates a gated clock signal based on the clock signal and the control signal.

According to various embodiments, a circuit is described including a plurality of scan flip-flops including a sequence of input wrapper scan flip-flops and including, for each input wrapper scan flip-flop of at least a subset of the input wrapper scan flip-flops, at the input wrapper scan flip-flop's test input a respective test input circuit configured to, when supplied with a mode control signal having a first value, connect the test input to the output of the preceding input wrapper scan flip-flop such that the test input of the flip-flop is supplied with the content of the preceding input wrapper scan flip-flop and when supplied with the mode control signal having a second value, connect the test input to an output of a part of the circuit such that the test input of the flip-flop is supplied with a value depending on a test result.

This invention discloses a post-mapping optimization method for RSFQ circuits based on path balancing, comprising: parsing the topological connection relationships of nodes in the netlist and presetting the number of iterations; constructing candidate supergates and calculating P-class truth tables, classifying and storing them after P-class transformations, with each P-class truth table storing only the candidate supergate with the fewest JJs, forming a supergate library; perturbing the node hierarchy of the netlist, randomly assigning logic levels, and inserting DFFs; traversing the netlist in reverse to extract fan-out free cones, calculating Boolean function truth tables and performing P-class transformations, matching equivalent structures, and if the number of JJs in the library is smaller, performing an inverse P-class transformation and replacing them in the netlist; performing retiming optimization on the netlist, deleting D flip-flops and continuing iterations or outputting the final netlist. This method has significant advantages in reducing the number of JJs, reducing DFF overhead, and improving the optimization space and efficiency of the mapped RSFQ circuit netlist.

An FPGA is disclosed, which includes a first delay line section to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input, a code conversion section that converts the order of the elements of a thermometer code output by the first delay line section and outputs it, and a calculation section that uses the converted code output by the code conversion section to determine the occurrence time difference, wherein the converted code is obtained by arranging the order of the elements of the thermometer code according to a predetermined standard, and the predetermined standard is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the first delay line section.