128results about "Exclusive-OR circuits" patented technology

The application provides a method and device for generating a pseudo-random sequence, an electronic device and a computer readable storage medium. The method comprises: performing AND operation and XOR operation on M bit values of a first sequence to obtain an (A+m)th bit value of the first sequence; wherein M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0; and determining an mth bit value of the pseudo-random sequence according to the (A+m)th bit value of the first sequence.

The invention relates to the technical field of memristors, and provides a chitosan-based memristor which comprises a substrate, a buffer layer, a composite dielectric layer and a top electrode which are sequentially stacked from bottom to top, the buffer layer is formed by spin-coating a PEDOT: PSS aqueous solution on the substrate and then carrying out heat treatment; the composite dielectric layer is formed by spin-coating the buffer layer with an ultrasonic composite solution formed by a graphene oxide aqueous dispersion and a chitosan acetic acid solution and then carrying out heat treatment. By adopting a collaborative architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT: PSS buffer layer, the prepared bio-based memristor has the effects of relatively high switching ratio, relatively low operating voltage and good performance stability. Meanwhile, based on stable high and low resistance states of the device, all seven basic logic operations including a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate and an XNOR gate are completely realized on a single bio-based platform, the function accuracy can reach 100%, and an unexpected effect is achieved.

An integrated circuit (IC) containing a circuit to be operable using one of multiple unequal power supplies during normal operation of the IC. The IC contains a one time programmable (OTP) memory containing a first bit and a second bit, with each of the bit having an initial value and being programmable to a programmed value. A configuration engine contained in the IC operates the circuit with a first selection with respect to using one of the unequal power supplies during normal operation of the IC if both of the first bit and the second bit have an equal value comprising one of the initial value and the programmed value. The configuration engine operates the circuit with a second selection with respect to using one of the unequal power supplies during normal operation of the IC if the first bit and the second bit have unequal values.

A gate apparatus configured to perform an XOR operation on received input signals to provide a logical output signal, y. The apparatus includes at least one first signal input adapted to receive a first input signal; and at least one second signal input adapted to receive a second input signal. At least one of the received input signals is split into a first split signal portion fed to a photo diode to generate an electrical photocurrent supplied to a junction node, and a second split signal portion combined with at least a signal portion of the other signal received at the second signal input to generate a combined optical output signal supplied to an electro-optical modulator to provide the logical output signal, y. The electro-optical modulator is driven by a photocurrent processing unit having an input connected to the junction node.

This invention relates to the field of integrated circuit technology and discloses a clock gating circuit, a clock signal control method, a chip, and an electronic device. By adding a feedback circuit based on a first reverse voltage signal generation module and a first OR gate unit to a conventional clock gating circuit, when the second register group needs to operate, a second enable signal corresponding to the second gating unit is generated to control the second gating unit to open. Based on the second enable signal, the feedback circuit then controls the first gating unit to open, thereby controlling the second register group to enter the working state. Therefore, this invention only needs to generate a second enable signal to simultaneously control the opening of the first and second gating units, eliminating the need to generate separate first and second enable signals to control the opening of the first and second gating units. This avoids the process of determining which gating units need to be opened based on the second gating unit, effectively improving the working efficiency of the clock gating circuit.

Disclosed is a stateful logic-in-memory using silicon diodes. More particularly, the stateful logic-in-memory according to an embodiment of the present invention includes a plurality of silicon diodes, each of the silicon diodes includes an anode region, a first channel region, a second channel region and a cathode region and is included as a memory cell.

A circuit is provided having: a first input configured to receive first data; a second input coupled and configured to receive second data; a clock input configured to receive a clock signal during a first time period, the clock signal having a trigger edge during the first time period; and an output. The circuit is configured to output first data through the output before a first time period begins, and to output second data through the output and avoid outputting the first data in response to receiving a clock signal having a trigger edge during the first time period.

A circuit may comprise a first multiplexer, a second multiplexer, a combination of logic gates, a third multiplexer, a first low-pas filter, and a second low-pass filter. The first multiplexer can be configured to receive and select a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. Respective phases of the first to fourth clock signals are related to each other. The second multiplexer can be configured to receive and select the first to fourth clock signals. The combination of logic gates may comprise a first logic gate and a second logic gate. The combination of logic gates can be coupled to the second multiplexer and can be configured to receive the second plurality of the first to fourth clock signals. The third multiplexer can be configured to receive and select the first to fourth outputs.

An example circuit, method, and electronic device configured to filter pulses below a minimum threshold pulse width and provide delays that exhibit low variance to changes in temperature, voltage, and technology processes, are provided. The example circuit includes a first flip / flop, a second flip / flop, and a charge detector. The first flip / flop generates a first out signal and a first inverse signal based on an input signal and a first clocking signal. The second flip / flop generates an output signal and a second out signal based on the first out signal, the first inverse signal, and a second clocking signal, wherein the second clocking signal is an inverse of the first clocking signal. The charge detector circuit includes a charging capacitor to generate a charge signal based on a change in the input signal, such that pulses are filtered based on a capacitance value of the charging capacitor and a reference voltage.

The invention relates to the technical field of circuit design, and discloses a multi-intensity emotion enhancement memristor bionic circuit which comprises a language enhancement module, a fear emotion module, an happy emotion module, an emotion enhancement module and a high-intensity memory module. Parallel light / heavy processing paths are arranged in the fear and happiness emotion module, and emotion stimulation of different intensities is distinguished. The light emotion signals are processed and then fed back to the language enhancement module, and formation of conventional memory is adjusted; and the severe emotion signal is transmitted to an independent high-intensity memory module for special storage. The language enhancement module integrally processes language signals and feedback adjustment signals of all the modules. The high-intensity memory module forms stable memory for severe emotional events through a parallel memristor structure. Through grading processing and signal interaction, the differential influence of emotions with different intensities and the interaction of multiple emotions can be simulated, a grading memory mechanism is established, and the fidelity and authenticity of circuit simulation biological memory are improved.

The utility model discloses a dead zone insertion circuit based on a gate-level circuit, and belongs to the technical field of gate-level circuits. A first input end of a first NAND gate is connected with a first complementary signal; the input end of the first NOT gate is connected with the first input end of the first NAND gate; the first resistance-capacitance circuit is connected with the output end of the first NOT gate through a first resistor; the first input end of the second NAND gate is connected with a second complementary signal, and the second input end of the second NAND gate is connected with the first resistance-capacitance circuit through a second resistor; the input end of the second NOT gate is connected with the first input end of the second NAND gate; the second resistance-capacitance circuit is connected with the output end of the second NOT gate through a third resistor; the first end of the fourth resistor is connected with the second input end of the first NAND gate, and the second end of the fourth resistor is connected between the third resistor and the second resistance-capacitance circuit. The beneficial effects are that through cooperation of the NAND gate, the NOT gate and the resistance-capacitance circuit, the circuit structure is simple, the safety and reliability of circuit work are improved, and the cost is low.

Aspects of the disclosure are directed to a test mode save and restore operation. In accordance with one aspect, the disclosure includes a hold latch cell configured to execute a save directive for a first operational state of a digital logic system and to execute a restore directive for the first operational state in the digital logic system in an operational mode; a first multiplexer coupled to the hold latch cell, the first multiplexer configured to execute a test sequence on the digital logic system in a test mode; and a logical XOR circuit coupled to the hold latch cell, the logical XOR circuit configured to perform a fault detection on the save directive and the restore directive to generate an error flag signal.

The embodiment of the present disclosure provides a delay-locked loop and a memory, the delay-locked loop comprising: a preprocessing module configured to receive an initial clock signal, preprocess the initial clock signal, output a first clock signal and a second clock signal; a first adjustable delay line configured to receive the first clock signal, adjust and transmit the first clock signal, and output a first target clock signal; a second adjustable delay line configured to receive the second clock signal, adjust and transmit the second clock signal, and output a second synchronization clock signal; and a first adjustment module configured to adjust the phase of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal. In this way, the first adjustment module can correct the phase difference between the first synchronization clock signal and the second target clock signal, and improve the phase deviation between the target clock signals.

The invention discloses a zero-power-consumption power-on reset circuit which is characterized in that a power supply voltage division unit performs voltage division on input power supply voltage and then outputs a first signal to a voltage detection unit; the voltage detection unit outputs a high-level or low-level second signal to the inverting unit according to a comparison result of the first signal and a preset threshold value. The inverting unit performs shaping and inverting processing on the second signal, generates a third signal and transmits the third signal to the output shaping unit. And the output shaping unit is used for buffering and shaping the third signal and outputting a reset signal. The AND gate unit inputs a reset signal and a sixth signal output by the D trigger unit to generate a fourth signal. And the delay unit receives the fourth signal, delays the fourth signal, generates a fifth signal and inputs the fifth signal to the D trigger unit. And the D trigger unit respectively receives the reset signal and the fifth signal, generates a sixth signal, inputs the sixth signal to the power supply voltage dividing unit, and turns off the power supply voltage dividing unit, so that the whole reset circuit keeps a zero power consumption state.

Embodiments of this application provide a convolution circuit, a convolution computing method, a chip, and an electronic device, applied to the field of chip technologies, to resolve problems of high power consumption and a large wiring area of a convolution circuit in an existing convolver. The convolution circuit includes a plurality of multipliers, a first adder coupled to the plurality of multipliers, and a second adder coupled to the first adder. Each multiplier includes a plurality of precoders, a plurality of encoder groups, and an adder tree circuit. Each precoder is in a one-to-one correspondence with one encoder group. Output ends of the plurality of encoder groups and input lines of the adder tree circuit are of a same quantity and in a one-to-one correspondence. In addition, the adder tree circuit is coupled to the first adder. The second adder is further coupled to a memory. A partial product that is related only to a weight parameter may be first accumulated with a constant 1 in the multiplier, and then added to results output by adder tree circuits in the second adder, to reduce an area and power consumption of the adder tree circuit.

An apparatus, including: a clock gating circuit, CGC, including: a clock gating device (920) configured to selectively gate / pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit (930) configured to select a non- complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

The present disclosure relates to a circuit comprising: —a first timing guard circuit (200) configured to detect when a slack time of a first data signal arriving at a first synchronous device (202) falls below a first threshold (SLG DELAY); and —a second timing guard circuit (200) configured to detect when a slack time of a second data signal arriving at a second synchronous device (202) falls below a second threshold (SLG DELAY), the first and second thresholds being different from each other.

This invention provides a crystal oscillator and a method for suppressing phase noise of the same. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to the output of the crystal oscillator core circuit, a pulse wave buffer coupled to the output of the crystal oscillator core circuit, and a phase noise suppression circuit coupled to the output of the crystal oscillator core circuit. The crystal oscillator core circuit can generate a sine wave. The bias circuit can provide a bias voltage for the sine wave. The pulse wave buffer can generate a pulse wave according to the sine wave. The phase noise suppression circuit can generate a reset signal containing at least one reset pulse for resetting the bias voltage. Furthermore, a reset signal is generated without calibrating at least one reset pulse to the zero-crossing point of the sine wave.

This invention relates to a device for generating truly random numbers, comprising a digital chaotic oscillating autonomous Boolean network as an entropy source. According to the invention, the proposed digital chaotic oscillating autonomous Boolean network comprises three interconnected logic elements, two of which represent two-input XOR gates and / or XNOR gates, while the third logic element has three inputs and one output, and implements a logic "one-to-one counting" function, wherein if a logic 1 appears at no more than one input of the third logic element, the output of the third logic element is set to logic 1; otherwise, the output is set to logic 0. The resulting technical advantages include improved truly random number generation speed while reducing energy consumption.

A bus buffer circuit is provided which can prevent a state fixation in the bus buffer circuit to reduce power consumption and temporarily output a potential different from an actual bus signal at a state transition. The bus buffer circuit includes an input buffer circuit which operates with a first power supply to output a non-inverted input signal and an inverted input signal; a voltage conversion circuit which operates with a second power supply to output a voltage-converted non-inverted output signal and a voltage-converted inverted output signal; an output maintenance section which maintains the voltage-converted non-inverted output signal and the voltage-converted inverted output signal at the same potential level when an output enable signal is in an inhibit state; a determination section which determines whether the same potential level is present; a tri-state output buffer circuit which outputs the voltage-converted non-inverted output signal or the voltage-converted inverted output signal; and an output control section which sets the tri-state output buffer circuit to an output inhibit state when the same potential level is present based on a result of the determination section.

A semiconductor device includes a pulse input circuit including flip-flops constituting each of two front-stage counters having different holding states from each other and configured such that first pulses from an even-stage ring circuit are input to each of the two front-stage counters, an edge detection circuit configured to detect edges of outputs of the two front-stage counters and output a second pulse having a predetermined pulse width larger than a predetermined value based on the edge, and a counter circuit including a rear-stage counter to which the second pulse is input. The edge detection circuit is configured to output the second pulse or a stepwise signal when a pulse width of the first pulse is smaller than the predetermined value.

The application relates to a constant-power-consumption multifunctional logic circuit based on mask control and belongs to the field of circuit electronics. The application comprises a double-track logic circuit, a power consumption balancing module and a mask; the double-track logic circuit is used for controlling signal transmission and realizing corresponding logic functions; the output of the mask control signal, the randomness of the mask and the power consumption balancing module are used for increasing the power consumption attack resistance of the circuit. Two logic function circuit structures are integrated in a double-track circuit, the output of different logic functions is controlled by using the mask, the logic units involved realize constant power consumption on the basis of random jumping of the output signal, the randomness of the mask, the double-track structure and the power consumption balancing module are used for improving the power consumption attack resistance, the inherent properties of the mask are used for controlling the output of MOS tubes to realize output of two logic functions under the same double-track structure, the average power consumption and the circuit cost can be reduced on the basis of improving the power consumption attack resistance of the circuit.

This application relates to the field of IC chip testing, and provides a decompression circuit, a circuit generation method, and an IC chip, to test a component in the IC chip by outputting a large quantity of test signals through the decompression circuit. The decompression circuit (12) includes a plurality of sub-circuits (30). The sub-circuit (30) includes a plurality of cellular automaton CA circuits (301) and a phase shifter (302). The CA circuit (301) includes a first XOR circuit (XOR1) and a register (R). The first XOR circuit (XOR1) includes a first input end. A data input end of the register (R) is coupled to an output end of the first XOR circuit (XOR1). A data output end of the register (R) is coupled to the first input end of the first XOR circuit (XOR1) and an input end of the phase shifter (302). The data output end of the register (R) is further coupled to a second input end of a first XOR circuit (XOR1) in at least one other CA circuit (301). The phase shifter (302) is configured to output a test signal.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

The device includes a phase change material, a first electrode at a first end of the phase change material, a second electrode at a second end of the phase change material, and a heating element coupled to at least a portion of the phase change material between the first and second ends. The device also includes a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.

The technology is directed to a di / dt circuit for detecting and measuring the di / dt droops on silicon. The circuit may be calibrated to account for silicon process spread. When a di / dt droop has been detected by the circuit, the magnitude of the droop can be measured by the circuit, allowing the system to determine the best course of action. For instance, when the measured droop is within predetermined limits, the system can continue to operate. However, in the event the measured droop is outside of the limits, the system can take different measures to reduce the clock frequency and therefore reduce the step change in power to prevent SDCs.

A circuit includes a plurality of differential pairs of transistors and circuitry connected to the plurality of differential pairs of transistors. The plurality of differential pairs of transistors is configured to receive a first clock and a second clock and to generate an output representing an exclusive OR sum of the first and second clocks. The circuitry is configured to compensate for mismatch between the plurality of differential pairs of transistors so that the output is zero when the first and second clocks are in quadrature with each other and the output is non-zero when the first and second clocks are not in quadrature with each other regardless of mismatch between the plurality of differential pairs of transistors.

Delay circuitry includes a temperature compensation control circuit and a delay circuit. The temperature compensation control circuit is configured to generate a target temperature compensation control signal based on an initial control signal, a real-time ambient temperature signal, a temperature coefficient compensation enable signal, and a temperature coefficient control signal. The delay circuit is connected to the temperature compensation control circuit, and is configured to generate a temperature compensated target delay signal based on the target temperature compensation control signal and an initial delay signal such that a delay time of the target delay signal generated by the delay circuit can be dynamically compensated based on a real-time ambient temperature signal collected by a temperature sensor.

One aspect includes implementing capacity reduction in a storage system, including: for each of a candidate page and a target page in the storage system, identifying a subset of sectors having identical data or a minimum amount of different data; performing a bitwise exclusive OR (XOR) operation on sectors of the candidate page and the target page; determining an entropy from a result of the XOR operation. When the entropy is determined to be less than or equal to a threshold, one aspect includes constructing a reference page from XOR sectors containing results of the bitwise XOR operation, and performing a compression operation on the reference page.