426results about "Exclusive-OR circuits" patented technology

The invention provides a ternary logic gate circuit, a calculation circuit, a chip and electronic equipment. The ternary logic gate circuit provided by the invention can realize addition and subtraction of 1 to an input logic value. Based on the ternary logic gate circuit, 27 univariate functions of ternary logic are utilized, the ternary logic gate circuit is applied to the ternary logic circuit, the purpose of simplifying the structure of the ternary logic circuit can be achieved, the number of transistors in the ternary logic circuit can be reduced, the power consumption of the ternary logic circuit can be reduced, and the reliability of the ternary logic circuit is improved. And the calculation efficiency of the ternary logic circuit is improved.

A computation node comprises an input, an output, a bistable node, comprising an input and an output, the output configured to have at least two equilibrium output voltages, a first buffer circuit, having an input and an output, the buffer input connected to the bistable node and the buffer output connected to the computation node, the buffer circuit configured to provide a first output voltage when a voltage at the buffer input is below a threshold, and a second output voltage when the voltage at the buffer input is above the threshold, and a current conveyor node having an input connected to the computation node and an output connected to the bistable node, the current conveyor configured to hold its input at a constant voltage and mirror current received at the input into the input of the bistable node. A network of resistively-coupled computation nodes is also described.

The present disclosure relates to a universal logic memory block using a plurality of universal logic memory cells. The universal logic memory block according to one embodiment of the present disclosure may implement various combinational logical operations in a single structure by combining logical operation results from a plurality of universal logic memory cells using triple-gate silicon devices driven by a positive feedback loop.

The embodiment of the invention provides a memory chip, a logic chip, a chip stacking structure and a memory, a global signal area of the memory chip is penetrated by a plurality of conductive through hole groups, each conductive through hole group comprises a first redundant conductive through hole group and a second redundant conductive through hole group, the first redundant conductive through hole group comprises a first conductive through hole and a fourth conductive through hole, and the second redundant conductive through hole group comprises a second conductive through hole and a third conductive through hole; the first redundant conductive through hole group is used for transmitting the same first global signal, and the second redundant conductive through hole group is used for transmitting the same second global signal.

According to an embodiment, a clock signal is input to clock terminals of first and second FFs. A first signal from a Q terminal of the first FF is input to a D terminal of the second FF. A first inverter performs inversion calculation on a second signal from a Q terminal of the second FF. A signal from the first inverter is input to a D terminal of the first FF. A second inverter performs inversion calculation on the first signal. (L−1) adders each calculate a different bit of a Gray code by an addition operation based on a carry signal. A circuit block generates a carry signal for a first adder based on a logical product of the first / second signals. The circuit block generates carry signals of second to (L−1)th adders based on the second signal and a signal from the second inverter.

Certain aspects are directed towards an interpolator and / or a clock generator. An example interpolator generally includes: a first capacitive element; a first current source; a first switch coupled between the first capacitive element and the first current source; a second current source; a second switch coupled between the first capacitive element and the second current source; and a first comparison circuit having an input coupled to the first capacitive element.

The present invention relates to a duobinary signal reception device and method in which: a variable gain amplifier (VGA) amplifies a duobinary signal; a duobinary-to-non return to zero (NRZ) converter restores an NRZ signal on the basis of a differential signal of the amplified duobinary signal and a predetermined reference voltage signal; a digital regulator voltage (DRV) circuit outputs the restored NRZ signal; and the duobinary-to-NRZ converter comprises an exclusive OR (XOR) gate to which the differential signal of the amplified duobinary signal is input, and a comparator to which an output of the XOR gate and the reference voltage signal are input.

The invention discloses a dual-path time delay difference PUF circuit, which comprises two time delay modules, two arbiters, a first exclusive-OR gate, n-1 time delay arbitration modules and an exclusive-OR gate array, each time delay module comprises n switch unit arrays, each switch unit array comprises m switch units, n is an integer greater than or equal to 1, n is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. Each time delay arbitration module comprises two arbiters and an exclusive-OR gate, the exclusive-OR gate array comprises n-1 exclusive-OR gates, each time delay module is divided into n switch unit arrays, and the two time delay modules are divided into n switch unit array combinations, inserting a time delay arbitration module between every two adjacent switch unit array combinations to extract an intermediate response, then performing XOR processing on the intermediate response through an XOR logic gate array to obtain a response, and then performing XOR processing on the response and responses output by two arbiters again through a first XOR gate to obtain a final response; the method has the advantages of high machine learning attack resistance and low hardware overhead.

An equalizer includes a delay circuit configured to generate at least one delay signal based on at least one input signal, an encoding circuit configured to generate a plurality of driving signals and a connection switching signal, based on the input signal and the delay signal, a pre-driver configured to generate a plurality of driving switching signals based on the plurality of driving signals, a first differential circuit configured to generate a first differential output signal based on the plurality of driving switching signals, a second differential circuit configured to generate a second differential output signal based on the plurality of driving switching signals, and a connection circuit configured to adjust a connection between the first differential circuit and the second differential circuit based on the connection switching signal.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The invention discloses a Boolean logic circuit based on a memristor, a control method and a Boolean logic operation device, and belongs to the technical field of microelectronic devices. The Boolean logic circuit comprises a memristor M1, a memristor M2, a first NMOS (N-channel Metal Oxide Semiconductor) tube, a second NMOS tube, a resistor and a voltage comparator; a voltage Vr is applied to the control end of the T1 and the control end of the T2 respectively, a grid voltage corresponding to a logic value a is applied to the grid of the first transistor, a grid voltage corresponding to a logic value c is applied to the grid of the second transistor, and the control end of the T3 is grounded, so that a corresponding Boolean logic operation result can be obtained at the output end of the voltage comparator. According to the invention, the resistance state characteristic of the memristor and the switching characteristic of the transistor are fully utilized, the values of the logic values a, b, c and d are set, any Boolean logic operation can be realized with fewer operation steps, and the realization of complete Boolean logic operation is supported. Meanwhile, the method is easy to cascade and has the advantage of parallel computing.

Examples of the presently disclosed technology provide CAM-based circuits specially constructed to implement Boolean satisfiability problems involving k-XOR-SAT clauses. With the strategic addition of auxiliary counting and logic circuits that evaluate match line voltage outputs of a CAM at k discrete times in order to determine whether a counted number of matches returned by a match line satisfies a pre-determine parity condition—where k represents a number of literals of a k-XOR-SAT clause of a Boolean satisfiability problem—a circuit of the present technology can leverage a common CAM (i.e., the same CAM) to implement the k-XOR-SAT clause and k-SAT clauses. Accordingly, this extremely versatile circuit can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT hybrid problems in less time, and with less hardware and power consumption than existing hardware accelerators.

An IC device includes a first interconnect structure configured to distribute a power supply voltage, a second interconnect structure configured to distribute a reference voltage, a third interconnect structure configured to distribute a first power gating signal, and a plurality of logic circuits. Each logic circuit of the plurality of logic circuits includes a power switch coupled in series with a logic gate between the first and second interconnect structures, and the power switch includes a control terminal coupled to the third interconnect structure.

The invention provides an SOT-MRAM memory calculation unit, array, system and method supporting exclusive-or operation, which support data writing and reading and exclusive-or operation and complete common exclusive-or operation in a memory to reduce data transmission so as to relieve the storage wall problem. The SOT-MRAM storage and calculation unit provided by the invention comprises a first NMOS (N-channel Metal Oxide Semiconductor) tube, a first transmission gate and a magnetic tunnel junction SOT-MTJ, the SOT-MRAM storage and calculation array disclosed by the invention comprises four SOT-MRAM storage and calculation units which are arranged in a 2 * 2 manner; the SOT-MRAM storage and calculation system disclosed by the invention comprises an SOT-MRAM storage and calculation array, two induction circuit modules and an XOR operation circuit module, the SOT-MRAM storage and calculation method comprises the following steps of data writing operation, data reading operation and XOR operation.

Systems and methods for performing signed matrix operations using a linear photonic processor are provided. The linear photonic processor is formed as an array of first amplitude modulators and second amplitude modulators, the first amplitude modulators configured to encode elements of a vector into first optical signals and the second amplitude modulators configured to encode a product between the vector elements and matrix elements into second optical signals. An apparatus may be used to implement a signed value of an output of the linear processor. The linear photonic processor may be configured to perform matrix-vector and / or matrix-matrix operations.

The application provides a method and device for generating a pseudo-random sequence, an electronic device and a computer readable storage medium. The method comprises: performing AND operation and XOR operation on M bit values of a first sequence to obtain an (A+m)th bit value of the first sequence; wherein M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0; and determining an mth bit value of the pseudo-random sequence according to the (A+m)th bit value of the first sequence.

A circuit for detecting metastability in an asynchronous successive approximation register analog-to-digital converter; wherein the dual output comparator is arranged to receive a first input signal and a second input signal, compare the first input signal with the second input signal, and drive one of the first comparison signal and the second comparison signal to a set state based on the comparison. When the first comparison signal is in the set state, the first output end is in the set state. When the second comparison signal is in the set state, the second output end is in the set state. If a predetermined duration elapses after the dual output comparator starts comparison, and if both the first comparison signal and the second comparison signal are in a reset state, the control logic outputs a set state at both the first output and the second output. This allows the metastability of the comparator to be detected in the asynchronous SAR ADC. The control logic may effectively terminate the comparison if a predetermined duration is reached. In other words, the control logic may overwrite the comparator output to provide a defined output indicative of metastability.

An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.

The embodiment of the invention provides a content addressing register and an operation method thereof, a processor and a memory system. The content addressing register comprises a plurality of memory cells, each word line and each bit line bus of which are coupled; the sequential control circuit is configured to determine a working mode and generate a control signal in the corresponding working mode according to a received bus command; the working modes comprise a reading mode, a writing mode and a comparison mode; an address line control circuit configured to: activate corresponding word line and bit line buses based on a control signal; the processing and output circuit is configured to read out the data stored in the storage unit from the bit line bus in a reading mode; in the writing mode, writing the data to be written into the storage unit from the bit line bus; in the comparison mode, to-be-compared data input from the bit line bus is compared with data stored in the storage unit, and a comparison result is output.

The invention relates to the technical field of memristors, and provides a chitosan-based memristor which comprises a substrate, a buffer layer, a composite dielectric layer and a top electrode which are sequentially stacked from bottom to top, the buffer layer is formed by spin-coating a PEDOT: PSS aqueous solution on the substrate and then carrying out heat treatment; the composite dielectric layer is formed by spin-coating the buffer layer with an ultrasonic composite solution formed by a graphene oxide aqueous dispersion and a chitosan acetic acid solution and then carrying out heat treatment. By adopting a collaborative architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT: PSS buffer layer, the prepared bio-based memristor has the effects of relatively high switching ratio, relatively low operating voltage and good performance stability. Meanwhile, based on stable high and low resistance states of the device, all seven basic logic operations including a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate and an XNOR gate are completely realized on a single bio-based platform, the function accuracy can reach 100%, and an unexpected effect is achieved.

An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate / pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

The invention discloses a normal distribution quantum state preparation method and device, and the method comprises the steps: preparing a quantum state of a first register from an initial state into a first quantum state representing a target value, and enabling the target value to be a value in a random variable value range after target normal distribution processing; preparing the quantum state of the second register from an initial state to a second quantum state representing a target value square; preparing a quantum state of a third register from an initial state to a third quantum state with an index including a target value square by using the second quantum state through a quantum logic gate combination for preparing an exponential distribution quantum state; and carrying out amplitude amplification on a superposition state comprising the first quantum state and the third quantum state to obtain a normal distribution quantum state. According to the embodiment of the invention, the normal distribution quantum state can be accurately prepared.

A switching converter includes a power stage and a controller. The power stage drives a current through an inductance in a duration specified by a control signal. The phase controller generates the control signal to cause the power stage to generate a regulated supply voltage. The power stage is designed to communicate with the phase controller on a path. The power stage includes a first sub-stage and a second sub-stage that respectively drive a first sub-current and a second sub-current via corresponding inductors in response to the control signal. The corresponding inductors together operate to provide the inductance. The path is used for communication between the first sub-stage and the phase controller, and then between the second sub-stage and the phase controller in alternate cycles of the control signal.

Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

A slew-rate control circuit, including: a proportional calculation circuit, which generates a first indicating voltage according to a plurality of adjusted first signals within a previous preset period and a plurality of first signals within a current preset period, and generates a second indicating voltage according to the plurality of adjusted first signals within the previous preset period and a plurality of second signals that are inverted from the plurality of first signals within the current preset period; a logic operation circuit, which generates an operation result according to a relationship between the first indicating voltage, and first and second reference voltages, and a relationship between the second indicating voltage, and the first and second reference voltages; and an output adjustment circuit, which determines whether to invert the multiple first signals within the current preset period according to the operation result.

A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.

An integrated circuit (IC) containing a circuit to be operable using one of multiple unequal power supplies during normal operation of the IC. The IC contains a one time programmable (OTP) memory containing a first bit and a second bit, with each of the bit having an initial value and being programmable to a programmed value. A configuration engine contained in the IC operates the circuit with a first selection with respect to using one of the unequal power supplies during normal operation of the IC if both of the first bit and the second bit have an equal value comprising one of the initial value and the programmed value. The configuration engine operates the circuit with a second selection with respect to using one of the unequal power supplies during normal operation of the IC if the first bit and the second bit have unequal values.

The embodiment of the invention provides a state switching method and device and electronic equipment, and the method comprises the steps: generating and maintaining a state switching signal under the condition that a preset state switching condition is satisfied; performing state switching on the target object by adopting the state switching signal; counting the time interval between the current moment and the ending moment of the synchronous alignment signal; the synchronous alignment signal is a signal which is applied to the target object and is earlier than the state switching signal; under the condition that the time interval meets the preset condition, the state switching signal is ended, and state switching of the target object is completed; the preset condition comprises that the time interval is even times of the first clock period. According to the scheme of the embodiment, the output signal after state switching of the target object is synchronized with the synchronous alignment signal, the problem of time sequence chaos is solved, and the circuit performance is improved.