198results about "Exclusive-OR circuits" patented technology

The present invention relates to a duobinary signal reception device and method in which: a variable gain amplifier (VGA) amplifies a duobinary signal; a duobinary-to-non return to zero (NRZ) converter restores an NRZ signal on the basis of a differential signal of the amplified duobinary signal and a predetermined reference voltage signal; a digital regulator voltage (DRV) circuit outputs the restored NRZ signal; and the duobinary-to-NRZ converter comprises an exclusive OR (XOR) gate to which the differential signal of the amplified duobinary signal is input, and a comparator to which an output of the XOR gate and the reference voltage signal are input.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The application provides a method and device for generating a pseudo-random sequence, an electronic device and a computer readable storage medium. The method comprises: performing AND operation and XOR operation on M bit values of a first sequence to obtain an (A+m)th bit value of the first sequence; wherein M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0; and determining an mth bit value of the pseudo-random sequence according to the (A+m)th bit value of the first sequence.

The embodiment of the invention provides a content addressing register and an operation method thereof, a processor and a memory system. The content addressing register comprises a plurality of memory cells, each word line and each bit line bus of which are coupled; the sequential control circuit is configured to determine a working mode and generate a control signal in the corresponding working mode according to a received bus command; the working modes comprise a reading mode, a writing mode and a comparison mode; an address line control circuit configured to: activate corresponding word line and bit line buses based on a control signal; the processing and output circuit is configured to read out the data stored in the storage unit from the bit line bus in a reading mode; in the writing mode, writing the data to be written into the storage unit from the bit line bus; in the comparison mode, to-be-compared data input from the bit line bus is compared with data stored in the storage unit, and a comparison result is output.

The invention relates to the technical field of memristors, and provides a chitosan-based memristor which comprises a substrate, a buffer layer, a composite dielectric layer and a top electrode which are sequentially stacked from bottom to top, the buffer layer is formed by spin-coating a PEDOT: PSS aqueous solution on the substrate and then carrying out heat treatment; the composite dielectric layer is formed by spin-coating the buffer layer with an ultrasonic composite solution formed by a graphene oxide aqueous dispersion and a chitosan acetic acid solution and then carrying out heat treatment. By adopting a collaborative architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT: PSS buffer layer, the prepared bio-based memristor has the effects of relatively high switching ratio, relatively low operating voltage and good performance stability. Meanwhile, based on stable high and low resistance states of the device, all seven basic logic operations including a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate and an XNOR gate are completely realized on a single bio-based platform, the function accuracy can reach 100%, and an unexpected effect is achieved.

Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.

An integrated circuit (IC) containing a circuit to be operable using one of multiple unequal power supplies during normal operation of the IC. The IC contains a one time programmable (OTP) memory containing a first bit and a second bit, with each of the bit having an initial value and being programmable to a programmed value. A configuration engine contained in the IC operates the circuit with a first selection with respect to using one of the unequal power supplies during normal operation of the IC if both of the first bit and the second bit have an equal value comprising one of the initial value and the programmed value. The configuration engine operates the circuit with a second selection with respect to using one of the unequal power supplies during normal operation of the IC if the first bit and the second bit have unequal values.

The present disclosure provides an integrated circuit, which includes a divider stage, a frequency trimming stage, a voltage control stage, and a logic stage. The divider stage is configured to generate a first clock signal by dividing a frequency of an input clock signal. The frequency trimming stage is configured to add a first delay to the first clock signal to generate a second clock signal. The voltage control stage is configured to repeatedly adjust a second delay of the second clock signal according to a control signal generated by a feedback path to generate a third clock signal. The logic stage is configured to perform a logic operation according to the first clock signal and the third clock signal to generate an output clock signal.

A gate apparatus configured to perform an XOR operation on received input signals to provide a logical output signal, y. The apparatus includes at least one first signal input adapted to receive a first input signal; and at least one second signal input adapted to receive a second input signal. At least one of the received input signals is split into a first split signal portion fed to a photo diode to generate an electrical photocurrent supplied to a junction node, and a second split signal portion combined with at least a signal portion of the other signal received at the second signal input to generate a combined optical output signal supplied to an electro-optical modulator to provide the logical output signal, y. The electro-optical modulator is driven by a photocurrent processing unit having an input connected to the junction node.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

This invention relates to the field of integrated circuit technology and discloses a clock gating circuit, a clock signal control method, a chip, and an electronic device. By adding a feedback circuit based on a first reverse voltage signal generation module and a first OR gate unit to a conventional clock gating circuit, when the second register group needs to operate, a second enable signal corresponding to the second gating unit is generated to control the second gating unit to open. Based on the second enable signal, the feedback circuit then controls the first gating unit to open, thereby controlling the second register group to enter the working state. Therefore, this invention only needs to generate a second enable signal to simultaneously control the opening of the first and second gating units, eliminating the need to generate separate first and second enable signals to control the opening of the first and second gating units. This avoids the process of determining which gating units need to be opened based on the second gating unit, effectively improving the working efficiency of the clock gating circuit.

Disclosed is a stateful logic-in-memory using silicon diodes. More particularly, the stateful logic-in-memory according to an embodiment of the present invention includes a plurality of silicon diodes, each of the silicon diodes includes an anode region, a first channel region, a second channel region and a cathode region and is included as a memory cell.

A method for manufacturing a semiconductor structure includes forming a fin over a substrate. The fin includes first semiconductor layers and second semiconductor layers alternating stacked in a first direction. The method also includes forming a dummy gate structure over the fin, forming first gate spacers on opposite sides of the dummy gate structure in a second direction, forming source / drain features on opposite sides of the dummy gate structure in the second direction, replacing the dummy gate structure and the first semiconductor layers with a gate structure, replacing the first gate spacers with second gate spacers, and forming inner spacers between the second semiconductor layers in the first direction. The gate structure wraps around the first semiconductor layers. Each of the second gate spacers has a first air gap. Each of the inner gate spacers has a second air gap.

A circuit is provided having: a first input configured to receive first data; a second input coupled and configured to receive second data; a clock input configured to receive a clock signal during a first time period, the clock signal having a trigger edge during the first time period; and an output. The circuit is configured to output first data through the output before a first time period begins, and to output second data through the output and avoid outputting the first data in response to receiving a clock signal having a trigger edge during the first time period.

A circuit may comprise a first multiplexer, a second multiplexer, a combination of logic gates, a third multiplexer, a first low-pas filter, and a second low-pass filter. The first multiplexer can be configured to receive and select a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. Respective phases of the first to fourth clock signals are related to each other. The second multiplexer can be configured to receive and select the first to fourth clock signals. The combination of logic gates may comprise a first logic gate and a second logic gate. The combination of logic gates can be coupled to the second multiplexer and can be configured to receive the second plurality of the first to fourth clock signals. The third multiplexer can be configured to receive and select the first to fourth outputs.

A non-overlapping clock generator based on exclusive-NOR gates. The non-overlapping clock generator generates a non-overlapping in-phase output clock signal and an inverting output clock signal from an input clock signal. The non-overlapping clock generator includes first and second exclusive-NOR gates, first and second load transistors cross-coupled to each other, and first and second delay circuits coupled between the in-phase output clock signal and the control terminal of the first load transistor and between the inverting output clock signal and the control terminal of the second load transistor, respectively. Each exclusive-NOR gate includes at least one pass transistor logic to implement exclusive-NOR logic, the at least one pass transistor logic being coupled to the first control voltage. A non-overlapping period between the in-phase output clock signal and the inverting output clock signal is determined based on the first control voltage and / or the delay periods of the first and second delay circuits.

The invention discloses a peak filter circuit capable of keeping the pulse width of an input signal, which comprises an input circuit, a first positive feedback filter circuit, a second positive feedback filter circuit and a filter output selection circuit, the output end of the input circuit is connected with the input end of the first positive feedback filter circuit and the input end of the second positive feedback filter circuit, and the output end of the first positive feedback filter circuit and the output end of the second positive feedback filter circuit are connected with the input end of the filter output selection circuit. The output end of the filter output selection circuit generates an output signal VOUT. According to the invention, the pulse width of the input signal can be maintained while the expected peak voltage is filtered, and the reliability of communication between chips is improved.

An example circuit, method, and electronic device configured to filter pulses below a minimum threshold pulse width and provide delays that exhibit low variance to changes in temperature, voltage, and technology processes, are provided. The example circuit includes a first flip / flop, a second flip / flop, and a charge detector. The first flip / flop generates a first out signal and a first inverse signal based on an input signal and a first clocking signal. The second flip / flop generates an output signal and a second out signal based on the first out signal, the first inverse signal, and a second clocking signal, wherein the second clocking signal is an inverse of the first clocking signal. The charge detector circuit includes a charging capacitor to generate a charge signal based on a change in the input signal, such that pulses are filtered based on a capacitance value of the charging capacitor and a reference voltage.

The present disclosure relates to a metal structure applicable to a semiconductor device, and more specifically, to a metal structure or method for controlling a skyrmion. A metal structure according to an embodiment of the present disclosure is characterized by including: a magnetic layer; and a heavy metal layer formed on the magnetic layer, having a convex portion, and guiding movement of a first skyrmion within the magnetic layer.

The invention relates to the technical field of circuit design, and discloses a multi-intensity emotion enhancement memristor bionic circuit which comprises a language enhancement module, a fear emotion module, an happy emotion module, an emotion enhancement module and a high-intensity memory module. Parallel light / heavy processing paths are arranged in the fear and happiness emotion module, and emotion stimulation of different intensities is distinguished. The light emotion signals are processed and then fed back to the language enhancement module, and formation of conventional memory is adjusted; and the severe emotion signal is transmitted to an independent high-intensity memory module for special storage. The language enhancement module integrally processes language signals and feedback adjustment signals of all the modules. The high-intensity memory module forms stable memory for severe emotional events through a parallel memristor structure. Through grading processing and signal interaction, the differential influence of emotions with different intensities and the interaction of multiple emotions can be simulated, a grading memory mechanism is established, and the fidelity and authenticity of circuit simulation biological memory are improved.

The utility model discloses a dead zone insertion circuit based on a gate-level circuit, and belongs to the technical field of gate-level circuits. A first input end of a first NAND gate is connected with a first complementary signal; the input end of the first NOT gate is connected with the first input end of the first NAND gate; the first resistance-capacitance circuit is connected with the output end of the first NOT gate through a first resistor; the first input end of the second NAND gate is connected with a second complementary signal, and the second input end of the second NAND gate is connected with the first resistance-capacitance circuit through a second resistor; the input end of the second NOT gate is connected with the first input end of the second NAND gate; the second resistance-capacitance circuit is connected with the output end of the second NOT gate through a third resistor; the first end of the fourth resistor is connected with the second input end of the first NAND gate, and the second end of the fourth resistor is connected between the third resistor and the second resistance-capacitance circuit. The beneficial effects are that through cooperation of the NAND gate, the NOT gate and the resistance-capacitance circuit, the circuit structure is simple, the safety and reliability of circuit work are improved, and the cost is low.

Aspects of the disclosure are directed to a test mode save and restore operation. In accordance with one aspect, the disclosure includes a hold latch cell configured to execute a save directive for a first operational state of a digital logic system and to execute a restore directive for the first operational state in the digital logic system in an operational mode; a first multiplexer coupled to the hold latch cell, the first multiplexer configured to execute a test sequence on the digital logic system in a test mode; and a logical XOR circuit coupled to the hold latch cell, the logical XOR circuit configured to perform a fault detection on the save directive and the restore directive to generate an error flag signal.

The embodiment of the present disclosure provides a delay-locked loop and a memory, the delay-locked loop comprising: a preprocessing module configured to receive an initial clock signal, preprocess the initial clock signal, output a first clock signal and a second clock signal; a first adjustable delay line configured to receive the first clock signal, adjust and transmit the first clock signal, and output a first target clock signal; a second adjustable delay line configured to receive the second clock signal, adjust and transmit the second clock signal, and output a second synchronization clock signal; and a first adjustment module configured to adjust the phase of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal. In this way, the first adjustment module can correct the phase difference between the first synchronization clock signal and the second target clock signal, and improve the phase deviation between the target clock signals.

The invention discloses a zero-power-consumption power-on reset circuit which is characterized in that a power supply voltage division unit performs voltage division on input power supply voltage and then outputs a first signal to a voltage detection unit; the voltage detection unit outputs a high-level or low-level second signal to the inverting unit according to a comparison result of the first signal and a preset threshold value. The inverting unit performs shaping and inverting processing on the second signal, generates a third signal and transmits the third signal to the output shaping unit. And the output shaping unit is used for buffering and shaping the third signal and outputting a reset signal. The AND gate unit inputs a reset signal and a sixth signal output by the D trigger unit to generate a fourth signal. And the delay unit receives the fourth signal, delays the fourth signal, generates a fifth signal and inputs the fifth signal to the D trigger unit. And the D trigger unit respectively receives the reset signal and the fifth signal, generates a sixth signal, inputs the sixth signal to the power supply voltage dividing unit, and turns off the power supply voltage dividing unit, so that the whole reset circuit keeps a zero power consumption state.

Embodiments of this application provide a convolution circuit, a convolution computing method, a chip, and an electronic device, applied to the field of chip technologies, to resolve problems of high power consumption and a large wiring area of a convolution circuit in an existing convolver. The convolution circuit includes a plurality of multipliers, a first adder coupled to the plurality of multipliers, and a second adder coupled to the first adder. Each multiplier includes a plurality of precoders, a plurality of encoder groups, and an adder tree circuit. Each precoder is in a one-to-one correspondence with one encoder group. Output ends of the plurality of encoder groups and input lines of the adder tree circuit are of a same quantity and in a one-to-one correspondence. In addition, the adder tree circuit is coupled to the first adder. The second adder is further coupled to a memory. A partial product that is related only to a weight parameter may be first accumulated with a constant 1 in the multiplier, and then added to results output by adder tree circuits in the second adder, to reduce an area and power consumption of the adder tree circuit.

An apparatus, including: a clock gating circuit, CGC, including: a clock gating device (920) configured to selectively gate / pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit (930) configured to select a non- complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

The present disclosure relates to a circuit comprising: —a first timing guard circuit (200) configured to detect when a slack time of a first data signal arriving at a first synchronous device (202) falls below a first threshold (SLG DELAY); and —a second timing guard circuit (200) configured to detect when a slack time of a second data signal arriving at a second synchronous device (202) falls below a second threshold (SLG DELAY), the first and second thresholds being different from each other.