312results about "Exclusive-OR circuits" patented technology

The present disclosure relates to a universal logic memory block using a plurality of universal logic memory cells. The universal logic memory block according to one embodiment of the present disclosure may implement various combinational logical operations in a single structure by combining logical operation results from a plurality of universal logic memory cells using triple-gate silicon devices driven by a positive feedback loop.

The embodiment of the invention provides a memory chip, a logic chip, a chip stacking structure and a memory, a global signal area of the memory chip is penetrated by a plurality of conductive through hole groups, each conductive through hole group comprises a first redundant conductive through hole group and a second redundant conductive through hole group, the first redundant conductive through hole group comprises a first conductive through hole and a fourth conductive through hole, and the second redundant conductive through hole group comprises a second conductive through hole and a third conductive through hole; the first redundant conductive through hole group is used for transmitting the same first global signal, and the second redundant conductive through hole group is used for transmitting the same second global signal.

Certain aspects are directed towards an interpolator and / or a clock generator. An example interpolator generally includes: a first capacitive element; a first current source; a first switch coupled between the first capacitive element and the first current source; a second current source; a second switch coupled between the first capacitive element and the second current source; and a first comparison circuit having an input coupled to the first capacitive element.

The present invention relates to a duobinary signal reception device and method in which: a variable gain amplifier (VGA) amplifies a duobinary signal; a duobinary-to-non return to zero (NRZ) converter restores an NRZ signal on the basis of a differential signal of the amplified duobinary signal and a predetermined reference voltage signal; a digital regulator voltage (DRV) circuit outputs the restored NRZ signal; and the duobinary-to-NRZ converter comprises an exclusive OR (XOR) gate to which the differential signal of the amplified duobinary signal is input, and a comparator to which an output of the XOR gate and the reference voltage signal are input.

An equalizer includes a delay circuit configured to generate at least one delay signal based on at least one input signal, an encoding circuit configured to generate a plurality of driving signals and a connection switching signal, based on the input signal and the delay signal, a pre-driver configured to generate a plurality of driving switching signals based on the plurality of driving signals, a first differential circuit configured to generate a first differential output signal based on the plurality of driving switching signals, a second differential circuit configured to generate a second differential output signal based on the plurality of driving switching signals, and a connection circuit configured to adjust a connection between the first differential circuit and the second differential circuit based on the connection switching signal.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The application provides a method and device for generating a pseudo-random sequence, an electronic device and a computer readable storage medium. The method comprises: performing AND operation and XOR operation on M bit values of a first sequence to obtain an (A+m)th bit value of the first sequence; wherein M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0; and determining an mth bit value of the pseudo-random sequence according to the (A+m)th bit value of the first sequence.

A circuit for detecting metastability in an asynchronous successive approximation register analog-to-digital converter; wherein the dual output comparator is arranged to receive a first input signal and a second input signal, compare the first input signal with the second input signal, and drive one of the first comparison signal and the second comparison signal to a set state based on the comparison. When the first comparison signal is in the set state, the first output end is in the set state. When the second comparison signal is in the set state, the second output end is in the set state. If a predetermined duration elapses after the dual output comparator starts comparison, and if both the first comparison signal and the second comparison signal are in a reset state, the control logic outputs a set state at both the first output and the second output. This allows the metastability of the comparator to be detected in the asynchronous SAR ADC. The control logic may effectively terminate the comparison if a predetermined duration is reached. In other words, the control logic may overwrite the comparator output to provide a defined output indicative of metastability.

The embodiment of the invention provides a content addressing register and an operation method thereof, a processor and a memory system. The content addressing register comprises a plurality of memory cells, each word line and each bit line bus of which are coupled; the sequential control circuit is configured to determine a working mode and generate a control signal in the corresponding working mode according to a received bus command; the working modes comprise a reading mode, a writing mode and a comparison mode; an address line control circuit configured to: activate corresponding word line and bit line buses based on a control signal; the processing and output circuit is configured to read out the data stored in the storage unit from the bit line bus in a reading mode; in the writing mode, writing the data to be written into the storage unit from the bit line bus; in the comparison mode, to-be-compared data input from the bit line bus is compared with data stored in the storage unit, and a comparison result is output.

The invention relates to the technical field of memristors, and provides a chitosan-based memristor which comprises a substrate, a buffer layer, a composite dielectric layer and a top electrode which are sequentially stacked from bottom to top, the buffer layer is formed by spin-coating a PEDOT: PSS aqueous solution on the substrate and then carrying out heat treatment; the composite dielectric layer is formed by spin-coating the buffer layer with an ultrasonic composite solution formed by a graphene oxide aqueous dispersion and a chitosan acetic acid solution and then carrying out heat treatment. By adopting a collaborative architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT: PSS buffer layer, the prepared bio-based memristor has the effects of relatively high switching ratio, relatively low operating voltage and good performance stability. Meanwhile, based on stable high and low resistance states of the device, all seven basic logic operations including a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate and an XNOR gate are completely realized on a single bio-based platform, the function accuracy can reach 100%, and an unexpected effect is achieved.

Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

A slew-rate control circuit, including: a proportional calculation circuit, which generates a first indicating voltage according to a plurality of adjusted first signals within a previous preset period and a plurality of first signals within a current preset period, and generates a second indicating voltage according to the plurality of adjusted first signals within the previous preset period and a plurality of second signals that are inverted from the plurality of first signals within the current preset period; a logic operation circuit, which generates an operation result according to a relationship between the first indicating voltage, and first and second reference voltages, and a relationship between the second indicating voltage, and the first and second reference voltages; and an output adjustment circuit, which determines whether to invert the multiple first signals within the current preset period according to the operation result.

A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.

An integrated circuit (IC) containing a circuit to be operable using one of multiple unequal power supplies during normal operation of the IC. The IC contains a one time programmable (OTP) memory containing a first bit and a second bit, with each of the bit having an initial value and being programmable to a programmed value. A configuration engine contained in the IC operates the circuit with a first selection with respect to using one of the unequal power supplies during normal operation of the IC if both of the first bit and the second bit have an equal value comprising one of the initial value and the programmed value. The configuration engine operates the circuit with a second selection with respect to using one of the unequal power supplies during normal operation of the IC if the first bit and the second bit have unequal values.

A control circuit outputs a first control signal and a second control signal to a first control input and a second control input, respectively, of a programmable delay circuit. In certain aspects, the control circuit receives a rising edge of a delay control signal. In response to the rising edge of the delay control signal, the control circuit outputs a rising edge of the first control signal and a falling edge of the second control signal after the rising edge of the first control signal. The control circuit also receives a falling edge of the delay control signal. In response to the falling edge of the delay control signal, the control circuit outputs a rising edge of the second control signal and outputs a falling edge of the first control signal after the rising edge of the second control signal.

The present disclosure provides an integrated circuit, which includes a divider stage, a frequency trimming stage, a voltage control stage, and a logic stage. The divider stage is configured to generate a first clock signal by dividing a frequency of an input clock signal. The frequency trimming stage is configured to add a first delay to the first clock signal to generate a second clock signal. The voltage control stage is configured to repeatedly adjust a second delay of the second clock signal according to a control signal generated by a feedback path to generate a third clock signal. The logic stage is configured to perform a logic operation according to the first clock signal and the third clock signal to generate an output clock signal.

Provided in the embodiments of the present disclosure are a memory chip, a logic chip, a chip stacking structure, and a memory. A global signal area of the memory chip is penetrated by a plurality of conductive through hole groups, and each conductive through hole group comprises a first redundant conductive through hole group and a second redundant conductive through hole group, wherein the first redundant conductive through hole group comprises a first conductive through hole and a fourth conductive through hole, and the second redundant conductive through hole group comprises a second conductive through hole and a third conductive through hole; and the first redundant conductive through hole group is configured to transmit the same first global signal, and the second redundant conductive through hole group is configured to transmit the same second global signal.

A gate apparatus configured to perform an XOR operation on received input signals to provide a logical output signal, y. The apparatus includes at least one first signal input adapted to receive a first input signal; and at least one second signal input adapted to receive a second input signal. At least one of the received input signals is split into a first split signal portion fed to a photo diode to generate an electrical photocurrent supplied to a junction node, and a second split signal portion combined with at least a signal portion of the other signal received at the second signal input to generate a combined optical output signal supplied to an electro-optical modulator to provide the logical output signal, y. The electro-optical modulator is driven by a photocurrent processing unit having an input connected to the junction node.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

This invention relates to the field of integrated circuit technology and discloses a clock gating circuit, a clock signal control method, a chip, and an electronic device. By adding a feedback circuit based on a first reverse voltage signal generation module and a first OR gate unit to a conventional clock gating circuit, when the second register group needs to operate, a second enable signal corresponding to the second gating unit is generated to control the second gating unit to open. Based on the second enable signal, the feedback circuit then controls the first gating unit to open, thereby controlling the second register group to enter the working state. Therefore, this invention only needs to generate a second enable signal to simultaneously control the opening of the first and second gating units, eliminating the need to generate separate first and second enable signals to control the opening of the first and second gating units. This avoids the process of determining which gating units need to be opened based on the second gating unit, effectively improving the working efficiency of the clock gating circuit.

The invention discloses a universal input / output interface, and belongs to the technical field of transmission interfaces of digital circuits and analog circuits, the universal input / output interface comprises a TX module, an RX module and a withstand voltage protection circuit, and the TX module comprises a first phase inverter; a second inverter; a first AND gate; a second AND gate; a first NAND gate; a second NAND gate; a third NAND gate; a third AND gate; a bias circuit; a level conversion circuit; a buffer; a first pmos tube; a second pmos tube; a first nmos tube; a second nmos tube; a third pmos tube; a fourth pmos tube; the RX module comprises a Schmitt trigger; a first switch; a pull-up resistor; a pull-down resistor; a second switch; the withstand voltage protection circuit comprises a third nmos tube to a seventh nmos tube; a fifth pmos tube to a tenth pmos tube; the electrostatic discharge protection circuit includes a p-type diode and an n-type diode. The range of the output level signal is selectable, and the application scenarios of the circuit can be increased.

An electronic device and a method for monitoring a driver's output signal are provided. The electronic device includes: a driver connected to a pin, receiving an input signal, and outputting an output signal to the pin in response to the input signal; a core circuit that transmits the input signal to the driver; and a monitoring circuit that receives the input signal and an output signal and detects a stagnation voltage state of the output signal based on the input and output signals. The monitoring circuit includes: a first detection circuit that detects a stagnation voltage state when the input and output signals are logically incorrect; a second detection circuit that detects a stagnation voltage state when the input and output signals are logically correct and the output signal is at a low level; and a third detection circuit that detects a stagnation voltage state when the input and output signals are logically correct and the output signal is at a high level.

Disclosed is a stateful logic-in-memory using silicon diodes. More particularly, the stateful logic-in-memory according to an embodiment of the present invention includes a plurality of silicon diodes, each of the silicon diodes includes an anode region, a first channel region, a second channel region and a cathode region and is included as a memory cell.

A method for manufacturing a semiconductor structure includes forming a fin over a substrate. The fin includes first semiconductor layers and second semiconductor layers alternating stacked in a first direction. The method also includes forming a dummy gate structure over the fin, forming first gate spacers on opposite sides of the dummy gate structure in a second direction, forming source / drain features on opposite sides of the dummy gate structure in the second direction, replacing the dummy gate structure and the first semiconductor layers with a gate structure, replacing the first gate spacers with second gate spacers, and forming inner spacers between the second semiconductor layers in the first direction. The gate structure wraps around the first semiconductor layers. Each of the second gate spacers has a first air gap. Each of the inner gate spacers has a second air gap.

A circuit is provided having: a first input configured to receive first data; a second input coupled and configured to receive second data; a clock input configured to receive a clock signal during a first time period, the clock signal having a trigger edge during the first time period; and an output. The circuit is configured to output first data through the output before a first time period begins, and to output second data through the output and avoid outputting the first data in response to receiving a clock signal having a trigger edge during the first time period.

A circuit may comprise a first multiplexer, a second multiplexer, a combination of logic gates, a third multiplexer, a first low-pas filter, and a second low-pass filter. The first multiplexer can be configured to receive and select a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. Respective phases of the first to fourth clock signals are related to each other. The second multiplexer can be configured to receive and select the first to fourth clock signals. The combination of logic gates may comprise a first logic gate and a second logic gate. The combination of logic gates can be coupled to the second multiplexer and can be configured to receive the second plurality of the first to fourth clock signals. The third multiplexer can be configured to receive and select the first to fourth outputs.

A non-overlapping clock generator based on exclusive-NOR gates. The non-overlapping clock generator generates a non-overlapping in-phase output clock signal and an inverting output clock signal from an input clock signal. The non-overlapping clock generator includes first and second exclusive-NOR gates, first and second load transistors cross-coupled to each other, and first and second delay circuits coupled between the in-phase output clock signal and the control terminal of the first load transistor and between the inverting output clock signal and the control terminal of the second load transistor, respectively. Each exclusive-NOR gate includes at least one pass transistor logic to implement exclusive-NOR logic, the at least one pass transistor logic being coupled to the first control voltage. A non-overlapping period between the in-phase output clock signal and the inverting output clock signal is determined based on the first control voltage and / or the delay periods of the first and second delay circuits.

The invention discloses an OR gate, a NOR gate and a maximum gate circuit realized based on a three-valued memristor, and belongs to the technical field of digital logic circuit design, the three-valued memristor is used in a three-valued digital logic circuit, and the OR gate, the NOR gate and the maximum gate circuit are realized. The multi-valued digital logic circuit carries more information, the complexity degree between circuit connecting lines is lower, the area and power consumption of the logic circuit are effectively reduced, the operational capability of the circuit is higher, the structure is clear and simple, implementation is easy, and the multi-valued digital logic circuit can be used for application research in many fields such as multi-valued digital logic operation.

The invention discloses a peak filter circuit capable of keeping the pulse width of an input signal, which comprises an input circuit, a first positive feedback filter circuit, a second positive feedback filter circuit and a filter output selection circuit, the output end of the input circuit is connected with the input end of the first positive feedback filter circuit and the input end of the second positive feedback filter circuit, and the output end of the first positive feedback filter circuit and the output end of the second positive feedback filter circuit are connected with the input end of the filter output selection circuit. The output end of the filter output selection circuit generates an output signal VOUT. According to the invention, the pulse width of the input signal can be maintained while the expected peak voltage is filtered, and the reliability of communication between chips is improved.