48results about "Counting chain pulse counters with non-natural counting order" patented technology

A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.

A modular Gray code counter of arbitrary bit length having identical Gray code counter cells in every bit position. Each cell comprises a Toggle Flop and logic which triggers the Toggle Flop and sets the state of the Gray code counter cell. The two outputs of a cell feed two inputs of the next more significant cell. A parity flip-flop provides odd parity, and as a third input to the cell together with the other two inputs determines the state of the cell.

There is offered a Gray code counter with which a delay time of a critical path is reduced and a fast operation is made possible. A first Gray code bit Q0 is obtained by outputting an output signal Q0o of an RDFF 2 through an RDFF 31 to synchronize with a clock CLK. A second Gray code bit Q1 is obtained by outputting an output signal Q1o of an RDFF 2 through an RDFF 32 to synchronize with the clock CLK. A third Gray code bit Q2 is obtained by delaying an output signal Q2o of an RDFF 4 with a selection circuit 21 and outputting it through an RDFF 33 to synchronize with the clock CLK. A fourth Gray code bit Q3 is obtained by delaying an output signal Q3o of an RDFF 5 with an AND circuit 11 and a selection circuit 22 and outputting it through an RDFF 34 to synchronize with the clock CLK. Higher bits of the Gray code are similarly generated.

A randomness testing apparatus is disclosed. A randomness testing apparatus according to an embodiment includes a randomness testing module to conduct a randomness test on physically unclonable function (PUF)-based hardware and a processing device to determine whether the PUF-based hardware is defective on the basis of a randomness test result.

Conventionally, it is difficult to design the logic of a Gray code counter that can be used in interlaced counting. Even though interlaced counting is possible with a Gray code counter, the number of simultaneously changing bits increases greatly depending on the number of counts skipped at a time. To overcome these problems, a Gray code counter according to the present invention has a consecutively counting Gray code counter that counts in increments or decrements of one, and an output value converter circuit that converts the Gray code data output from the consecutively counting Gray code counter into a Gray code corresponding to decimal counts as obtained by counting with (2 raised to a particular power minus 1) counts skipped at a time.

A gray code is produced from a minimum of gate logic by making available and monitoring master outputs of master-slave latch pairs, where the latch pairs are arranged to form a cascading chain of toggle flip-flop stages. The least significant bit through one less than the most significant bit in the gray code is supplied by the master latch outputs and the most significant gray code bit is supplied by the slave latch output of the last toggle stage in the chain.

A Gray code counter includes a holding circuit, first and second conversin circuit and an operation circuit. The holding circuit stores gray code signals and outputs the stored gray code signals in response to a clock signal. The first conversion circuit receives the gray code signals from the holding circuit and converts the received gray code signals into first binary code signals. The operation circuit applies a logical operation to the first binary code signals so as to generate second binary code signals. The second conversion circuit receives the second binary code signals and converts the received second binary code signals into the gray code signals. The second conversion circuit outputs the gray code signals to the holding circuit.

The invention provides a double-exponential nuclear signal counting method and device, and relates to the technical field of nuclear signal processing, and the method comprises the steps: obtaining ato-be-counted double-exponential nuclear signal; inputting the to-be-counted double-exponential nuclear signal into a pre-established transfer function, and obtaining an impulse signal output by the transfer function; and counting the to-be-counted double-exponential nuclear signal according to the impulse signal. In the implementation process, the to-be-counted double-exponential nuclear signalsare input into thepre-established transfer function, the output signals are impulse signals with short dead time, a sampling period is occupied, and the double-exponential nuclear signals are accurately counted by identifying the accumulated nuclear signals.

A method for generating a modulo Gray-code representation of a non-power-of-two set of binary values begins by determining a desired Gray-code sequence length. The method then continues by determining a bus width, M, in bits, based on the desired Gray-code sequence length, to represent the generated Gray-code. The method then continues by determining a set of skipped binary values based on the desired Gray-code sequence length and the bus width to obtain the non-power-of-two set of binary values. The method then continues by representing the non-power-of-two set of binary values as a set of equivalent Gray-code values.

The invention is a Gray code counter that uses a carry chain to determine the state of each bit of the counter. An additional bit that toggles at every clock is used to originate the carry chain, and to determine the counter direction. Then, a generic Gray count bit module is used to process the carry and count chain for each bit of the counter. Special consideration is given to the first and last bits of the counter to ensure correct termination and reset of the counter. A one bit gray code generic module is described such that a scalable counter can be generated recursively.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

A power control method includes: modulating a first bit stream by using a first modulation method to obtain a first modulation symbol, modulating a second bit stream by using a second modulation method to obtain a second modulation symbol, and adopting a third modulation mode to modulate a combined bit stream obtained by combining the first bit stream and the second bit stream to obtain a joint modulation symbol; obtaining a first correction coefficient and a second correction coefficient according to the first modulation symbol, the second modulation symbol, and the joint modulation symbol; correcting the first modulation symbol by using the first correction coefficient to obtain a first corrected modulation symbol, and correcting the second modulation symbol by using the second correction coefficient to obtain a second corrected modulation symbol; and respectively performing power control processing on the first corrected modulation symbol and the second corrected modulation symbol,and combining and sending the first corrected modulation symbol and the second corrected modulation symbol after the power control to a terminal device.

A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.

An N-bit Gray counter, with N an integer greater than 1, comprises a string of N logic cells connected in cascade, wherein each logic cell comprises an input port for a succession of clock pulses, a circuit for generating a Gray count bit having an output port for the Gray count bit and a circuit for generating a clock signal having a clock output port linked to the input port of the following logic cell. An analogue-digital converter of ramp type using such a Gray counter is also provided.

The invention relates to an even-number-of-times Gray code counter circuit, which belongs to the field of integrated circuits. The even-number-of-times Gray code counter circuit in the invention can count for 2N times; the output is an M-bit Gray code, wherein M and N are both positive integers, and the specific value of M is determined by the formula; the Gray code counter proposed by the invention comprises M+1 groups of triggers and a control module; it is determined that in the M+1th group to the second group of triggers, the M-bit Gray code is output by taking the Q output end or QB output end of the M+1th D trigger to the second D trigger as the output end of the M+1th group to the second group of triggers according to the Nth time of counting; the control module comprises an AND gate; the input end of the AND gate is connected with the M-bit Gray code; the output end thereof outputs a flag signal FLAG; when counting to the Nth time, the flag signal FLAG is logic 1 and logic 0 for the rest; and the M+1 groups of triggers are respectively composed of one D trigger and respective logic circuit. According to the even-number-of-times Gray code counter circuit in the invention, atransition state does not appear between the adjacent counting code values; the circuit is simple; and counting of any even number of times is realized.

The invention discloses a pulse density modulation method and a pulse density value signal conversion circuit. The method comprises the following steps of (S01) obtaining bits n of a binary density value, setting the bits of a counter to be n and setting an initial value of the counter to be 0 or 1; (S02) searching the rightmost 1, obtaining the bits j of the count of the rightmost 1 of a current value i of the counter from right to left, wherein the number in the counter is a binary number and the minimum value of j is 1; (S03) judging whether the corresponding bit is equal or not, if the jth bit of the d from left to right is 1, the signal bit output in the period is, if the jth bit of the d from left to right is 0, the signal bit output in the period is 0; and (S04) adding 1 to the value i of the counter, entering the next period and skipping to the step (S02). Output voltage can be more even and smooth.

Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.

Apparatuses, systems and methods associated with bidirectional Gray code counter design are disclosed herein. In embodiments, a bidirectional Gray code counter may include a sequential logic element to store a Gray code value and logic circuitry. The logic circuitry may be to determine, based on a bidirectional indicator signal, whether to increment or decrement the Gray code value update, through performance of an increment or a decrement of the Gray code value based on the determination of whether to increment or decrement the Gray code value, the Gray code value to be a sequential Gray code value and replace the Gray code value stored in the sequential logic element with the updated Gray code value. Other embodiments may be described and/or claimed.