32results about "Counting chain synchronous pulse counters" patented technology

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

In a first aspect, the disclosure provides an apparatus (412a) for wireless communication, comprising: a first clock loop (420) comprising a first plurality of latches (422, 424) that generate a first plurality of clock signals (I, Q) having a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) having a corresponding second plurality of phases, where the first clock loop is configured to be enabled or disabled based on the first enable signal and the second clock loop is configured to be enabled or disabled based on the second enable signal. And wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

In a clock domain crossover scenario, a flip-flop synchronizer features a reduced number of series-connected flip-flops (110, 113), receiving input data (A_q) from a first clock domain (107) and outputting data (120) from the second clock domain (114). The second clock signal has a variable frequency tuned to a target frequency by a division factor (k0). The flip-flops (110, 113) are clocked by a clock signal (CLK_k) that downsamples the second clock signal (CLK_B) by a factor of k1. The downsampled clock signal is generated by a frequency divider (301) that propagates a pulse of the signal (CLK_B) every k1 clock pulses, keeping the edges aligned. Theoretically, additional flip-flops (111, 112) are avoided.

Systems and methods for synchronizing multiple of output clocks. The system includes: a plurality of frequency dividers configured to receive a plurality of input clock signals and produce a plurality of output clock signals, wherein each of the plurality of output clock signals are lower in frequency than a corresponding input clock signal; and a circuit. The circuit is configured to: compare a first output clock signal of the plurality of output clock signals to a second output clock signal of the plurality of output clock signals to determine whether the first output clock signal is synchronized with the second output clock signal, generate a slip signal in response to determining that the first output clock signal is not synchronized with the second output clock signal, and apply the slip signal to the second output clock signal to synchronize the second output clock signal with the first output clock signal.

A synchronizer with flip-flops has a reduced number of flip-flops coupled in series, receiving as an input data of a first clock domain and supplying as an output data in the second clock domain. The second clock signal is at a variable frequency adjusted to a target frequency, by a division factor. The flip-flops are timed by a clock signal subsampling the second clock signal by a factor k1. The subsampled clock signal is generated by a frequency divider propagating a pulse of the signal every k1 clock pulses, while keeping the edges aligned.

The application relates to a random clock generation method and device against side channel attacks, wherein the method comprises the following steps: S1, selecting a reference clock as an input clock of a first round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; S2, randomly selecting a frequency multiplication clock from the frequency multiplication clocks, performing spur filtering, and then outputting the frequency multiplication clock as a system clock; S3, performing multi-path frequency division on the randomly selected frequency multiplication clock to obtain frequency division clocks with different frequency division coefficients; S4, randomly selecting a frequency division clock from the frequency division clocks, and performing multi-path frequency multiplication on the frequency division clock as an input clock of a next round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; and S5, repeating steps S2 to S4, and obtaining a system clock with various and random frequencies through multiple rounds of iteration. The application effectively improves the side channel attack protection effect.

The application relates to a programmable frequency divider and a phase-locked loop, the programmable frequency divider comprising a plurality of cascaded subtractors, a period end detection module and a delay reset circuit, wherein the plurality of cascaded subtractors are connected to corresponding initial value signals, under the triggering of a clock signal to be divided, the signals output by the plurality of cascaded subtractors correspond to the output results of decrement, and under the condition that the signals output by the plurality of cascaded subtractors reach a period end condition, the period end detection module outputs a period end signal to the delay reset circuit based on the signals output by the plurality of cascaded subtractors and the period end condition. Under the condition that the delay reset circuit receives the period end signal, a reset trigger signal is output to each subtractor so as to reset each subtractor. After a preset delay time length of the delay reset circuit after the reset trigger signal, a work trigger signal is output to each subtractor so as to make each subtractor work and enter the next round of decrement cycle operation.

A semiconductor device includes a pulse input circuit including flip-flops constituting each of two front-stage counters having different holding states from each other and configured such that first pulses from an even-stage ring circuit are input to each of the two front-stage counters, an edge detection circuit configured to detect edges of outputs of the two front-stage counters and output a second pulse having a predetermined pulse width larger than a predetermined value based on the edge, and a counter circuit including a rear-stage counter to which the second pulse is input. The edge detection circuit is configured to output the second pulse or a stepwise signal when a pulse width of the first pulse is smaller than the predetermined value.

An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

The embodiment of the present disclosure provides a counting circuit, comprising: a clock source, a clock control unit and N output units; wherein N is a positive integer. The clock control unit generates a clock control signal according to a clock signal output by the received clock source and output values of the first output unit to the Mth output unit, and outputs the clock control signal to clock input ends of the M+1th output unit to the Nth output unit, wherein the clock control signal has a first signal value and a second signal value with different signal values. The M+1th output unit to the Nth output unit latch when the received clock control signal switches from the second signal value to the first signal value; and keep the current state value unchanged when the received clock control signal is the second signal value.

The invention relates to a frequency modulation synchronizer for clock domain crossing. A synchronizer with flip-flops has a reduced number of flip-flops coupled in series that receive data of a first clock domain as an input and provide data in a second clock domain as an output. The second clock signal is at a variable frequency that is adjusted to a target frequency by a frequency division factor. The flip-flop is clocked by a clock signal subsampled by a factor k1 on the second clock signal. The sub-sampled clock signal is generated by a frequency divider that propagates one pulse of the signal per k1 clock pulses while maintaining edge alignment.

Aspects of the subject disclosure may include, for example, a track-and-hold sampling circuit, having: a duty-cycle limiter that generates a clock signal having a duty cycle that is less than 100% from three out of four clock signals; and a sampling circuit comprising complementary positive and negative input gates that track and sample data input signals, wherein the sampling circuit generates sampled data signals, wherein the complementary positive and negative input gates are coupled to the clock signal. Other embodiments are disclosed.

A pulse signal output circuit capable of stable operation and a shift resistor including the same. One of the objectives is to provide [a service / product]. [Solution] A pulse signal output circuit according to one aspect of the disclosed invention includes a node connected to the output terminal. The channel length of the transistors that make up the system is the channel length of the transistor that functions as the output terminal. Make it larger than the length of the loop. This will suppress current leakage from the node and prevent leakage over a long period of time. This makes it possible to maintain a stable potential over a long period, preventing malfunctions in the pulse signal output circuit. It can be stopped.

Frequency Divider This description relates to a frequency divider (300), comprising at least two flip-flops (302, 304) and in which a pull-up current (Itail) of each flip-flop is controlled by a reference current (IDAC). Figure for the abbreviation: Fig. 3

Reduce power consumption in semiconductor devices. The semiconductor device includes a latch circuit composed of dynamic circuitry. The latch circuit includes a first circuit with decoding functionality, multiple capacitors, multiple clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. During a first clock signal of "H", the potential of the first capacitor is refreshed according to the decoding result of the first circuit. During a second clock signal of "H", the potential of the second capacitor is refreshed according to the potential of the first capacitor, and the first output terminal receives the potential of the second capacitor as a first output signal. During a third clock signal of "H", the potential of the third capacitor is refreshed according to the potential of the second capacitor, and the second output terminal receives the potential of the third capacitor as a second output signal.

This disclosure provides in a first aspect, an apparatus (412a) for wireless communications including a first clock loop (420) comprising a first plurality of latches (422, 424) generating a first plurality of clock signals (I, Q) with a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) with a corresponding second plurality of phases, wherein the first clock loop is configured to be enabled or disabled based on a first enable signal, and wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

To provide a pulse signal output circuit which can stably operate and a shift register including the pulse signal output circuit.SOLUTION: A pulse signal output circuit according to an embodiment comprises first through tenth transistors. A ratio W / L of a channel width W to a channel length L of each of the first transistor and the third transistor is set larger than W / L of the sixth transistor; W / L of the fifth transistor is set larger than W / L of the sixth transistor; W / L of the fifth transistor is set identical to W / L of the seventh transistor; and W / L of the third transistor is set larger than W / L of the fourth transistor. As a result, the pulse signal output circuit which can stably operate and a shift register including the pulse signal output circuit can be provided.SELECTED DRAWING: Figure 1

This invention provides a de-glitching clock divider circuit, method, and terminal, including a first trigger module for counting an input reference clock based on an input division factor to output first count data; a second trigger module for generating an intermediate clock signal based on the division factor and the reference clock, and processing the first count data based on the intermediate clock signal to output second count data; a combination circuit connected to the output of the second trigger module to process the second count data and output an intermediate output signal; a third trigger module for outputting a second-level asynchronous reset signal based on the intermediate clock signal; and a fourth trigger module, whose reset terminal is connected to the output of the third trigger module, and which generates a divided clock based on the first count data and the reference clock. The frequency divider circuit of this invention not only increases the upper limit of the circuit's operating clock frequency but also improves clock stability.

An apparatus, including: a clock source configured to generate first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer; and a logic circuit configured to perform a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction.

The embodiment of the present application provides a kind of counter, comprising: counting module, including multiple cascaded sub-counters and the delay unit being connected between at least two adjacent sub-counters in multiple sub-counters;Wherein, sub-counter is used to count the number of clock pulses to output count output signal and carry output signal;Delay unit is used to receive the carry output signal of the previous stage sub-counter in at least two sub-counters, and the received carry output signal is output to the next stage sub-counter after being delayed;Data alignment module is used to receive the count output signal of multiple sub-counters, and the received multiple count output signals belonging to the same counting period are data-aligned according to the relationship corresponding to the delay time caused by delay unit, to output count result.

In a clock domain crossover scenario, a flip-flop synchronizer features a reduced number of series-connected flip-flops (110, 113), receiving input data (A_q) from a first clock domain (107) and outputting data (120) from the second clock domain (114). The second clock signal has a variable frequency tuned to a target frequency by a division factor (k0). The flip-flops (110, 113) are clocked by a clock signal (CLK_k) that downsamples the second clock signal (CLK_B) by a factor of k1. The downsampled clock signal is generated by a frequency divider (301) that propagates a pulse of the signal (CLK_B) every k1 clock pulses, keeping the edges aligned. Theoretically, additional flip-flops (111, 112) are avoided. Figure for the abbreviation: Figure 3

Aspects of the subject disclosure may include, for example, an inner clock generation circuit, including: a selectable frequency divider having: a ring of tri-state inverters; a reset gate on an output of each tri-state inverter in the ring; and a reset circuit comprising one or more selectable flip-flops; and a duty-cycle limiter that generates clock signals having a 25% duty cycle from three out of four quadrature clock signals. Other embodiments are disclosed.

The invention relates to a programmable frequency divider and a phase-locked loop, the programmable frequency divider comprises a plurality of cascaded subtracters, a period end detection module and a band delay reset circuit, the plurality of cascaded subtracters are accessed to corresponding initial value signals, and under the trigger of a clock signal to be subjected to frequency division, the period end detection module detects the initial value signals to be subjected to frequency division; signals output by the multiple cascaded subtracters correspond to decreasing output results, and under the condition that the signals output by the multiple cascaded subtracters reach a period ending condition, the period ending detection module outputs a period ending signal to the band delay reset circuit based on the signals output by the multiple cascaded subtracters and the period ending condition. And under the condition that the delay reset circuit receives the period end signal, a reset trigger signal is output to each subtractor, so that each subtractor is reset. And the reset circuit with time delay outputs a working trigger signal to each subtractor after a preset delay duration after the trigger signal is reset, so that each subtractor works, and the next round of decreasing cycle operation is entered.

A frequency division correction circuit includes: a first frequency divider (302) configured to perform decimal frequency division (divide by 1.5) on an input signal and output a first frequency division signal (CK11) and a second frequency division signal (CK14) which are different from each other in duty ratio; and a corrector (303) configured to generate a first output signal (CK21) having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.

The present invention provides a semiconductor device capable of stably counting pulses output from an even-stage ring circuit. [Solution] The semiconductor device includes a pulse input circuit 10 into which a first pulse from an even-stage ring circuit is input to each of two pre-stage counters, each comprising a flip-flop that constitutes a pre-stage counter having different holding states; an edge detection circuit 20 that detects the edges of the outputs of the two pre-stage counters and outputs a second pulse having a predetermined pulse width that is larger than a predetermined value based on the edge; and a counter circuit that includes a post-stage counter into which the second pulse is input. The edge detection circuit is configured to output a second pulse or a step-shaped signal if the pulse width of the first pulse is smaller than a predetermined value.

The objective is to provide a clock modulation circuit that can measure the characteristics of a clock with greater precision. [Solution] The clock modulation circuit of the embodiment includes a clock output circuit, a multiple frequency divider circuit that receives a clock from the clock output circuit and has a plurality of frequency divider circuits that divide the clock, and a frequency divider control circuit that controls the timing of the start of frequency division for each of the plurality of frequency divider circuits and controls the phase difference between at least one pair of output signals of the plurality of frequency divider circuits based on the period of the clock.