71results about "Counting chain synchronous pulse counters" patented technology

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

An apparatus, including: a clock source configured to generate first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer; and a logic circuit configured to perform a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction.

The invention relates to a method and system for an injection locked frequency divider with frequency calibration. In some embodiments, a circuit system may include a series of symmetric stages, where an initial stage in the series is coupled to an input signal having a first plurality of phases and an output stage in the series couples an output signal including a second plurality of phases to a calibration engine, wherein a number of the phases in the output signal increases based at least on a number of the symmetric stages and a number of the first plurality of phases in the input signal. Additionally, the circuitry may include embodiments in which the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include embodiments in which the calibration engine outputs a current provided to the series, where the output current may be based at least on a calibration frequency.

In some implementations, a circuitry may include a series of symmetrical stages with an initial stage in the series coupled to an input signal having a first plurality of phases and an output stage in the series coupling an output signal comprising a second plurality of phases to a calibration engine, where a quantity of the phases in the output signal is increased based at least on a quantity of the symmetrical stages and a quantity of the first plurality of the phases in the input signal. In addition, the circuitry may include implementations, where the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include implementations, where the calibration engine outputs a current provided to the series, where the output current can be based at least on a calibrated frequency.

An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

In a first aspect, the disclosure provides an apparatus (412a) for wireless communication, comprising: a first clock loop (420) comprising a first plurality of latches (422, 424) that generate a first plurality of clock signals (I, Q) having a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) having a corresponding second plurality of phases, where the first clock loop is configured to be enabled or disabled based on the first enable signal and the second clock loop is configured to be enabled or disabled based on the second enable signal. And wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

The present invention suppresses an increase in the number of state transitions during a counting period. The photoelectric detection device includes: light receiving units arranged in a matrix in a row direction and a column direction and outputting pulses generated in response to incidence of photons; and a counting circuit that counts the pulses output from the light receiving unit. The counting circuit includes a plurality of 2-bit Johnson counters that cause a state transition based on a transition input. And the second bit of the counting output of the front-stage 2-bit Johnson counter is used as the conversion input of the rear-stage 2-bit Johnson counter. Each 2-bit Johnson counter includes flip-flops connected in two stages, and in each of the plurality of 2-bit Johnson counters, an inverted value of an output of a latter stage flip-flop may be used as an input of a preceding stage flip-flop.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

To provide a semiconductor integrated circuit and a semiconductor device capable of suitably generating a gray code.SOLUTION: A clock signal is input to clock terminals of a first FF and a second FF. A first signal output from a Q terminal of the first FF is input to a D terminal of the second FF. A first inverter performs an inversion operation on a second signal output from the Q terminal of the second FF. The signal output from the first inverter is input to the D terminal of the first FF. A second inverter performs an inversion operation on the first signal. Each of (L-1) adders calculates a different bit of the gray code by addition based on a carry signal. A circuit block generates the carry signal of a first adder on the basis of an AND operation of the first signal and the second signal. The circuit block generates the carry signals of a second adder to an (L-1)th adder on the basis of the second signal and the signal output by the second inverter.SELECTED DRAWING: Figure 1

An aspect of the disclosure relates to a ring oscillator (RO) divider configured to divide an input clock by a programmable division ratio to generate an output clock. In this regard, the RO divider receives an input clock and, in response to the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time and outputs a second clock from an output of one stage of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another aspect, each stage includes two PMOS FETs and one NMOS FET.

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

To solve the problem that the duty ratio of a clock signal with an odd frequency division ratio cannot be adjusted to 50%.SOLUTION: A divider circuit comprises: an internal clock generation circuit that is connected with first to n-th (n is an integer of 2 or more) flip flop circuits, and divides an input clock signal by (2n-1) to generate a first internal clock signal; an edge timing generation circuit that, on the basis of the input clock signal, generates a second internal clock signal having a rising edge at a timing delayed by ((2n-1) / 2) of the period of the input clock signal from a rising edge of the first internal clock signal; and an RS latch circuit that has a reset terminal to which the first internal clock signal is input, and a set terminal to which the second internal clock signal is input.SELECTED DRAWING: Figure 1

In a clock domain crossover scenario, a flip-flop synchronizer features a reduced number of series-connected flip-flops (110, 113), receiving input data (A_q) from a first clock domain (107) and outputting data (120) from the second clock domain (114). The second clock signal has a variable frequency tuned to a target frequency by a division factor (k0). The flip-flops (110, 113) are clocked by a clock signal (CLK_k) that downsamples the second clock signal (CLK_B) by a factor of k1. The downsampled clock signal is generated by a frequency divider (301) that propagates a pulse of the signal (CLK_B) every k1 clock pulses, keeping the edges aligned. Theoretically, additional flip-flops (111, 112) are avoided.

The present technology allows for stable operation with respect to fluctuations in power supply voltage.　The present technology provides, among other things, a frequency divider circuit comprising at least: a plurality of input terminals, a plurality of output terminals, a first inverter circuit, a second inverter circuit, a third inverter circuit, a fourth inverter circuit, a first latch circuit, a second latch circuit, and a current-controlled bias circuit, wherein the plurality of input terminals, the first to fourth inverter circuits, the first and second latch circuits, and the plurality of output terminals are connected, and the current-controlled bias circuit is connected to the first and second latch circuits and controls a current flowing to a transistor included in each of the first and second latch circuits.

The present description relates to a frequency divider circuit comprising a first latch, a first output amplifier having at least one input coupled to at least one output of the first latch, a second latch having at least one input coupled to at least one output of the first output amplifier, and a second output amplifier having at least one input coupled to at least one output of the second latch, and having at least one output coupled to an input of the first latch.

Systems and methods for synchronizing multiple of output clocks. The system includes: a plurality of frequency dividers configured to receive a plurality of input clock signals and produce a plurality of output clock signals, wherein each of the plurality of output clock signals are lower in frequency than a corresponding input clock signal; and a circuit. The circuit is configured to: compare a first output clock signal of the plurality of output clock signals to a second output clock signal of the plurality of output clock signals to determine whether the first output clock signal is synchronized with the second output clock signal, generate a slip signal in response to determining that the first output clock signal is not synchronized with the second output clock signal, and apply the slip signal to the second output clock signal to synchronize the second output clock signal with the first output clock signal.

The present invention provides a device, a method and an electronic system for controlling an internal reset signal. The internal reset signal is synchronized with a clock signal. The device includes a clock switching circuit and a plurality of DFFs serially coupled. The clock switching circuit receives the clock signal and is configured to output the clock signal in an on state and block the clock signal in an off state. The plurality of DFFs are coupled to the clock switching circuit and driven by the clock signal. The plurality of DFFs are configured to enable the internal reset signal in response to the external reset signal being enabled, and disable the internal reset signal after a predetermined number of clock signal cycles after the external reset signal is disabled. The present invention can synchronize the internal reset signal with the clock signal and avoid the metastability problem between different transmitter paths.

A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock receiving circuit, configured to receive an initial clock signal and perform frequency division processing on the initial clock signal to obtain a first clock signal; a sampling and logic circuit, configured to perform two-stage sampling processing and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a chip select clock signal, where the chip select clock signal includes two pulses, and the width of each pulse is a preset clock cycle; and a decoding circuit, configured to perform decoding processing and sampling processing on the to-be-processed command signal according to the to-be-processed chip select signal and the chip select clock signal to obtain a target command signal.

A synchronizer with flip-flops has a reduced number of flip-flops coupled in series, receiving as an input data of a first clock domain and supplying as an output data in the second clock domain. The second clock signal is at a variable frequency adjusted to a target frequency, by a division factor. The flip-flops are timed by a clock signal subsampling the second clock signal by a factor k1. The subsampled clock signal is generated by a frequency divider propagating a pulse of the signal every k1 clock pulses, while keeping the edges aligned.

A multi-bit binary counter outputs a predetermined binary number of bits reflecting a number of times of triggering an input pin, and providing a binary counter output having a decimal equivalent. A multi-bit binary counter is implemented as a multi-bit synchronous counter IC chip with a ripple carry-out pin and loading functionality. An active output count indication pin is connected to cause the IC to transition states, such as from a HIGH state to a LOW state, when the counter output's decimal equivalent exceeds single-digit numbers. In one configuration, the counter functions selectively as a MOD-10 (decade) or MOD-16 binary counter.

The application relates to a random clock generation method and device against side channel attacks, wherein the method comprises the following steps: S1, selecting a reference clock as an input clock of a first round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; S2, randomly selecting a frequency multiplication clock from the frequency multiplication clocks, performing spur filtering, and then outputting the frequency multiplication clock as a system clock; S3, performing multi-path frequency division on the randomly selected frequency multiplication clock to obtain frequency division clocks with different frequency division coefficients; S4, randomly selecting a frequency division clock from the frequency division clocks, and performing multi-path frequency multiplication on the frequency division clock as an input clock of a next round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; and S5, repeating steps S2 to S4, and obtaining a system clock with various and random frequencies through multiple rounds of iteration. The application effectively improves the side channel attack protection effect.

The application relates to a programmable frequency divider and a phase-locked loop, the programmable frequency divider comprising a plurality of cascaded subtractors, a period end detection module and a delay reset circuit, wherein the plurality of cascaded subtractors are connected to corresponding initial value signals, under the triggering of a clock signal to be divided, the signals output by the plurality of cascaded subtractors correspond to the output results of decrement, and under the condition that the signals output by the plurality of cascaded subtractors reach a period end condition, the period end detection module outputs a period end signal to the delay reset circuit based on the signals output by the plurality of cascaded subtractors and the period end condition. Under the condition that the delay reset circuit receives the period end signal, a reset trigger signal is output to each subtractor so as to reset each subtractor. After a preset delay time length of the delay reset circuit after the reset trigger signal, a work trigger signal is output to each subtractor so as to make each subtractor work and enter the next round of decrement cycle operation.

In some implementations, a circuitry may include a series of symmetrical stages with an initial stage in the series coupled to an input signal having a first plurality of phases and an output stage in the series coupling an output signal comprising a second plurality of phases to a calibration engine, where a quantity of the phases in the output signal is increased based at least on a quantity of the symmetrical stages and a quantity of the first plurality of the phases in the input signal. In addition, the circuitry may include implementations, where the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include implementations, where the calibration engine outputs a current provided to the series, where the output current can be based at least on a calibrated frequency.

A code generator is disclosed, including: an asynchronous counter including a first flip-flop to an m-th flip-flop, the first flip-flop to the m-th flip-flop being configured to asynchronously output a first output signal to an m-th output signal respectively corresponding to a first bit to an m-th bit (m is an integer greater than or equal to 2) of a code in response to a first clock signal; and a synchronous counter including an (m + 1)-th flip-flop to an (m + n)-th flip-flop, the (m + 1)-th flip-flop to the (m + n)-th flip-flop being configured to synchronously output an (m + 1)-th output signal to an (m + n)-th output signal corresponding to the (m + 1)-th bit to the (m + n)-th bit (n is an integer greater than or equal to 2) of the code in response to the first clock signal. The asynchronous counter further includes: a first delay circuit to an m-th delay circuit, configured to respectively delay the first output signal to the m-th output signal such that when the (m + 1)-th bit to the (m + n)-th bit are output, the first bit to the m-th bit of the code are output together simultaneously.

A semiconductor device includes a pulse input circuit including flip-flops constituting each of two front-stage counters having different holding states from each other and configured such that first pulses from an even-stage ring circuit are input to each of the two front-stage counters, an edge detection circuit configured to detect edges of outputs of the two front-stage counters and output a second pulse having a predetermined pulse width larger than a predetermined value based on the edge, and a counter circuit including a rear-stage counter to which the second pulse is input. The edge detection circuit is configured to output the second pulse or a stepwise signal when a pulse width of the first pulse is smaller than the predetermined value.

An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

To provide an integral A / D converter in which a phase division circuit for generating a high-speed signal by appropriately combining a counter code signal is disposed at an appropriate interval and locally in a column, and which is capable of operating faster than a frequency of the counter code signal.SOLUTION: An integral A / D converter comprises a global counter which outputs a counter code signal including a multi-phase signal. The integral A / D converter also comprises: a ramp wave generation circuit which outputs a ramp wave voltage; a comparator which compares the ramp wave voltage with a pixel voltage; and a column circuit including a latch circuit which latches the counter code signal in output inversion timing of the comparator. For each column circuit, a latch circuit output value is defined as a digital conversion output value. A phase division circuit is further provided for outputting a phase division signal dividing a phase of the counter code signal to the latch circuit as an LSB of the digital conversion output value of the integral A / D converter. The phase division circuits are disposed with respect to a plurality of column circuits and the LSB is shared by a plurality of phase division circuits.SELECTED DRAWING: Figure 2

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

To provide a processing circuit that enables a repeated calculation using a logic circuit and holding of the results of the calculation.SOLUTION: A processing circuit 11 includes a control circuit 13 configured to receive at least one operation instruction signal SCNT and a base clock Clock, and to generate a write enable signal WE and a read enable signal RE in response to the base clock Clock and the operation instruction signal SCNT, a memory 15 capable of operating in synchronization with a multiplied clock Clk which is a multiplied base clock Clock, and an arithmetic circuit 17 configured to perform an operation on read data DRT received from the memory 15 using a dedicated hardware logic circuit to generate write data, and the memory 15 is configured to read a memory area 25 identified by an address and including at least one memory element in response to the read enable signal RE, and to write write data DWT to the memory area 25 in response to the write enable signal WE.SELECTED DRAWING: Figure 1

The embodiment of the present disclosure provides a counting circuit, comprising: a clock source, a clock control unit and N output units; wherein N is a positive integer. The clock control unit generates a clock control signal according to a clock signal output by the received clock source and output values of the first output unit to the Mth output unit, and outputs the clock control signal to clock input ends of the M+1th output unit to the Nth output unit, wherein the clock control signal has a first signal value and a second signal value with different signal values. The M+1th output unit to the Nth output unit latch when the received clock control signal switches from the second signal value to the first signal value; and keep the current state value unchanged when the received clock control signal is the second signal value.