6results about "Counting chain synchronous pulse counters" patented technology

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

The application relates to a random clock generation method and device against side channel attacks, wherein the method comprises the following steps: S1, selecting a reference clock as an input clock of a first round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; S2, randomly selecting a frequency multiplication clock from the frequency multiplication clocks, performing spur filtering, and then outputting the frequency multiplication clock as a system clock; S3, performing multi-path frequency division on the randomly selected frequency multiplication clock to obtain frequency division clocks with different frequency division coefficients; S4, randomly selecting a frequency division clock from the frequency division clocks, and performing multi-path frequency multiplication on the frequency division clock as an input clock of a next round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; and S5, repeating steps S2 to S4, and obtaining a system clock with various and random frequencies through multiple rounds of iteration. The application effectively improves the side channel attack protection effect.

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

A pulse signal output circuit capable of stable operation and a shift resistor including the same. One of the objectives is to provide [a service / product]. [Solution] A pulse signal output circuit according to one aspect of the disclosed invention includes a node connected to the output terminal. The channel length of the transistors that make up the system is the channel length of the transistor that functions as the output terminal. Make it larger than the length of the loop. This will suppress current leakage from the node and prevent leakage over a long period of time. This makes it possible to maintain a stable potential over a long period, preventing malfunctions in the pulse signal output circuit. It can be stopped.

The embodiment of the present application provides a kind of counter, comprising: counting module, including multiple cascaded sub-counters and the delay unit being connected between at least two adjacent sub-counters in multiple sub-counters;Wherein, sub-counter is used to count the number of clock pulses to output count output signal and carry output signal;Delay unit is used to receive the carry output signal of the previous stage sub-counter in at least two sub-counters, and the received carry output signal is output to the next stage sub-counter after being delayed;Data alignment module is used to receive the count output signal of multiple sub-counters, and the received multiple count output signals belonging to the same counting period are data-aligned according to the relationship corresponding to the delay time caused by delay unit, to output count result.

The objective is to provide a clock modulation circuit that can measure the characteristics of a clock with greater precision. [Solution] The clock modulation circuit of the embodiment includes a clock output circuit, a multiple frequency divider circuit that receives a clock from the clock output circuit and has a plurality of frequency divider circuits that divide the clock, and a frequency divider control circuit that controls the timing of the start of frequency division for each of the plurality of frequency divider circuits and controls the phase difference between at least one pair of output signals of the plurality of frequency divider circuits based on the period of the clock.