48results about "Counting chain synchronous pulse counters" patented technology

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

In a first aspect, the disclosure provides an apparatus (412a) for wireless communication, comprising: a first clock loop (420) comprising a first plurality of latches (422, 424) that generate a first plurality of clock signals (I, Q) having a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) having a corresponding second plurality of phases, where the first clock loop is configured to be enabled or disabled based on the first enable signal and the second clock loop is configured to be enabled or disabled based on the second enable signal. And wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

The present invention suppresses an increase in the number of state transitions during a counting period. The photoelectric detection device includes: light receiving units arranged in a matrix in a row direction and a column direction and outputting pulses generated in response to incidence of photons; and a counting circuit that counts the pulses output from the light receiving unit. The counting circuit includes a plurality of 2-bit Johnson counters that cause a state transition based on a transition input. And the second bit of the counting output of the front-stage 2-bit Johnson counter is used as the conversion input of the rear-stage 2-bit Johnson counter. Each 2-bit Johnson counter includes flip-flops connected in two stages, and in each of the plurality of 2-bit Johnson counters, an inverted value of an output of a latter stage flip-flop may be used as an input of a preceding stage flip-flop.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

To solve the problem that the duty ratio of a clock signal with an odd frequency division ratio cannot be adjusted to 50%.SOLUTION: A divider circuit comprises: an internal clock generation circuit that is connected with first to n-th (n is an integer of 2 or more) flip flop circuits, and divides an input clock signal by (2n-1) to generate a first internal clock signal; an edge timing generation circuit that, on the basis of the input clock signal, generates a second internal clock signal having a rising edge at a timing delayed by ((2n-1) / 2) of the period of the input clock signal from a rising edge of the first internal clock signal; and an RS latch circuit that has a reset terminal to which the first internal clock signal is input, and a set terminal to which the second internal clock signal is input.SELECTED DRAWING: Figure 1

In a clock domain crossover scenario, a flip-flop synchronizer features a reduced number of series-connected flip-flops (110, 113), receiving input data (A_q) from a first clock domain (107) and outputting data (120) from the second clock domain (114). The second clock signal has a variable frequency tuned to a target frequency by a division factor (k0). The flip-flops (110, 113) are clocked by a clock signal (CLK_k) that downsamples the second clock signal (CLK_B) by a factor of k1. The downsampled clock signal is generated by a frequency divider (301) that propagates a pulse of the signal (CLK_B) every k1 clock pulses, keeping the edges aligned. Theoretically, additional flip-flops (111, 112) are avoided.

Systems and methods for synchronizing multiple of output clocks. The system includes: a plurality of frequency dividers configured to receive a plurality of input clock signals and produce a plurality of output clock signals, wherein each of the plurality of output clock signals are lower in frequency than a corresponding input clock signal; and a circuit. The circuit is configured to: compare a first output clock signal of the plurality of output clock signals to a second output clock signal of the plurality of output clock signals to determine whether the first output clock signal is synchronized with the second output clock signal, generate a slip signal in response to determining that the first output clock signal is not synchronized with the second output clock signal, and apply the slip signal to the second output clock signal to synchronize the second output clock signal with the first output clock signal.

The present invention provides a device, a method and an electronic system for controlling an internal reset signal. The internal reset signal is synchronized with a clock signal. The device includes a clock switching circuit and a plurality of DFFs serially coupled. The clock switching circuit receives the clock signal and is configured to output the clock signal in an on state and block the clock signal in an off state. The plurality of DFFs are coupled to the clock switching circuit and driven by the clock signal. The plurality of DFFs are configured to enable the internal reset signal in response to the external reset signal being enabled, and disable the internal reset signal after a predetermined number of clock signal cycles after the external reset signal is disabled. The present invention can synchronize the internal reset signal with the clock signal and avoid the metastability problem between different transmitter paths.

A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock receiving circuit, configured to receive an initial clock signal and perform frequency division processing on the initial clock signal to obtain a first clock signal; a sampling and logic circuit, configured to perform two-stage sampling processing and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a chip select clock signal, where the chip select clock signal includes two pulses, and the width of each pulse is a preset clock cycle; and a decoding circuit, configured to perform decoding processing and sampling processing on the to-be-processed command signal according to the to-be-processed chip select signal and the chip select clock signal to obtain a target command signal.

A synchronizer with flip-flops has a reduced number of flip-flops coupled in series, receiving as an input data of a first clock domain and supplying as an output data in the second clock domain. The second clock signal is at a variable frequency adjusted to a target frequency, by a division factor. The flip-flops are timed by a clock signal subsampling the second clock signal by a factor k1. The subsampled clock signal is generated by a frequency divider propagating a pulse of the signal every k1 clock pulses, while keeping the edges aligned.

A multi-bit binary counter outputs a predetermined binary number of bits reflecting a number of times of triggering an input pin, and providing a binary counter output having a decimal equivalent. A multi-bit binary counter is implemented as a multi-bit synchronous counter IC chip with a ripple carry-out pin and loading functionality. An active output count indication pin is connected to cause the IC to transition states, such as from a HIGH state to a LOW state, when the counter output's decimal equivalent exceeds single-digit numbers. In one configuration, the counter functions selectively as a MOD-10 (decade) or MOD-16 binary counter.

The application relates to a random clock generation method and device against side channel attacks, wherein the method comprises the following steps: S1, selecting a reference clock as an input clock of a first round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; S2, randomly selecting a frequency multiplication clock from the frequency multiplication clocks, performing spur filtering, and then outputting the frequency multiplication clock as a system clock; S3, performing multi-path frequency division on the randomly selected frequency multiplication clock to obtain frequency division clocks with different frequency division coefficients; S4, randomly selecting a frequency division clock from the frequency division clocks, and performing multi-path frequency multiplication on the frequency division clock as an input clock of a next round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; and S5, repeating steps S2 to S4, and obtaining a system clock with various and random frequencies through multiple rounds of iteration. The application effectively improves the side channel attack protection effect.

The application relates to a programmable frequency divider and a phase-locked loop, the programmable frequency divider comprising a plurality of cascaded subtractors, a period end detection module and a delay reset circuit, wherein the plurality of cascaded subtractors are connected to corresponding initial value signals, under the triggering of a clock signal to be divided, the signals output by the plurality of cascaded subtractors correspond to the output results of decrement, and under the condition that the signals output by the plurality of cascaded subtractors reach a period end condition, the period end detection module outputs a period end signal to the delay reset circuit based on the signals output by the plurality of cascaded subtractors and the period end condition. Under the condition that the delay reset circuit receives the period end signal, a reset trigger signal is output to each subtractor so as to reset each subtractor. After a preset delay time length of the delay reset circuit after the reset trigger signal, a work trigger signal is output to each subtractor so as to make each subtractor work and enter the next round of decrement cycle operation.

A code generator is disclosed, including: an asynchronous counter including a first flip-flop to an m-th flip-flop, the first flip-flop to the m-th flip-flop being configured to asynchronously output a first output signal to an m-th output signal respectively corresponding to a first bit to an m-th bit (m is an integer greater than or equal to 2) of a code in response to a first clock signal; and a synchronous counter including an (m + 1)-th flip-flop to an (m + n)-th flip-flop, the (m + 1)-th flip-flop to the (m + n)-th flip-flop being configured to synchronously output an (m + 1)-th output signal to an (m + n)-th output signal corresponding to the (m + 1)-th bit to the (m + n)-th bit (n is an integer greater than or equal to 2) of the code in response to the first clock signal. The asynchronous counter further includes: a first delay circuit to an m-th delay circuit, configured to respectively delay the first output signal to the m-th output signal such that when the (m + 1)-th bit to the (m + n)-th bit are output, the first bit to the m-th bit of the code are output together simultaneously.

A semiconductor device includes a pulse input circuit including flip-flops constituting each of two front-stage counters having different holding states from each other and configured such that first pulses from an even-stage ring circuit are input to each of the two front-stage counters, an edge detection circuit configured to detect edges of outputs of the two front-stage counters and output a second pulse having a predetermined pulse width larger than a predetermined value based on the edge, and a counter circuit including a rear-stage counter to which the second pulse is input. The edge detection circuit is configured to output the second pulse or a stepwise signal when a pulse width of the first pulse is smaller than the predetermined value.

An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

The embodiment of the present disclosure provides a counting circuit, comprising: a clock source, a clock control unit and N output units; wherein N is a positive integer. The clock control unit generates a clock control signal according to a clock signal output by the received clock source and output values of the first output unit to the Mth output unit, and outputs the clock control signal to clock input ends of the M+1th output unit to the Nth output unit, wherein the clock control signal has a first signal value and a second signal value with different signal values. The M+1th output unit to the Nth output unit latch when the received clock control signal switches from the second signal value to the first signal value; and keep the current state value unchanged when the received clock control signal is the second signal value.

The invention relates to a frequency modulation synchronizer for clock domain crossing. A synchronizer with flip-flops has a reduced number of flip-flops coupled in series that receive data of a first clock domain as an input and provide data in a second clock domain as an output. The second clock signal is at a variable frequency that is adjusted to a target frequency by a frequency division factor. The flip-flop is clocked by a clock signal subsampled by a factor k1 on the second clock signal. The sub-sampled clock signal is generated by a frequency divider that propagates one pulse of the signal per k1 clock pulses while maintaining edge alignment.

Systems, devices, and methods related to frequency converter arrangements are provided. For example, a frequency converter arrangement converts a first signal centered at a first frequency to a second signal centered at a second frequency different from the first frequency. The frequency converter arrangement includes local oscillator (LO) circuitry and in-phase, quadrature-phase (IQ) mixer circuitry coupled to the LO circuitry. The LO circuitry includes duty cycle correction circuitry to adjust a duty cycle of a pair of input clock signals. The duty cycle correction circuitry includes coarse tuning circuitry responsive to a digital calibration code, and analog tuning loop circuitry. The LO circuitry further includes quadrature divider circuitry coupled to an output of the duty cycle correction circuitry, where the quadrature divider circuitry generates an in-phase LO signal and a quadrature-phase LO signal from a pair of output clock signals at outputs of the duty cycle correction circuitry.

Aspects of the subject disclosure may include, for example, an inner clock generation circuit, including: a selectable frequency divider having: a ring of tri-state inverters; a reset gate on an output of each tri-state inverter in the ring; and a reset circuit comprising one or more selectable flip-flops; and a duty-cycle limiter that generates clock signals having a 25% duty cycle from three out of four quadrature clock signals. Other embodiments are disclosed.

To provide, among others, a pulse signal output circuit capable of operating stably, and a shift register including the pulse signal output circuit.SOLUTION: In an embodiment of the pulse signal output circuit, the channel length of a transistor forming a node connecting to an output terminal is longer than the channel length of a transistor functioning as an output terminal. Thereby, the amount of a leakage current from the node can be reduced, and the potential can be kept stably for a long period of time, so that a malfunction of the pulse signal output circuit can be prevented.SELECTED DRAWING: Figure 1

A semiconductor device comprising: a first circuit (10_2); and a second circuit (10_3) adjacent to the first circuit (10_2), wherein the first circuit (10_2) comprises a first to fifth transistor, wherein the second circuit (10_3) comprises a sixth to tenth transistor, wherein one of a source and a drain of the first transistor (103) is directly connected to a first clock line (21), wherein the other of the source and the drain of the first transistor (103) is directly connected to a first wiring (27) configured to output a signal, wherein one of a source and a drain of the second transistor (104) is directly connected to a first power supply line (31), the other of the source and drain of the second transistor (104) being directly connected to the first wiring (27), wherein one of a source and a drain of the third transistor (108) is directly connected to a gate of the second transistor (104), wherein the other of the source and drain of the third transistor (108) is directly connected to a second power supply line (32), wherein a gate of the third transistor (108) is directly connected to a second clock line (22), wherein one of a source and a drain of the fourth transistor (107) is directly connected to a gate of the first transistor (103), wherein a gate of the fourth transistor (107) is directly connected to the second power supply line (32), wherein one of a source and a drain of the fifth transistor (106) is directly connected to the first power supply line (31), wherein a gate of the fifth transistor (106) is directly connected to the gate of the second transistor (104), wherein one of a source and a drain of the sixth transistor is directly connected to the second clock line (22), wherein the other of the source and the drain of the sixth transistor is directly connected to a second wiring configured to output a signal, wherein one of a source and a drain of the seventh transistor is directly connected to the first power supply line (31), the other of the source and drain of the seventh transistor being directly connected to the second wiring, wherein one of a source and a drain of the eighth transistor is directly connected to a gate of the seventh transistor, the other of the source and drain of the eighth transistor being directly connected to the second power supply line (32), wherein one of a source and a drain of the ninth transistor is directly connected to a gate of the sixth transistor, wherein a gate of the ninth transistor is directly connected to the second power supply line (32), wherein one of a source and a drain of the tenth transistor is directly connected to the first power supply line (31), wherein a gate of the tenth transistor is directly connected to the gate of the seventh transistor, wherein a potential of the first power supply line (31) is supplied to the other of the source and the drain of the fourth transistor (107) at least through a channel formation region of the fifth transistor (106) when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the fourth transistor (107) at least through the channel formation region of the fifth transistor (106), wherein the potential of the first power supply line (31) is supplied to the other of the source and the drain of the ninth transistor at least through a channel formation region of the tenth transistor when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the ninth transistor at least through the channel formation region of the tenth transistor, and wherein the eighth transistor is configured to control a timing when a potential of the second power supply line (32) is supplied to the gate of the seventh transistor and the gate of the tenth transistor at least through a channel formation region of the eighth transistor.

Aspects of the subject disclosure may include, for example, a track-and-hold sampling circuit, having: a duty-cycle limiter that generates a clock signal having a duty cycle that is less than 100% from three out of four clock signals; and a sampling circuit comprising complementary positive and negative input gates that track and sample data input signals, wherein the sampling circuit generates sampled data signals, wherein the complementary positive and negative input gates are coupled to the clock signal. Other embodiments are disclosed.

A pulse signal output circuit capable of stable operation and a shift resistor including the same. One of the objectives is to provide [a service / product]. [Solution] A pulse signal output circuit according to one aspect of the disclosed invention includes a node connected to the output terminal. The channel length of the transistors that make up the system is the channel length of the transistor that functions as the output terminal. Make it larger than the length of the loop. This will suppress current leakage from the node and prevent leakage over a long period of time. This makes it possible to maintain a stable potential over a long period, preventing malfunctions in the pulse signal output circuit. It can be stopped.

Frequency Divider This description relates to a frequency divider (300), comprising at least two flip-flops (302, 304) and in which a pull-up current (Itail) of each flip-flop is controlled by a reference current (IDAC). Figure for the abbreviation: Fig. 3

Reduce power consumption in semiconductor devices. The semiconductor device includes a latch circuit composed of dynamic circuitry. The latch circuit includes a first circuit with decoding functionality, multiple capacitors, multiple clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. During a first clock signal of "H", the potential of the first capacitor is refreshed according to the decoding result of the first circuit. During a second clock signal of "H", the potential of the second capacitor is refreshed according to the potential of the first capacitor, and the first output terminal receives the potential of the second capacitor as a first output signal. During a third clock signal of "H", the potential of the third capacitor is refreshed according to the potential of the second capacitor, and the second output terminal receives the potential of the third capacitor as a second output signal.

This disclosure provides in a first aspect, an apparatus (412a) for wireless communications including a first clock loop (420) comprising a first plurality of latches (422, 424) generating a first plurality of clock signals (I, Q) with a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) with a corresponding second plurality of phases, wherein the first clock loop is configured to be enabled or disabled based on a first enable signal, and wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).