15results about "Continuously circulated pulse counters" patented technology

In a first aspect, the disclosure provides an apparatus (412a) for wireless communication, comprising: a first clock loop (420) comprising a first plurality of latches (422, 424) that generate a first plurality of clock signals (I, Q) having a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) having a corresponding second plurality of phases, where the first clock loop is configured to be enabled or disabled based on the first enable signal and the second clock loop is configured to be enabled or disabled based on the second enable signal. And wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

The present invention suppresses an increase in the number of state transitions during a counting period. The photoelectric detection device includes: light receiving units arranged in a matrix in a row direction and a column direction and outputting pulses generated in response to incidence of photons; and a counting circuit that counts the pulses output from the light receiving unit. The counting circuit includes a plurality of 2-bit Johnson counters that cause a state transition based on a transition input. And the second bit of the counting output of the front-stage 2-bit Johnson counter is used as the conversion input of the rear-stage 2-bit Johnson counter. Each 2-bit Johnson counter includes flip-flops connected in two stages, and in each of the plurality of 2-bit Johnson counters, an inverted value of an output of a latter stage flip-flop may be used as an input of a preceding stage flip-flop.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

An aspect of the disclosure relates to a ring oscillator (RO) divider configured to divide an input clock by a programmable division ratio to generate an output clock. In this regard, the RO divider receives an input clock and, in response to the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time and outputs a second clock from an output of one stage of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another aspect, each stage includes two PMOS FETs and one NMOS FET.

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

The embodiment of the invention provides a frequency dividing circuit, a frequency dividing method and a chip. The frequency dividing circuit comprises a calculation circuit used for receiving a software frequency dividing coefficient and a hardware frequency dividing coefficient; determining a target frequency division coefficient according to the software frequency division coefficient and the hardware frequency division coefficient; determining a counting lower limit value and a counting upper limit value according to the target frequency division coefficient and the frequency division coefficient threshold value; sending the counting lower limit value and the counting upper limit value to a counting circuit; the counting circuit is used for receiving an initial clock signal, a counting lower limit value and a counting upper limit value; counting in a counting range represented by the counting lower limit value and the counting upper limit value according to the initial clock signal to obtain a counting signal; and outputting the highest bit of the counting signal as a first frequency division signal.

A semiconductor device includes a pulse input circuit including flip-flops constituting each of two front-stage counters having different holding states from each other and configured such that first pulses from an even-stage ring circuit are input to each of the two front-stage counters, an edge detection circuit configured to detect edges of outputs of the two front-stage counters and output a second pulse having a predetermined pulse width larger than a predetermined value based on the edge, and a counter circuit including a rear-stage counter to which the second pulse is input. The edge detection circuit is configured to output the second pulse or a stepwise signal when a pulse width of the first pulse is smaller than the predetermined value.

A high frequency electromagnetic radiation generation device is disclosed that includes a high voltage input, a nonlinear transmission line, an antenna, and a pulse recirculating circuit. In some embodiments, the high voltage input may be configured to receive electrical pulses having a first peak voltage that is greater than 5 kV, and / or may be electrically coupled with the nonlinear transmission line. The antenna may be electrically coupled with the nonlinear transmission line and / or may radiate electromagnetic radiation at a frequency greater than 100 MHz about a voltage greater than 5 kV. The pulse recirculating may be electrically coupled with the high voltage input and the antenna. The pulse recirculating circuit may include a diode; a low pass filter; and a delay line. In some embodiments, unradiated energy from the antenna is directed through the pulse recirculating circuit to the nonlinear transmission line with a delay of less than 100 ns.

The invention discloses a coding and decoding system and a coding circuit and a decoding circuit thereof, and the coding and decoding system comprises a minimum change code generating circuit, a mark generating circuit and a decoding circuit. The least variation code generating circuit is used for generating a digital code. The flag generating circuit is coupled to the minimum change code generating circuit and is used for generating a flag according to the digital code. The decoding circuit is used for decoding the digital code according to a preset value and the mark so as to generate an output value.

A method performed by a first network entity (121, 131) for authenticating an event in a communications network (101, 102, 103, 104) is provided. The first network entity (121, 131) is configured to receive an event signal. The first network entity (121, 131) is also configured to authenticate the event if the received event signal correlates with an 5 output signal of a closed-loop shift register in the first network entity (121,131). Furthermore, the first network entity (121, 131) is configured to trigger a change in the closed-loop shift register in order to obtain a subsequent output signal from the closed-loop shift register. A first network entity (121, 131) for authenticating an event is also provided. Further, a wake-up receiver circuit (1210) comprising the first network entity 10 (121, 131) is provided, as well as, a wireless device (1200) comprising the wake-up receiver circuit (1210). Furthermore, a second network entity (110, 111, 112, 113) and a method therein for authenticating an event in at least one first network entity (121, 131) in a communications network (101, 102, 103, 104) are also provided. Also, a radio base station comprising the second network entity (110, 111, 112, 113) is provided, as well as, 15 computer programs and communications networks.

This disclosure provides in a first aspect, an apparatus (412a) for wireless communications including a first clock loop (420) comprising a first plurality of latches (422, 424) generating a first plurality of clock signals (I, Q) with a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) with a corresponding second plurality of phases, wherein the first clock loop is configured to be enabled or disabled based on a first enable signal, and wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

This invention discloses a frequency divider. The frequency divider includes at least two filtering units, with the first end of each filtering unit connected to the first end of the frequency divider, and the second end of each filtering unit serving as a second end of the frequency divider. Each filtering unit includes at least one inductor, and the signal transmission directions of adjacent inductors are opposite, which can reduce the mutual interference between the magnetic fields generated by adjacent inductors, thereby reducing the mutual interference between filtering units and improving the isolation between different channels of the frequency divider.

An apparatus (200), including: a clock source (210) configured to generate first and second clock signals based on an input clock signal (fin), wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer; and a logic circuit (230) configured to perform a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction.

A circuit for a divider or counter may include a frequency divider (200) having multiple rings (210, 220, 230) for dividing an input frequency (Vin, 202) to obtain an output frequency. The first and second rings (210, 220) may include an odd-numbered plurality of elements, such as inverters, wherein each inverter of a ring is coupled to another inverter of the ring in a circular chain. An input frequency (Vin, 202) may be input to a power supply input of inverters (212A- N) of the first ring (210). The second ring inverters (222A-N) may be coupled at a power supply input to output nodes of the first ring inverters, which results in the second ring operating at a divisional rate of the first frequency given by (N-l), where N is the number of inverters in the ring. The circuits may be used in frequency dividers and counters, such as in phase-locked loops (PLLs) and analog-to- digital converters (ADCs).