Idle percent adjustable N-time frequency division circuit of pulse mixing mode

A technology of pulse synthesis and frequency division circuit, applied in the direction of synchronous pulse counter, continuous cycle pulse counter, electrical components, etc., can solve the problem that it is difficult to achieve odd or arbitrary order, and achieve strong PVT change ability, strong resistance and stability Good results

Inactive Publication Date: 2007-12-12
NAT UNIV OF DEFENSE TECH
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  • Abstract
  • Description
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AI Technical Summary

Problems solved by technology

However, the above two methods are not easy to achieve odd or arbitrary times, and a frequency division circuit with adjustable duty cycle

Method used

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  • Idle percent adjustable N-time frequency division circuit of pulse mixing mode
  • Idle percent adjustable N-time frequency division circuit of pulse mixing mode

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Embodiment Construction

[0018] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0019] The invention adopts a dynamic edge trigger register, utilizes the phase difference of the clock signal to generate a double pulse signal with two positive edge / negative edge jumps every N input clock signal cycles, and uses the double pulse signal to obtain N times of frequency division output. As shown in Fig. 1 and Fig. 2, the duty cycle adjustable N times frequency division circuit of the pulse synthesis mode of the present invention comprises: the shift latch cascaded by N dynamic flip-flops in the pulse clock generating unit wherein N is the frequency division ratio of the input clock (10 stages in this embodiment), the control clocks of the odd-stage shift register and the even-stage shift register are reversely connected, and the output of the last stage shift register is passed through an inverted After the phase conve...

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Abstract

The invention discloses dutycycle adjustable N order frequency dividing circuit of pulse synthesizing method, which includes: generating unit of pulse clock which consists of shift register with cascaded N dynamic lock memorizers, and the N is the frequency dividing ratio of input clock, the control clock of odd shift register is connected with the control clock of even shift register reversely, and the output of the last shift register feeds back to the input end of first shift register by inverter; the synthesis unit of control clock consists of NOT-OR gate and three drive inverters; the synthesis unit of frequency dividing clock consists of two shift registers and the adjusting unit of input information, two shift registers controlled by reversed clock control form a dynamic trigger, and feeds back to input by inverter. The invention is dutycycle adjustable N order frequency dividing circuit of pulse synthesizing method with simple structure, adopting pulse synthesizing method, and the dutycycle adjustable random order frequency dividing.

Description

technical field [0001] The invention mainly relates to the field of frequency division circuits with CMOS transistors, in particular to a frequency division circuit with an adjustable duty ratio of N times in a pulse synthesis mode. Background technique [0002] In the high-speed serial bus, the serial / serial-parallel conversion circuit is an important part, which converts low-speed parallel data into high-speed serial data stream output, or receives high-speed serial data stream and converts low-speed parallel data. During the parallel / serial or serial / parallel conversion process, there is also a clock frequency conversion, and it is obvious that the ratio of the clock for N-bit parallel data transmission to the clock for serial data transmission is K=1 / N. [0003] Traditional frequency division circuits mostly use counters or shift feedback register chains. The principle of the counter method is simple, that is, the input clock edge is counted by the counting method, and ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K23/54H03L7/197
Inventor 陈吉华欧阳干李少青张民选赵振宇陈怒兴马剑武徐炜遐吴宏何小威刘征王建军邹金安雷建武郑东裕
Owner NAT UNIV OF DEFENSE TECH
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