Idle percent adjustable N-time frequency division circuit of pulse mixing mode

Abstract

The invention discloses dutycycle adjustable N order frequency dividing circuit of pulse synthesizing method, which includes: generating unit of pulse clock which consists of shift register with cascaded N dynamic lock memorizers, and the N is the frequency dividing ratio of input clock, the control clock of odd shift register is connected with the control clock of even shift register reversely, and the output of the last shift register feeds back to the input end of first shift register by inverter; the synthesis unit of control clock consists of NOT-OR gate and three drive inverters; the synthesis unit of frequency dividing clock consists of two shift registers and the adjusting unit of input information, two shift registers controlled by reversed clock control form a dynamic trigger, and feeds back to input by inverter. The invention is dutycycle adjustable N order frequency dividing circuit of pulse synthesizing method with simple structure, adopting pulse synthesizing method, and the dutycycle adjustable random order frequency dividing.

Description

technical field [0001] The invention mainly relates to the field of frequency division circuits with CMOS transistors, in particular to a frequency division circuit with an adjustable duty ratio of N times in a pulse synthesis mode. Background technique [0002] In the high-speed serial bus, the serial / serial-parallel conversion circuit is an important part, which converts low-speed parallel data into high-speed serial data stream output, or receives high-speed serial data stream and converts low-speed parallel data. During the parallel / serial or serial / parallel conversion process, there is also a clock frequency conversion, and it is obvious that the ratio of the clock for N-bit parallel data transmission to the clock for serial data transmission is K=1 / N. [0003] Traditional frequency division circuits mostly use counters or shift feedback register chains. The principle of the counter method is simple, that is, the input clock edge is counted by the counting method, and ...

AI Technical Summary

Problems solved by technology

However, the above two methods are not easy to achieve odd or arbitrary times, and a frequency division circuit with adjustable duty cycle

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