136 results about "Positive edge" patented technology

There is described a method as well as a device for motion detect ion in an optical sensing device, such as an optical mouse. A photodetector array comprising a plurality of pixels is used to detect successive light intensity patterns of an illuminated portion of a surface with respect to which a measurement of relative motion is to be determined. Light intensity between neighbouring pixels is compared in order to determine edge direction data descriptive of light intensity differences between the pixels, such data including (i) a first edge condition, or positive edge, defined as a condition wherein light intensity of a first pixel is less than light intensity of a second pixel, and (ii) a second edge condition, or negative edge, defined as a condition wherein light intensity of the first pixel is greater than light intensity of the second pixel. Through comparison of this edge direction data with edge direction data determined from a previous illumination (or by comparing data extracted from this edge direction data) a measurement of the relative motion of the optical sensing device with respect to the illuminated portion of the surface is determined.

The System-on-Chip apparatus and integration methodology disclosed includes a single semiconductor integrated circuit having one or more processor subsystems, one or more DMA-type peripherals, and a Memory Access Controller (MAC) on a first internal unidirectional bus. The first internal unidirectional bus controls transactions between the processor subsystem(s) and the DMA peripheral(s) using a Memory Access Controller (MAC) and unidirectional, positive-edge clocked address and transaction control signals. The first internal unidirectional bus can support burst operation, variable-speed pipelined memory transactions, and hidden arbitration. The SoC may include a second internal unidirectional bus that controls transactions between the processor subsystem(s) and non-DMA peripherals. The second internal unidirectional bus controls transactions between the processor subsystem(s) and the non-DMA peripheral(s) using unidirectional address and transaction control signals. Peripherals may be synchronous or asynchronous to their respective buses.

A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter.

Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captured data values are combined along with the data value captured by the previous negative edge to determine the data bit value. The captured data may be dynamically de-skewed previous to being clocked into a buffer based on the clock edges sampling the data.

A touch sensing system which includes a touch input interface and a capacitance sensing circuit is provided. The touch input interface includes a plurality of sensing capacitors which output at least one waveform under test and at least one reference waveform. The capacitance sensing circuit includes a difference comparing unit. The difference comparing unit receives the waveform under test and the reference waveform and outputs a differential signal according to at least one positive edge difference and at least one negative edge difference between the waveform under test and the reference waveform. Furthermore, a capacitance sensing method is also provided.

A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

A phase to digital converter for a digital PLL (Phase Locked Loop) provides an output in the same or single reference clock period for which it is digitizing the phase error information. The phase to digital converter operates on a positive edge of the reference clock and a digital filter operates on the negative edge of the reference clock so the phase correction performed by the PLL occurs in the same reference clock cycle in which the phase to digital converter is digitizing the phase error information.

The invention relates to a multipurpose sheet metal stamping die-set for positive edge pressing. An edge pressing mechanism is arranged above a concave template, and comprises an edge pressing plate and a power driving device; the edge pressing plate is movably connected to a support post and a guide post; the upper end face of the edge pressing plate is in fit connection with the power driving device which is provided with an edge pressing force sensor; and electrical control parts of the edge pressing force sensor and the power driving device are connected with a PLC control system through circuits. The multipurpose sheet metal stamping die-set has the advantages that: the structure is novel and simple; the performance of the die is greatly improved; the edge pressing mechanism is arranged positively; an inverse jacking device is arranged; independent hydraulic power system and electrical control part are arranged and are used for controlling the strokes of the edge pressing plate and an inverse jacking plate and the magnitude of the edge pressing force and the inverse jacking force; the edge pressing force and the inverse jacking force required can be constantly generated at specific positions of the stamping stroke and high accuracy requirement can be met; and when the upper die part works, the upper die part is wrapped by the lower die part, and the safety of the stamping is greatly improved.

The present invention provides a full-digital clock duty cycle correction circuit and a method thereof. The circuit comprises a sampling unit, a duty cycle correcting module, and a phase-lock module. The duty cycle correcting module produces a first clock signal according to an input clock signal. The phase-lock module produces a second clock signal according to the first clock signal and is used for aligning the positive edges of the clock signals. The duty cycle correcting module adjusts the pulse width of the first clock signal according to the clock signals. In addition, after the pulse width is adjusted, the positive edges of the clock signals are re-aligned. When the pulse width is not equal to zero, the pulse width is re-adjusted and the positive edges are re-aligned until the pulse widths of the clock signals are identical. Finally, the second clock signal is outputted and thus producing a clock signal having 50% duty cycle.

A positive counter starts counting, starting with an initial value, upon receiving a positive edge of a dimming pulse signal. A negative edge counter starts counting, starting with an initial value, upon receiving a negative edge of the dimming pulse signal. For each i-th (2≦i≦n) channel, the phase shift amount is calculated by multiplying a period count value that indicates the period of the dimming pulse signal by (i−1) / n. When the count value matches the phase shift amount, a burst control signal is switched to a first level. When the count value matches the phase shift amount, the burst control signal is switched to a second level.

The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal.

The invention discloses a three-phase alternating current phase sequence testing circuit. The three-phase alternating current phase sequence testing circuit comprises a waveform and amplitude shaping circuit capable of shaping the waveform of inputted alternating current, and a phase sequence testing circuit capable of carrying out the logic control on the time sequence. A three-phase switch impulse signal from a waveform transformation circuit transistor is respectively connected with two paralleled CLK terminals and reset terminals of a D-shaped positive edge trigger between the A, B, C three-phase waveform and amplitude shaping circuit and the phase sequence control circuit; and high levels or low levels outputted according to a time sequence cycle period are sent to a phase sequence judgment transistor of the phase sequence output control circuit. The three-phase alternating current phase sequence testing circuit can dynamically test the three-phase existence only through the paralleled D-shaped positive edge trigger outputting the switching impulse signal and the phase sequence judgment transistor, thereby preventing the harm to a tester or a product caused by an error phase sequence, and consequently solving the problems of phase sequence errors and phase deficiency when detecting a three-phase power supply.

A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead / lag indicator circuit that generates a lead / lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data.

The present invention's cutting tool coated using the PVD process can cut with high geometrical precision, produce a good machined surface, and cut for a prolonged time. Its substrate is composed of cemented carbide or cermet, has a surface roughness, Ra, of at most 0.3 mum, is structured by hard particles having an average particle diameter of 0.3 to 1.5 mum, and has a cutting part having a sharp positive edge. Its coating is formed over the substrate using the PVD process and comprises an inner layer and an outer layer. The total thickness of the inner and outer layers is at most 2.0 mum. The inner layer comprises (a) at least one of the 4a-, 5a-, 6a-group elements, Al, and Si and (b) at least one of carbon, nitrogen, and oxygen. The outer layer comprises (c) at least one of boron, silicon, carbon, and nitrogen and (d) Ti.

A method for reducing latency in conversions from a SMII (Serial Media Independent Interface) to a MII (Media Independent Interface). The method involves generating receive and transmit clock signals from a physical layer device; generating receive and transmit clock signals at a media access controller; and synchronizing the clock signals at the media access controller and the clock signals at the physical layer device such that MII clocks are generated from the SMII and a synchronization signal of the SMII is always delayed 8 nsec from a positive edge of the MII clock.

An apparatus and method of scanning a dual edge-triggered flip-flop with scan capability includes a first scan slave element capable of capturing data on a positive edge of a clock signal; and a second scan slave element capable of capturing data on a negative edge of the clock signal. An apparatus and method of scanning a dual edge-triggered flip-flop with scan capability includes a scan slave element capable of capturing data on either a positive edge or a negative edge of a clock signal; wherein a control signal determines whether the scan slave element captures data on the positive edge or negative edge of the clock signal.

The invention discloses a source electrode driven integrated circuit framework of display, comprising a shift cache for temporarily storing a data signal, a linear buffer coupled to the shift cache and used for latching the data signal, a standard potential shifter coupled to the linear buffer and used for lifting output electric potential, a digital analogue converter for converting data and analogue signal, an output buffer coupled to the digital analogue converter and outputting the converted data, and an output control circuit coupled to the output buffer. The output control circuit comprises a positive edge trigger flip-flop and a complementary metal-oxide semiconductor switch component, and can output an LP output signal to control the data signal output of the source electrode driven integrated circuit, so as to avoid the noise generated in the process of turning on a display.

The invention relates to a self-encoding neural network-based symbol diagram node classification method. The method includes the following steps that: S1, an adjacency matrix is constructed on the basis of a symbol diagram structure; S2, the representation vectors of symbol diagram nodes are learned on the basis of a self-encoding model, so that the representation vectors of two nodes connected bya positive edge are adjacent to each other, and the representation vectors of two nodes connected by a negative edge are far away from each other; S3, on the basis of the obtained node representationvectors, a small number of nodes with type tags are adopted to train a classifier; and S4, the trained classifier is utilized to predict the type of an unknown node, a node type is outputted, and therefore, the node can be classified according to the node type. Compared with the prior art, the method of the invention has the advantages of low computational complexity, fewer required training data, no need for retraining new nodes and the like.

A circuit with adjustable phase delay and a feedback voltage includes a delay setting unit and a phase delay signal generator. The delay setting unit generates a delay time according to an external resistor. The phase delay signal generator includes a plurality of phase delay units. Each phase delay unit includes an edge trigger subunit and a signal generation subunit. The edge trigger subunit receives an input signal, and generates a positive edge trigger signal and a negative edge trigger signal according to a positive edge and a negative edge of the input signal, respectively. The signal generation subunit generates and outputs a phase delay signal according to the positive edge trigger signal, the negative edge trigger signal, and the delay time. The phase delay signal lags the input signal for the delay time.

A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for ach transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Provided in the invention is a drive circuit for a thin-film transistor liquid crystal display. The drive circuit comprises a positive edge counter, a negative edge counter, a shift register, a pre-charging controller, and a lever shifter. To be specific, the positive edge counter is used for outputting a first control signal; the negative edge counter is used for outputting a second control signal; the shift register is used for receiving a gate starting signal and outputting a plurality of clock signals according to the first and second control signals; the pre-charging controller is used for outputting a pre-charging pulse width modulation signal; and the level shifter is used for carrying out a pre-charging operation on rising edges of at least parts of clock signals according to the pre-charging pulse width modulation signal. Compared with the prior art, the pre-charging controller outputs the pre-charging pulse width modulation signal; and thus the level shifter can carry out the pre-charging operation on rising edges of at least parts of clock signals. Therefore, the clock signals after pre charging can open the gate of the thin-film transistor in advance to charge a pixel, so that the pixel can be charged to an expected voltage potential rapidly; and thus the power consumption of the drive circuit can be reduced.

A fractional-N PLL synthesizer has an up-down counter counting up for positive edges of a frequency-divided signal produced by a frequency divider with a fractional divide ratio in a feedback path of the synthesizer and down for positive edges of a reference signal. A phase offset between portions of the synthesizer signal before and after a loss-of-lock interval is then assessed as a numerical value proportional to the product of the divide ratio and the cycle difference registered by the up-down counter (36) after the loss-of-lock interval. A correction term derived from the phase offset can be used in a signal processing device as employed, e.g., in a GNSS receiver, for producing, from an analog input signal, a phase-corrected baseband signal where portions of the signal before and after loss of lock are phase coherent.

The invention provides a digital logic circuit module with a reset and burr removing function. The digital logic circuit module comprises an input end rst_in, a negative edge burr removing unit, a positive edge burr removing unit, a testing mode selection unit, a stable reset generating output unit and an output end rst_out, wherein the positive edge burr removing unit comprises a second D triggerset and an AND gate, and when a middle reset signal por_with_pos_glitch is sent to the input end D of the first D trigger in the second D trigger set, under control of an input synchronous clock signal clk_in, output signals of the M D triggers in series connection are directly sent to the AND gate to conduct 'AND' operation to filter out positive edge burrs and negative edge burrs of a reset control signal PAD_RESETN. Besides, the digital logic circuit module supports a DFT test, and a testing mode control signal test_mode makes output rst_out of the digital logic circuit module equal to input rst_in to ensure that reset R of the digital logic circuit module is totally controllable.

The invention discloses a honeycomb material large entrance angle low damage processing cutter and a honeycomb material large entrance angle low damage processing method. The processing cutter comprises a toothed cutterhead and a cutter bar component, wherein the cutter tooth of the toothed cutterhead is provided with a primary cutting edge, a secondary cutting edge and a side edge. According to the invention, a circular disc type cutter is adopted to cut and process honeycomb material; the position relation between the cutter and a workpiece hole lattice is determined according to theoreticalcalculation, so that the range of the entrance angle theta at a single-layer hole wall is equal to or greater than 90 degrees and less than 165 degrees as much as possible during the machining process, and the surface burr is effectively reduced; and in addition, the processing cutter with a positive edge dip angle is utilized to move the position of an entry point inwards, so that hole wall tearing due to defect expansion is avoided, and low damage processing of the molded surface, the chamfer and the cutting side of the honeycomb material is realized. The processing cutter can effectively cut off the low-rigidity complicated hole wall structure in the honeycomb material surface and reduces the surface burr; and moreover, the cutting edge inclination angle of the primary cutting edge facilitates inward movement of the entry point position, so that longer hole wall tearing due to defect expansion is avoided.

A method and system for providing variable edge control of pulse waveforms is provided. A positive edge DAC number is set so that the positive edge time of a first pulse waveform of some amplitude is substantially equal to some initial edge time. Similarly, a second positive edge DAC number associated with a second pulse waveform of different amplitude is set so that the positive edge time of the second pulse waveform also equals the initial edge time. Positive gain and offset factors are then generated so that a third positive edge DAC number associated with any pulse waveform may be calculated so that a desired positive edge time of that waveform is produced. Negative edge DAC numbers may be calculated in a similar manner so that the positive and negative edge times of a pulse waveform may be balanced, or more efficient methods may be used.