141 results about "Media Independent Interface" patented technology

A SGMII that operates to transfer data between MAC and PHY chips at 2500/1000/100/10 Mbps utilizes a unique frame extending technique in one embodiment where frames having multiples of 2 and 3 data bytes are utilized to change the data transfer rate by multiples of 2.5. In another embodiment different clock signals are utilized.

A method of configuring system layers for a synchronous Ethernet is provided. In the method, a physical layer takes charge of input and output of an Ethernet frame in direct relation to hardware, an xMII (x Media Independent Interface) layer connects the physical layer to a data link layer. The data link layer has a sync frame processor for processing a synchronous frame and an async frame processor for processing an asynchronous frame. A parser and multiplexer (MUX), included in the x MII layer, construct a super frame with a synchronous frame and an asynchronous frame, transmit the super frame through the physical layer, parse a received super frame into a synchronous frame and an asynchronous frame, and transmit the synchronous and asynchronous frames to the data link layer.

Disclosed is a UGMII system to interface multirate devices including 10 gigabit per second data exchange rates. Mode selection is enabled to provide for automatic detection and adaptation to any transmit rate including 10M, 100M, 1 G, and 10 G. Mode selection comprises the negotiation between the UGMII extension sublayers located at the MAC and PHY to select between one of several operational modes including: XGMII communication, GMII encapsulation, Clause 22 MDIO register management and Clause 45 MDIO register management. Selection of UGMII and XGMII operating modes are negotiated between the MAC and PHY using ordered sets to announce and acknowledgement a mode change. In one embodiment 802.3 Clause 46 defined ordered sets are utilized.

A method and apparatus for distributing and receiving high-speed Ethernet Media Independent Interface (MII) blocks are provided to moderate the increase of control lines with the increase of the bit width and to simplify the block types in the coding process of the Physical Coding Sublayer (PCS). The technical solution disclosed herein includes: processing received Media Access Control (MAC) layer data, and adjusting distribution of control characters to generate a 64-bit block; obtaining a control signal code of the 64-bit block according to the relation between the form of the 64-bit block and the control signal code; and binding each 64-bit block to the corresponding control signal code respectively, and sending bound data over a separate channel.

A network interface which reduces pin count in an MII or GMII system by logically combining certain signals to eliminate redundancies, thereby enabling one external connection or pin to perform the functions previously performed by multiple pins. In particular, the two connections previously used for TX_EN and TX_ER are reduced to a single TX_CTRL connection. Similarly, the three connections for RX_DV, CRS and RX_ER are reduced to a single RX_CTRL connection. The COL connection is also eliminated.

Provided is a 10/100Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional 100Base-T interface specified by IEEE 802.3u (clause 22). As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on sixteen wires in a conventional 100Base-T interface at 25 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 125 MHz, five times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis. Therefore, the number of pins required for a MAC to transceiver interface is two times the number of ports plus two instead of sixteen times the number of ports, and the addition of each additional port requires only two more wires (pins).

Methods and apparatus are provided for interfacing a plurality of encoded serial data streams, such as Serial Gigabit Media Independent Interface streams, to a serializer/deserializer circuit. A plurality of encoded serial data streams are transmitted by receiving the plurality of encoded serial data streams that have been encoded using an encoding scheme that provides a substantially uniform distribution of a first code and a second code; marking at least one of the encoded serial data streams (such as changing a first code to a predefined code); and combining at least two of the plurality of encoded serial data streams into a single data stream. A plurality of encoded serial data streams are received by receiving a single data stream comprised of the plurality of encoded serial data streams; detecting a mark in the single data stream; demultiplexing the single data stream into the plurality of encoded serial data streams based on the mark; and providing the demultiplexed plurality of encoded serial data streams to a decoder that decodes the plurality of encoded serial data streams using a decoding scheme that provides a substantially uniform distribution of a first code and a second code.

A physical layer (PHY) in a network device may provide self-adapting power reduction based on monitoring of activity associated with an interface between the PHY and remaining components of the network device. The power management operations of the PHY may then be configured and/or adjusted based on that monitoring. The PHY may comprise an Ethernet PHY, which may support energy efficient Ethernet (EEE) features. The monitored interface may comprise a Media Independent Interface (MII) based interface. In instances where the monitored activity comprises outbound traffic, outbound data received via the interface may be buffered when at least one subcomponent of the PHY that is operable to support transmission of the outbound traffic is unavailable due to the power management operations. The buffering may be configured to last to allow sufficient time to reactivate the at least one subcomponent.

A method is performed in a communication device that includes one or more media access control (MAC) entities, a coax physical layer (PHY), and a media-independent interface coupling the one or more MAC entities with the coax PHY. In the method, a bitstream is generated that includes data frames and characters corresponding to time windows in which the coax PHY does not transmit signals. The bitstream is provided to the coax PHY through the media-independent interface. Signals corresponding to the data frames are transmitted from the coax PHY during a transmit mode. The coax PHY enters a receive mode when the bitstream contains the characters corresponding to the time windows.

The invention relates to radar signal processing and relevant technical fields, in particular to a network and SRIO data exchanging plate based on a VPX bus and a control method for the network and SRIO data exchanging plate. The network and SRIO data exchanging plate based on the VPX bus comprises a power module, an FPGA (field programmable gate array) control module, a first SRIO exchanging module, a second SRIO exchanging module, a network exchanging module, a network interface module, an FLASH module, a debugging serial port module, an FPGA debugging port and an LED (light emitting diode) lamp display module. The problems that a data transmission mode of the existing signal processing system is inflexible, and the existing signal processing system does not have a system reconfigurable function are solved; an SRIO and network exchanging chip is adopted; a 12-channel SGMII (serial gigabit media independent interface) network and a 10-channel SRIO port can be exchanged; and the 10-channel SRIO port can be configured into an X4 or X1 SRIO exchanging port according to different application requirements. The data exchanging plate has the advantages that the data exchanging plate is high in integration level and real-time in exchanging and has abundant ports.

The invention discloses an Ethernet MAC (Media Access Control) sublayer controller applicable to WLAN (Wireless Local Area Network). The Ethernet MAC sublayer controller comprises a transmitter module, a receiver module, a state module, a control module, an MII (Media Independent Interface) management module, a transmission cache, a receiving cache and a register module, wherein the transmission cache and the receiving cache can realize storage, retransmission and discard of data frames by employing the asynchronous FIFO (First-in First-out) capable of loading read addresses, the information interaction of data frames between a host and the MAC sublayer controller is carried out through data frame cache descriptors which include transmitting cache descriptors and receiving cache descriptors, wherein the transmitting cache descriptors are used for controlling the transmitting process of the data frames, recording and returning a transmitting state; the receiving cache descriptors are used for controlling the reading of received data frames and returning a frame receiving state to the host. By the Ethernet MAC sublayer controller, the network access of embedded devices, the frame conflict retransmission and discard of bad frames are realized, and the utilization rate of cache in a chip is improved when short frames are received.

The invention discloses a GigE vision protocol-based Ethernet controller IP core. The GigE vision protocol-based Ethernet controller IP core is composed of a control module, a PHY (physical layer) management interface module, a transmission control module, a flow control module and a receiving control module and implemented through FPGAs (field programmable gate array) and follows the Avalon Memory-Mapped interface specifications and the GMII (gigabit media independent interface) specifications. The GigE vision protocol-based Ethernet controller IP core is a special IP core designed according to the characteristics of the GigE Vision protocol and can achieve GigE camera image receiving and automatic storage; the GigE vision protocol-based Ethernet controller IP core achieves image collection and meanwhile overcomes the shortcomings of large resource occupation, high CPU (central processing unit) utilization rate, low image collecting efficiency and the like of traditional Ethernet controllers; by means of the characteristics of parallel processing of the FPGAs, the data receiving speed and the system timeliness can be improved. Under the same testing conditions, collecting images through the GigE vision protocol-based Ethernet controller IP core can reduce more than a half of FPGA resource consumption compared with a triple-speed Ethernet core of the Altera Company.

A network device includes a plurality of physical-media entities (PMEs), each corresponding to a distinct channel, to generate transmit signals based on transmit packets received over a media-independent interface. The network device also includes a channel-bonding sublayer to direct the transmit packets from the media-independent interface to respective PMEs of the plurality of PMEs. The channel-bonding sublayer has a substantially fixed delay between the media-independent interface and the plurality of PMEs for the transmit packets.

The invention discloses an E1 emulation realization method, which relates to the field of network simulation and comprises the following steps of: performing protocol encapsulation on a direction, and performing serialization processing on received data to generate a real-time transport protocol value; assembling a time division multiplexing (TDM) payload into a frame, forming cache data packets by using the processed data, and finishing a corresponding description table; attaching packet headers to the TDM payload, generating control word information and real-time transport protocol information according to configuration, and performing encapsulation according to a protocol; performing clock domain adaptation on the processed data, finishing Ethernet media access control (MAC) processing, and transmitting Ethernet data by using a media independent interface (MII); performing protocol decapsulation on the direction, receiving and caching the Ethernet data, and finishing MAC layer processing; classifying and identifying the Ethernet data packets, extracting the payload and related control bytes, and counting state information; and performing clock recovery on a processed TDM payload code stream, and externally transmitting the processed TDM payload code stream. The method is relatively lower in cost; updating can be performed; and requirements on the performance of a central processing unit (CPU) are reduced, and clock recovery performance is improved.

A method for testing a network switch chip having an expansion port configured for transferring data according to a prescribed expansion port protocol. The method includes outputting the expansion port frame data from the expansion port according to the prescribed expansion port protocol, converting the expansion port frame data from the prescribed expansion port protocol to a prescribed network protocol such as IEEE 802.3-based Media Independent Interface (MII) protocol, and outputting the converted data according to the prescribed MII protocol to a test device having an MII interface configured for receiving the data according to the prescribed MII protocol. The conversion of the data from the prescribed expansion port protocol to the prescribed MII protocol enables the use of the test device for validation of the expansion port, without the necessity of another network switch chip.

The present invention discloses an energy efficient network communication device comprising: a media-access-controller for outputting a transmission-end low power idle (LPI) indication and receiving a reception-end LPI indication; a media-independent-interface for generating a transmission-end LPI signal according to the transmission-end LPI indication, and generating the reception-end LPI indication according to a reception-end LPI signal; and a physical-layer-circuit, coupled to several pairs of transmission lines, for converting the transmission-end LPI signal into a transmission signal to send it to a reception end for requesting an LPI mode and receiving a reception signal from the reception end to convert it into the reception-end LPI signal. Said physical-layer-circuit uses some of the several pairs of transmission lines for transmission and reception when keeping the other pairs of transmission lines unused to save power; furthermore, the physical-layer-circuit can enter the LPI mode from an idle mode for additional power saving.

The invention relates to a universal full-hardware one-step 1588 clock synchronization device and method. The device comprises a framing module, an MAC transmission control module, an MAC receiving control module, an analysis module, a timestamp generation module, a first-in first-out queue timestamp FIFO module, a local clock module, a deviation calculation module and a timestamp insertion module. The method of the invention includes the following steps: recording timestamp information, identifying synchronous messages, storing the timestamp information, identifying synchronous broadcast messages Sync, inserting the timestamp information, calculating the time deviation of master-slave clocks, and correcting the time of the slave clock. According to the scheme of the invention, a hardware-only one-step synchronization method is adopted, effective data signals ctrl at a reduced gigabit media independent interface (RGMII) between a data link layer MAC and a physical layer PHY are adoptedto collect accurate timestamp information, and thus the universality and synchronization accuracy of the system can be improved.

The invention discloses a network time-setting system and method for secondary equipment of an electric power system. The network time-setting system is characterized by comprising a CPU (central processing unit), an FPGA (field programmable gate array), a physical layer network card chip PHY and an oven controlled crystal oscillator OCXO, wherein the CPU is connected with the FPGA through a PCIE (peripheral component interface express) bus; the FPGA comprises Ethernet medium access controllers (MAC) which are realized through the FPGA, a hardware time stamp detecting and generating module and a phase locking loop (PLL). The time-setting method comprises the following steps: inputting setting time through a network, filtering messages, improving the time -setting synchronizing precision of the messages, adding hardware time stamps to the messages through the FPGA, synchronizing network setting-time, and outputting network setting-time. The network time-setting system disclosed by the invention uses the FPGA as a core, and under the condition that a hardware structure is not changed, multichannel high-precision network time setting can be realized at a relatively low cost; besides, through the phase locking loop (PLL) and a technique of additionally stamping the hardware time stamps on an MII (media independent interface) layer, the network time-setting precision can also be greatly improved, and the expansion performance is good.

A communication device includes: a wireless communication unit configured to perform data transmission and receiving with another communication device via a wireless network; and a communication control unit electrically connected with the wireless communication unit via a media independent interface (MII) bus and configured to control the wireless communication unit using a management data input-output/management data clock (MDIO/MDC) included in the MII bus.