14 results about "Media Independent Interface" patented technology

The invention discloses an ASIC chip for high-performance AOIP network audio stream transmission, and the interior of the chip comprises a function simulation circuit subsystem, a sensor controller, a clock, and a reset control module. The high-speed peripheral interface subsystem is arranged on the first bus, the hardware acceleration subsystem is arranged on the second bus, the low-speed peripheral interface subsystem is arranged on the third bus, the second bus is connected with the first bus and the third bus, and the function simulation circuit subsystem is connected with the third bus through the sensor controller; the hardware acceleration subsystem comprises a plurality of processor cores, two gigabit or 100M bit medium independent interfaces and a real-time transport protocol RTP transceiving engine; the two gigabit or 100M bit medium independent interfaces are compatible with the simplified medium independent interface, one of the two gigabit or 100M bit medium independent interfaces is used as a main network interface, and the other one is used as a standby network interface. The reliability problem of AOIP network audio stream transmission is solved.

The application relates to the technical field of well logging, in particular to a high-speed temperature-resistant data reading system, method, device, equipment, medium and product, wherein the system comprises a processing unit, an encoding circuit, an analog-digital conversion circuit and an impedance matching circuit; a simplified media independent interface of the processing unit is connected to the encoding circuit; the encoding circuit is coupled to the analog-digital conversion circuit through the impedance matching circuit; and the temperature-resistant performance and reading rate of the data reading system can be improved.

A serial media independent interface (Mil) for a host device and / or a physical layer (PHY) device embeds a register access protocol such as management data input / output (MDIO) in a serial data stream. Symbol ordered sets are exchanged over the Mil and / or enhanced SMII interface. At least one of the symbol ordered sets selectively defines a sync signal allowing removal of a sync signal and corresponding sync pin. Clock speeds are selectively reduced on the enhanced SMII interface. Toggling power is selectively reduced when idles are exchanged.

The invention discloses a time division multiplexing media independent interface and method supporting multi-rate and multi-channel communication, and the interface comprises a media access control layer module and a physical coding sub-layer module which support the multi-rate and multi-channel communication, the medium access control layer module and the physical coding sub-layer module share the same path of clock signals and channel mode configuration signals, and signals output to the physical coding sub-layer module by the medium access control layer module comprise transmission channel time slot signals, transmission data signals, transmission control signals and transmission data and control effective signals; signals output to the medium access control layer module by the physical coding sub-layer module comprise a sending enable signal, a receiving channel time slot signal, a receiving data signal, a receiving control signal and a receiving data and control effective signal. The invention aims to solve the problems of various interface types and interface signals in the existing medium independent interface technology, and realizes the compatibility of the multi-rate multi-channel Ethernet in a large rate range.

The utility model relates to a wireless communication module and a wireless communication system. The wireless communication module comprises a baseband chip, an M.2 connector and a power management unit, the baseband chip comprises a multiplexing function module and an interface type selection pin; wherein the multiplexing function module is used for selecting a level state input by a pin according to the interface type to transmit a high-speed serial computer expansion bus standard PCIe signal or a serial gigabit media independent interface SGMII signal; the M.2 connector comprises an M.2 interface and a selection circuit; the M.2 interface is connected with the multiplexing function module, one end of the selection circuit is connected with the interface type selection pin, and a high level or a low level is output to the interface type selection pin through the connection state of the other end of the selection circuit. Therefore, the wireless communication module is compatible with the SGMII interface besides supporting the PCIe interface defined by the original specification, and the compatibility and the product competitiveness of the wireless communication module are improved.

An apparatus with a network controller sideband interface retimer includes a second clock circuit configured to transmit a second clock signal to a NIC. The second clock signal is separate from a first clock signal from a clock connected to a BMC. The apparatus includes a NIC data relay circuit configured to receive data packets from the NIC on a first reduced media independent interface (“RMII”) bus and to transmit the received data packets to the BMC over a second RMII bus. The apparatus includes a clock delay circuit configured to add a delay to the second clock signal to create a delayed second clock signal. The delay is adjusted to cause the delayed second clock signal to coincide with a time during receipt of the data packets received from the NIC when data of a bit of the data packets received from the NIC is valid.

An apparatus with a network controller sideband interface retimer includes a second clock circuit configured to transmit a second clock signal to a NIC. The second clock signal is separate from a first clock signal from a clock connected to a BMC. The apparatus includes a NIC data relay circuit configured to receive data packets from the NIC on a first reduced media independent interface (“RMII”) bus and to transmit the received data packets to the BMC over a second RMII bus. The apparatus includes a clock delay circuit configured to add a delay to the second clock signal to create a delayed second clock signal. The delay is adjusted to cause the delayed second clock signal to coincide with a time during receipt of the data packets received from the NIC when data of a bit of the data packets received from the NIC is valid.

The invention provides a photoelectric conversion interface device and a control system. The photoelectric conversion interface device comprises a first media independent interface, a PHY chip and a photoelectric conversion unit, the first media independent interface is used for receiving a first MII signal from the outside of the device and sending a second MII signal in the photoelectric conversion interface device, the PHY chip is connected with the first media independent interface and is used for carrying out physical layer coding and parallel-to-serial conversion on the MII signal to generate a first electric signal, and the first electric signal is sent to the first media independent interface. The second MII module is used for performing clock data recovery, serial-to-parallel conversion and decoding on the second electric signal to obtain a corresponding second MII signal; and the photoelectric conversion unit comprises a first optical fiber interface, is directly or indirectly connected with the PHY chip and is used for performing photoelectric conversion. Complex hardware does not need to be designed for a special communication protocol, the communication rate is improved by arranging the PHY chip, and a universal MII / RMII interface is provided on the controller side, so that a high-speed optical communication link based on a standard Ethernet physical layer can be established between the controller and the driver.

The application discloses an ASIC chip for high-performance AOIP network audio stream transmission, which internally comprises a functional analog circuit subsystem, a sensor controller, a clock and reset control module, a high-speed peripheral interface subsystem arranged on a first bus, a hardware acceleration subsystem arranged on a second bus, and a low-speed peripheral interface subsystem arranged on a third bus, the second bus being connected with the first bus and the third bus respectively, and the functional analog circuit subsystem being connected with the third bus through the sensor controller; the hardware acceleration subsystem comprises a plurality of processor cores, two gigabit or megabit media independent interfaces and a real-time transmission protocol (RTP) transceiving engine; the two gigabit or megabit media independent interfaces are compatible with simplified media independent interfaces, one of the two gigabit or megabit media independent interfaces is used as a main network interface, and the other is used as a backup network interface. The reliability of AOIP network audio stream transmission is solved.

The application discloses a time division multiplexing medium independent interface and method supporting multi-rate multi-channel communication. The interface comprises a medium access control layer module and a physical coding sublayer module supporting multi-rate multi-channel communication. The medium access control layer module and the physical coding sublayer module share the same path clock signal and channel mode configuration signal. The signal output from the medium access control layer module to the physical coding sublayer module comprises a sending channel time slot signal, a sending data signal, a sending control signal and a sending data and control effective signal. The signal output from the physical coding sublayer module to the medium access control layer module comprises a sending enable signal, a receiving channel time slot signal, a receiving data signal, a receiving control signal and a receiving data and control effective signal. The application aims to solve the problem of various interface types and interface signals in the existing medium independent interface technology and realize the compatibility of multi-rate multi-channel Ethernet with a large rate range.

The utility model relates to the technical field of network transmission, in particular to a zero-delay switching parallel redundant network chip, which comprises an electronic circuit board, an FPGA (Field Programmable Gate Array) chip, an indicating lamp, a power supply and a heat dissipation device, the FPGA chip, the indicating lamp, the power supply and the heat dissipation device are fixed on the electronic circuit board; a connecting plug is arranged on the FPGA chip, a jack is formed in the electronic circuit board, the connecting plug is matched with the jack, and electric connecting sheets are arranged in the connecting plug and the jack; and the FPGA chip at least comprises two RGMII (Regularly Gateway Media Independent Interface) interfaces and four 1000BASE-X interfaces. The zero-delay switching parallel redundant network chip can realize dual-redundancy communication, and achieves the technical effect of improving the reliability of the network.

The invention provides a data transmission method and device based on an MII interface, and relates to the technical field of data transmission. The method comprises the following steps: firstly detecting the state of a data effective signal of a receiving end of an MII interface, if the state of the data effective signal is low level, generating a pulse enable signal, then determining the state of a counter according to the pulse enable signal to obtain a counter value, and when the counter value is a first count value, sampling the data signal received by the MII interface; and when the counter value is a second count value, executing parallel-to-serial operation on the sampled data signal to obtain serial data, and finally, outputting the serial data. Therefore, by detecting the state of the pulse enable signal and matching with the counter value, the data sampling time and the time for executing the parallel-to-serial operation on the data can be accurately controlled, so that the time delay can be reduced, and the data transmission efficiency of the MII interface can be improved.

The invention relates to a serial port-Ethernet protocol conversion system and method based on a domestic chip. System hardware adopts full-autonomous chips: a JS32F407 MCU (Microprogrammed Control Unit), a JDP83848 PHY (Physical Layer) chip and a JS74401 power supply management chip, and a domestic hardware platform is constructed through direct connection of an RMII (Remote Media Independent Interface); an LWIP protocol stack is customized on the software level, an IEEE 1588 v2 protocol is fused, and sub-microsecond clock synchronization is achieved through a JS32F407 hardware timestamp engine. The system and the method have the following advantages that the JS74401 chip integrates soft start and a multi-stage protection circuit, and supports a wide temperature range of-50 DEG C to 105 DEG C and + / -15% voltage fluctuation; through a frame header separation technology, 115200bps high Baud rate non-packet loss transmission is supported; the size is reduced through the stacking design, and the method is suitable for compact scenes such as edge gateways.

Embodiments of the present application provide a communication method and device based on a server, which are applied to the technical field of servers. A baseboard management controller communicates with a network switch chip by means of a target chip, and the network switch chip provides at least two network ports. The method comprises: detecting a connection mode of a management data input / output protocol in a target chip; and when the connection mode is that the target chip is connected to a baseboard management controller, controlling the baseboard management controller to communicate with the target chip by using an optical fiber gigabit Ethernet protocol in an optical fiber mode, and controlling the target chip to communicate with a network switch chip by using an optical fiber gigabit Ethernet protocol in a reduced gigabit media independent interface mode. In this way, a network switch chip provides at least two network ports for a baseboard management controller, and normal communication of the at least two network ports is guaranteed, so that the method is suited to scenarios where a plurality of network functions are required.