5 results about "Media Independent Interface" patented technology

The application relates to the technical field of well logging, in particular to a high-speed temperature-resistant data reading system, method, device, equipment, medium and product, wherein the system comprises a processing unit, an encoding circuit, an analog-digital conversion circuit and an impedance matching circuit; a simplified media independent interface of the processing unit is connected to the encoding circuit; the encoding circuit is coupled to the analog-digital conversion circuit through the impedance matching circuit; and the temperature-resistant performance and reading rate of the data reading system can be improved.

The utility model relates to a wireless communication module and a wireless communication system. The wireless communication module comprises a baseband chip, an M.2 connector and a power management unit, the baseband chip comprises a multiplexing function module and an interface type selection pin; wherein the multiplexing function module is used for selecting a level state input by a pin according to the interface type to transmit a high-speed serial computer expansion bus standard PCIe signal or a serial gigabit media independent interface SGMII signal; the M.2 connector comprises an M.2 interface and a selection circuit; the M.2 interface is connected with the multiplexing function module, one end of the selection circuit is connected with the interface type selection pin, and a high level or a low level is output to the interface type selection pin through the connection state of the other end of the selection circuit. Therefore, the wireless communication module is compatible with the SGMII interface besides supporting the PCIe interface defined by the original specification, and the compatibility and the product competitiveness of the wireless communication module are improved.

An apparatus with a network controller sideband interface retimer includes a second clock circuit configured to transmit a second clock signal to a NIC. The second clock signal is separate from a first clock signal from a clock connected to a BMC. The apparatus includes a NIC data relay circuit configured to receive data packets from the NIC on a first reduced media independent interface (“RMII”) bus and to transmit the received data packets to the BMC over a second RMII bus. The apparatus includes a clock delay circuit configured to add a delay to the second clock signal to create a delayed second clock signal. The delay is adjusted to cause the delayed second clock signal to coincide with a time during receipt of the data packets received from the NIC when data of a bit of the data packets received from the NIC is valid.

The invention provides a photoelectric conversion interface device and a control system. The photoelectric conversion interface device comprises a first media independent interface, a PHY chip and a photoelectric conversion unit, the first media independent interface is used for receiving a first MII signal from the outside of the device and sending a second MII signal in the photoelectric conversion interface device, the PHY chip is connected with the first media independent interface and is used for carrying out physical layer coding and parallel-to-serial conversion on the MII signal to generate a first electric signal, and the first electric signal is sent to the first media independent interface. The second MII module is used for performing clock data recovery, serial-to-parallel conversion and decoding on the second electric signal to obtain a corresponding second MII signal; and the photoelectric conversion unit comprises a first optical fiber interface, is directly or indirectly connected with the PHY chip and is used for performing photoelectric conversion. Complex hardware does not need to be designed for a special communication protocol, the communication rate is improved by arranging the PHY chip, and a universal MII / RMII interface is provided on the controller side, so that a high-speed optical communication link based on a standard Ethernet physical layer can be established between the controller and the driver.

The application discloses an ASIC chip for high-performance AOIP network audio stream transmission, which internally comprises a functional analog circuit subsystem, a sensor controller, a clock and reset control module, a high-speed peripheral interface subsystem arranged on a first bus, a hardware acceleration subsystem arranged on a second bus, and a low-speed peripheral interface subsystem arranged on a third bus, the second bus being connected with the first bus and the third bus respectively, and the functional analog circuit subsystem being connected with the third bus through the sensor controller; the hardware acceleration subsystem comprises a plurality of processor cores, two gigabit or megabit media independent interfaces and a real-time transmission protocol (RTP) transceiving engine; the two gigabit or megabit media independent interfaces are compatible with simplified media independent interfaces, one of the two gigabit or megabit media independent interfaces is used as a main network interface, and the other is used as a backup network interface. The reliability of AOIP network audio stream transmission is solved.