Universal full-hardware one-step 1588 clock synchronization device and method

Abstract

The invention relates to a universal full-hardware one-step 1588 clock synchronization device and method. The device comprises a framing module, an MAC transmission control module, an MAC receiving control module, an analysis module, a timestamp generation module, a first-in first-out queue timestamp FIFO module, a local clock module, a deviation calculation module and a timestamp insertion module. The method of the invention includes the following steps: recording timestamp information, identifying synchronous messages, storing the timestamp information, identifying synchronous broadcast messages Sync, inserting the timestamp information, calculating the time deviation of master-slave clocks, and correcting the time of the slave clock. According to the scheme of the invention, a hardware-only one-step synchronization method is adopted, effective data signals ctrl at a reduced gigabit media independent interface (RGMII) between a data link layer MAC and a physical layer PHY are adoptedto collect accurate timestamp information, and thus the universality and synchronization accuracy of the system can be improved.

Description

technical field [0001] The present invention belongs to the technical field of communication, and further relates to a universal full-hardware one-step clock synchronization device and method based on the precision clock synchronization protocol standard IEEE 1588 (Precision Clock Synchronization Protocol) of the network measurement and control system in the technical field of Ethernet. According to the precision clock synchronization protocol standard IEEE 1588 (Precision Clock Synchronization Protocol) of the network measurement and control system, the present invention calibrates the clock of the network equipment, so that the distributed system based on Ethernet can achieve accurate synchronization, and guarantee the communication between network equipment in the Ethernet environment. real-time communication. Background technique [0002] At present, with the rapid development of Ethernet technology, modern industry has higher and higher requirements for clock synchroniz...

AI Technical Summary

Problems solved by technology

The disadvantage of this device is that the PHY module needs to use a dedicated PHY chip that supports the IEEE 1588 protocol to complete the functions of identifying IEEE 1588 messages and giving message sending and receiving indication signals. Although the synchronization accuracy is greatly improved, this chip will cause The synchronization platform has poor versatility and portability

The disadvantage of this method is that in each synchronization process, the master node needs to send a follow message (FollowUp), which contains the precise time stamp information when sending the synchronization message Sync, which increases the traffic of the network

The disadvantage of this method is that when the system kernel and the network card software driver layer process the timestamp generated by the software, due to the cache effect of the network card and the uncertainty of the process scheduling of the operating system, the CPU will be congested. The problem makes this synchronization method unable to guarantee the stability of clock synchronization of network equipment

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