135 results about "Slave clock" patented technology

The invention discloses a synchronization method and device for time synchronization of a network system, and relates to the technical field of computers, and the method comprises the following steps: when a master station sends a dynamic compensation synchronization frame, recording a compensation sending timestamp in a sensing identification field of a sending end; when the frame is received and transmitted from the station, the identification field is sensed at the port to determine a compensation receiving timestamp and a compensation transmitting timestamp. And the slave station identifies the dynamic compensation synchronization frame after reverse return, calculates dynamic compensation time information based on the compensation receiving timestamp and the compensation sending timestamp corresponding to the slave station, and reads and writes the dynamic compensation time information to a corresponding field. And the master station analyzes the returned dynamic compensation synchronization frame, aggregates the dynamic compensation time information of each slave station, and solves the dynamic compensation values of the master and slave stations in combination with the fixed link delay. And the master station corrects a local high-precision clock according to the data, and writes a compensation value into a local time correction register of the slave station to trigger a hardware counter to correct so as to complete synchronization of the master and slave clocks. By realizing dynamic residence separation, the problem of overlarge error is solved.

The invention discloses a wireless communication system and method based on an EtherCAT network. The system comprises a wireless gateway and a wireless slave station, the wireless gateway comprises an EtherCAT slave station module, a wireless communication module, a control module and an auxiliary function module. The control module carries out packaging conversion on an EtherCAT frame received by the EtherCAT slave station module and a wireless frame of the wireless communication module through hardware-level protocol conversion; the wireless communication module is an FHSS module or a WiFi module. The auxiliary function module comprises a timestamp module for recording time information and is used for assisting the control module to perform master-slave clock synchronization by adopting a multi-stage distributed clock synchronization optimization algorithm; the wireless slave station comprises an EtherCAT slave station module, a wireless communication module and a local control unit, wherein the EtherCAT slave station module is used for receiving the control instruction of the EtherCAT master station and is compatible with the wireless gateway; the wireless communication module is used for uploading a wireless frame packaged with an EtherCAT sub-message and has the same model as the wireless frame; and the local control unit is used for analyzing the control instruction of the EtherCAT master station to collect local data and packaging the local data into the EtherCAT sub-message. According to the invention, requirements of industrial automation on high-precision and high-reliability wireless communication can be met.

The invention discloses a power grid time frequency change trend prediction method and system based on intelligent electric meter data fusion, and the method comprises the steps: measuring the network transmission delay and time deviation between a master clock and a slave clock of a power grid, obtaining an initial time frequency deviation sequence, carrying out the error calibration, carrying out the data fusion after time domain alignment, and carrying out the prediction of the time frequency change trend. Generating a fusion time sequence; performing recursive estimation on the fusion time sequence, outputting an optimal time frequency deviation sequence, and performing synchronous estimation to obtain a clock phase error, a frequency error and frequency drift as state characteristic quantities; and training a preset machine learning prediction model by taking the optimal time frequency deviation sequence as a supervision signal and taking the state characteristic quantity of the corresponding moment as input, and obtaining a prediction result of the power grid time frequency change trend in the future period based on the trained time frequency change trend prediction model. According to the method, the power grid time synchronization precision and prediction capability are remarkably improved, and reliable technical guarantee is provided for stable operation of a power system.

The invention discloses a time sequence synchronization method and system for data fusion of a multi-modal wearable sensor, a terminal and a storage medium. The method comprises the following steps: acquiring an absolute timestamp as a global clock source; taking the global clock source as a master clock of a precision time protocol, configuring the plurality of wearable sensors as slave clocks, and executing multiple rounds of message interaction between the master clock and the slave clocks through the precision time protocol to obtain a timestamp corresponding to each round of interaction; and calculating the current path time delay and the current clock offset according to the corresponding timestamps, carrying out iterative judgment on the current path time delay and the current clock offset according to a preset path time delay threshold value and a preset clock offset threshold value, and determining whether to correct the local clock according to the current clock offset according to an iterative judgment result. The slave clock and the global clock source achieve time sequence synchronization; and after time synchronization is achieved, phase alignment is carried out on the periodic data sampling tasks of the multiple wearable sensors. According to the invention, the time sequence synchronization precision is obviously improved.

The invention provides a clock synchronization method, a multi-axis drive control system and a computer storage medium, and the method comprises the steps: obtaining a clock synchronization signal which is sent by a master station timer and has a matched period at a slave station end, selecting any timestamp in the clock synchronization signal as a reference point, and carrying out the clock synchronization based on the reference point, determining the corresponding position of the reference point in the counting signal of the local timer, mapping the time information of the master station to a local time axis of the slave station, and calculating the phase difference between the corresponding position of the reference point in the counting signal of the local timer and the starting position of the next period of the counting signal of the local timer, and quantizing the real-time deviation of the master and slave clocks, and finally, dynamically adjusting and updating the period of a counting signal of a local timer to eliminate the phase difference, so that the slave station clock period is kept synchronous with the master station, and the time consistency of the action of each slave station in the multi-axis driving system is ensured.

The invention relates to the technical field of testability design, and discloses an on-chip clock controller and test equipment, the on-chip clock controller comprises a main clock control circuit, the functional clock input end of the main clock control circuit is connected with a phase-locked loop output clock, and the clock output end of the main clock control circuit is connected to a main frequency domain receiving node so as to output a main frequency clock signal to the main frequency domain receiving node; the functional clock input end of the slave clock control circuit is connected with the clock output end of the master clock control circuit, and the clock output end of the slave clock control circuit is connected to a frequency division domain receiving node so as to output a frequency division clock signal to the frequency division domain receiving node; wherein the master clock control circuit and the slave clock control circuit are controlled by external slave enable signals, and a data interaction channel is arranged between the master frequency domain receiving node and the frequency division domain receiving node. By cascading the master clock control circuit and the slave clock control circuit and constructing the data interaction channel, dynamic collaborative testing of the master frequency domain and the frequency division domain is realized, and the problem of delay fault detection of the multi-frequency-domain integrated circuit is solved.

Embodiments of this application provide a clock synchronization method and an apparatus. The clock synchronization method is applied to a slave node. The clock synchronization method includes: receiving a synchronization packet sent by a master node, where the synchronization packet carries a master clock timestamp of the master node; establishing a mapping relationship between a master clock of the master node and a reference timescale of the slave node based on the master clock timestamp and a timestamp corresponding to a reference timescale of the slave node when the slave node receives the synchronization packet; obtaining a time combination of the timestamp corresponding to the reference timescale of the slave node and slave clock time of the slave node, where a collection moment of the reference timescale of the slave node and a collection moment of the slave clock time corresponding to the reference timescale are the same.

The invention discloses a task synchronization and scheduling method for compensating CAN bus clock drift, which relates to the technical field of industrial automation control, and comprises the following four steps: initializing a system, loading a real-time protocol stack, completing hardware self-inspection and clock calibration, and sending a ready signal after confirming that a link is smooth; performing synchronization parameter configuration and task planning, defining clock synchronization reference parameters, dividing four types of tasks and setting priorities; performing dynamic calibration and data buffering on master and slave clocks, broadcasting a synchronous message with a timestamp by a master station, correcting a local timer by a slave station through a soft phase-locked loop, and constructing an annular buffer area to realize time domain decoupling; task cooperative scheduling and abnormal fault tolerance are carried out, a control task is triggered based on a calibration clock, edge calculation is carried out to reconstruct a motion state and feed-forward compensation is carried out, a multi-dimensional state is monitored in real time, and a fault tolerance mechanism is triggered. According to the method, clock synchronization precision and control stability are greatly improved, bus bandwidth limitation is broken through, high dynamic tracking precision is achieved, and long-term stable operation of the system is guaranteed.

The invention discloses a periodic synchronous position interpolation control method and system for a servo driver, and relates to the technical field of servo control, and the method comprises the steps: receiving a synchronous position instruction at a fixed bus period, and recording a theoretical / actual arrival timestamp of the synchronous position instruction; converting the instruction into a position increment and storing the position increment into a buffer; calculating a cache saturation index reflecting instruction stream supply and demand balance in real time; based on the index and the change trend, dynamically calculating and smoothly adjusting a next position loop sampling period through a feedback control model; position loop processing is triggered in the post-adjustment period. According to the invention, by monitoring the instruction stream state and adaptively adjusting local processing, the influence caused by master and slave clock skew and network jitter is compensated, and continuous and uniform instruction input is ensured to be always obtained by a position ring, so that high-stability and high-precision motion control under bus communication is realized, and the anti-interference capability and the synchronization performance of the system are improved.

The invention discloses a PTP clock synchronization implementation method based on sliding mode control calibration, and the method comprises the steps: designing master and slave clock synchronization equipment, designing a slave clock into two DP83640 pieces for eliminating the problem of insufficient adjustment resolution of a local clock of a single chip, calculating the clock deviation through message transmission by the master and slave clocks, and carrying out the initial adjustment and compensation of the local clock, after preliminary adjustment is completed, a high-precision time interval counter is used for finely measuring master-slave clock skew, the master-slave clock skew is input into a designed sliding mode controller to generate a calibration control quantity, the clock skew is finely calibrated according to the calibration control quantity, and more accurate clock synchronization is completed. Experimental results show that the method provided by the invention can realize synchronization precision superior to 300ps, and has great reference value.

The invention relates to the technical field of current transformer calibration equipment, and discloses a current transformer calibration device and a detection method. An integrated controller, a signal generation module, a data processing unit, a man-machine interaction unit, a signal processing unit, a communication relay unit and an error calculation module are arranged in the device, and a master-slave clock distributor is arranged in the communication relay unit. And the detection probe is internally provided with a plurality of current sensors, and each current sensor has a broadband response characteristic. The design is reasonable, the multi-station mutual inductor fixing clamp is in linkage with the bevel gear set through the driving motor, the driving shaft and the spiral groove connecting cylinder are driven to achieve synchronous rotating propelling, and the rotating frame and the arc-shaped connecting rod are matched to drive the clamping plate to retract in a self-adaptive mode. According to an original constant force control mechanism, after the clamping plate makes contact with the mutual inductor, the balance weight mechanism is triggered through axial displacement of the connecting cylinder to dynamically balance pressure, and it is ensured that constant clamping force is applied to all stations.

The invention relates to the technical field of wireless communication networks, and particularly discloses a high-robustness PTP time synchronization method and system for a wireless Mesh network. According to the method, global topology information and real-time link quality information of a wireless Mesh network are obtained through a centralized network controller, an optimal end-to-end synchronization path is dynamically calculated for a slave clock node, an intermediate node on the path performs residence time accumulation correction in a transparent clock mode, high-precision end-to-end synchronization of a slave clock and a master clock is realized, and the synchronization precision of the slave clock and the master clock is improved. And the synchronization stability is ensured through continuous monitoring and seamless switching of a backup path. The system comprises a centralized network controller, a PTP master clock and a plurality of enhanced Mesh nodes. According to the method, the problems of poor dynamic topology adaptation, large transmission delay jitter, multi-hop error accumulation and the like of a standard PTP protocol in a wireless Mesh network are solved, the synchronization precision and robustness are remarkably improved, and a core support is provided for deterministic scheduling of a wireless TSN network.

A method of synchronization of a slave master clock of a set of slave equipment with a master main clock of a set of master equipment, on the basis of a common time base, including receiving, by the master equipment and by the slave equipment, clock pulses from the common time base, performing, from the master equipment and the slave equipment, a master timestamping and a slave timestamping of clock pulses received on the basis of the common time base, on the base of the master and the slave main clocks, respectively, for generating the master and the slave timestamping information, communicating the master timestamping information to the slave equipment, and regulating, in the slave equipment, the slave main clock on the basis of the master timestamping information communicated and on the basis of the slave timestamping information generated.

The invention discloses an internal delay calibration method for a network time protocol measurement device, which comprises the following steps of: establishing a reference signal 1PPS as a unified time reference; sending a synchronous message and outputting message record receiving time; measuring the moment when the synchronous message is received, and outputting the actual receiving time; comparing the message record receiving time with the actual receiving time, and outputting the internal delay of a receiving path; the slave clock sends a delay request message, and outputs the message to record the sending time; measuring the moment of sending the request message, and outputting the actual sending time of the request message; comparing the message record sending time with the actual sending time, outputting the internal delay of a sending path, and separating a stable delay component; and taking the internal delay of the receiving path and the sending path as input, compensating the master-slave clock deviation, and outputting the real time deviation of the master-slave clock. According to the invention, internal delay calibration of the measuring device is realized.

The invention provides a multi-source data fusion state estimation method, device and equipment, and relates to the technical field of state estimation, and the method comprises the steps: S1, collecting original observation data from N heterogeneous sensors, writing a local hardware timestamp for each piece of original observation data, and converting the timestamp into a second timestamp under a unified reference time base through master-slave clock bidirectional synchronization to obtain an original data stream with a unified time scale. According to the multi-source data fusion state estimation method, device and equipment, sensor time delay is used as an explicit variable for online estimation, and late data is digested by using an independent compensation channel. The main filter always runs according to a high-frequency beat without pause and rollback, and the end-to-end delay of the system is less than 5 milliseconds; the sliding window can be dynamically expanded, the delay error is converged to a sampling interval through correlation sampling interpolation, and the state precision is improved by about 30% compared with that of a traditional loose coupling method.

The application discloses a linear topology slave node synchronization method and system based on IEEE 1588 precision clock protocol, and the method comprises the following steps: step one, slave node 1 to slave node n-1 accepts PTP messages from a master node and forwards the PTP messages to the next level; step two, slave node 1 to slave node n-1 accepts PTP messages from slave node n and forwards the PTP messages to the previous level; step three, slave node 1 to slave node n takes an average value of round trip time to obtain an average link delay; step four, the master-slave clock offset is calculated according to the average transmission delay; and step five, dynamic frequency compensation calculation is performed. The application can increase the synchronization accuracy of the system and effectively reduce the clock deviation between nodes in the distributed system of the linear topology structure.

This invention relates to a time synchronization method for 5G and TSN converged networks based on a timestamp compensation algorithm, belonging to the field of cross-network time synchronization. It includes: introducing a 5G network as a TSN virtual bridge into the TSN network to form a cross-network, which includes a TSN1 network, a 5G network, and a TSN2 network. The cross-network uses the TSN switches in the TSN1 network as the master clock and the TSN devices in the TSN2 network as slave clocks. Synchronization is achieved by transmitting time synchronization information step-by-step across the NW-TT module, the 5G network clock domain, and the DS-TT module. The cross-network time synchronization includes TSN2 network time synchronization, 5G network time synchronization, and TSN2 network time synchronization. This invention improves the accuracy of time synchronization by calculating the frequency offset and dwell time between NW-TT and DS-TT within the 5G system and performing time compensation in the DS-TT.

The invention relates to the technical field of LED display, in particular to an LED display control system. The LED display control system comprises a sending card and a plurality of cascaded receiving cards, and the sending card comprises a video input module, a video data protocol packaging module, a first network data module, a main protocol module and a main clock module. The receiving card comprises an LED video driving control module, a video data protocol unpacking module, a second network data module, a slave protocol module, a slave clock module and a video frame frequency clock module, and the sending card and the receiving card carry out data interaction through the first network data module and the second network data module. The moment when each LED display box body uses the video frame frequency clock to reach the moment contained in the message is used as the starting moment of the next video frame, so that the asynchronization and jitter of the refresh frame frequency between the LED display box bodies caused by the transmission delay and jitter of the data packet in the cascade network can be eliminated.

The present disclosure describes a system, and a method to improve the system performance through hardware offload of a Best Master Clock Algorithm (BMCA). The system comprising at least one hardware entity integrated with a primary BMCA. The at least one hardware entity is configured to receive a plurality of Precision Time Protocol (PTP) masters from a plurality of PTP master clocks. Thereafter, the at least one hardware entity is configured to select a PTP master as a best PTP master from the plurality of PTP masters using the primary BMCA in the at least one hardware entity and transmit the best PTP master to a second entity for synchronizing a slave clock.

The present disclosure relates to a device and a communication method for appropriately determining: the timing and the frequency of an R2D signal used for CFO calibration; and the detection of the R2D signal used for the CFO calibration. The device, which has lower complexity than a Narrow Band Internet of Things (NB-IoT) device, comprises: a reception unit that receives a reception signal including control information from a wireless communication device; and a control unit that determines which sequence / pattern / length is to be detected from a signal of a clock acquisition part of the reception signal on the basis of the control information in the reception signal. The control unit determines to use a signal of the sequence / pattern / length detected from the clock acquisition part for timing calibration and calibration of a carrier frequency offset.

Provided in the embodiments of the present application is a data transmission method, which is applied to any intermediate node in a networking system and comprises: receiving a target packet, wherein a destination node of the target packet is different from the intermediate node, and the target packet is a packet used for time synchronization; and after a first duration from the start of receiving the target packet, sending the target packet to a downstream node of the intermediate node. Because the intermediate node sends the target packet to the downstream node of the intermediate node after the first duration from the start of receiving the target packet, a processing delay of the intermediate node for the target packet is fixed, making receiving and sending processing delays of the intermediate node symmetrical. Thus, when target packets used for time synchronization are exchanged between a master clock node and a slave clock node via an intermediate node, it can be ensured that uplink and downlink transmissions between the master clock node and the slave clock node are symmetrical, thereby simplifying a time synchronization process and achieving accurate time synchronization.

A serial interface comprising an I / O cell communicates serial data from a target device to an initiator device. The I / O cell comprises a clock pad that receives a clock signal from the initiator device; a data pad that receives a data output signal from the target device; and a clock input buffer coupled to the clock pad. A flip-flop integrated in the I / O cell receives the clock signal directly from the clock input buffer, receives the data output signal from control logic of the target device, and outputs the data output signal in synchronization with the clock signal. A data output buffer receives the data output signal from the flip-flop and drives the data output signal to the data pad for access by the initiator device.

The invention discloses an Ethernet clock phase synchronization method and a related device, and the method comprises the steps: obtaining a sending timestamp and a receiving timestamp through a time synchronization protocol, and calculating the time offset between a master clock and a slave clock according to the sending timestamp and the receiving timestamp; a delay configuration signal including the transmit and receive path delay control value is then generated. Control values are respectively input to programmable delay arrays on a sending path and a receiving path, and the number of unit delay units through which clock signals pass is dynamically controlled, so that the phases of a sending clock and a receiving sampling clock are accurately adjusted. According to the method, a circuit structure with unit delay time is utilized, refined dynamic compensation of the clock phase is achieved, and Ethernet clock synchronization precision and system data transmission reliability are effectively improved.

The present techniques relate to voltage droop detection and there is disclosed circuitry for detecting a voltage droop event, the circuitry configured to: receive a clock signal from a clock distribution network; obtain, from a storage, a first predetermined value, a second predetermined value and a predetermined threshold count; obtain one or more measurement values associated with a system voltage; when a first measurement value of the one or more measurement values reaches the first predetermined value, initiate a count of clock cycles until a subsequent measurement value of the one or more measurement values reaches the second predetermined value, the second predetermined value being different from the first predetermined value; and when the count of clock cycles is lower than the predetermined threshold count, cause a control entity to take mitigation action.

The application discloses a kind of multi-modal wearable sensor data fusion-oriented timing synchronization method, system, terminal and storage medium, the method includes: obtaining absolute timestamp as global clock source;Global clock source is as the master clock of precision time protocol, a plurality of wearable sensors are configured as slave clock, through precision time protocol, multiple rounds of message interaction are performed between master clock and slave clock, and the timestamp corresponding to each round of interaction is obtained;According to the corresponding timestamp, the current path delay and the current clock offset are calculated, and according to the preset path delay threshold and clock offset threshold, the current path delay and the current clock offset are iteratively judged, whether the local clock is corrected according to the current clock offset is determined according to the iterative judgment result, until slave clock and global clock source achieve timing synchronization;After achieving time synchronization, the periodic data sampling tasks of a plurality of wearable sensors are phase-aligned.The application significantly improves timing synchronization accuracy.

The invention discloses a time-sensitive network clock synchronization recovery method and device, equipment, a storage medium and a product, and the method comprises the steps: switching a predetermined candidate master clock into a master clock in response to the abnormality of the master clock; a synchronization message is sent through the master clock, the synchronization message comprises a newly added slave clock hopping field, whether first synchronization is carried out or not is judged through each slave clock according to the first synchronization identifier, if yes, whether the value of the slave clock hopping field is a first preset value or not is judged, and if yes, a candidate master clock notification is broadcasted through the slave clock; judging whether the value of the local slave clock hopping field is a first preset value or not through each slave clock, and if so, determining a candidate master clock according to the performance parameter of the slave clock included in the candidate master clock notification and the local parameter; if not, determining that the slave clock corresponding to the notification is a candidate master clock; by pre-determining the candidate master clock, the master clock can be quickly switched when the master clock is abnormal, so that the continuity and reliability of clock synchronization of the time-sensitive network are guaranteed.

Frames of a first and second type with a common preamble that are periodically transmitted by a master device (200) are received at a slave device (100) that is maintained in a low powered mode, and periodically set in a higher-powered mode to receive and process the received frames based on a slave clock (130) in a period prior to an expected transmission of the common preamble of each frame from the master device (200) to detect a preamble extension of a frame of the second type in the period. The slave device (100) returns to a low powered mode when no preamble extension is detected in the period. Information is received from and / or transmitted to the master device (200) by the slave device (100) when a preamble extension is detected. The slave device (100) is returned to the low powered mode after the information has been received and / or transmitted.

The application relates to an anti-single-event multi-bit upset latch circuit, which comprises a clock control inverter circuit controlled by clock signals CK1 and CK2 to be turned on or turned off, and data signals are transmitted to a latch unit when the clock control inverter circuit is turned on; the latch unit receives the data signals from the clock control inverter circuit and performs the latching of the data signals through the control of the clock signals CK1 and CK2; an SEU monitoring unit monitors whether a single-event upset occurs at a data sensitive node in the latch unit, and if the single-event upset occurs at the monitored latch unit, the data channel is switched to other latch units through a chip selection control unit; the chip selection control unit controls the opening or closing of the output of the latch unit according to the monitoring result of the SEU monitoring unit; and an inverter circuit inverts the data signals output by the chip selection control unit or the clock signals; the application has good single-event hardening capability and can realize the anti-single-event multi-bit upset.

The application relates to a communication method, a vehicle-mounted communication device and infrastructure for vehicle networking. The method comprises the following steps: selecting a clock module of a plurality of vehicle communication devices as a master clock module, and taking the clocks of the plurality of vehicle communication devices as slave clocks; based on the master clock of the master clock module and the slave clocks, calculating the deviation between the master clock and the slave clocks, and the time delay of at least one available communication path of the vehicle communication device; and selecting the communication path with the minimum time delay for communication. The embodiment of the application can realize high-precision time synchronization of the master clock and the slave clock, and minimize the communication time delay between nodes in vehicle networking.

An integrated circuit (IC) includes a clock modulation circuitry including a delay hierarchy circuitry coupled to the register, the delay hierarchy circuitry configured to receive a clock (CLK) signal, provide a delayed master clock (CLKM) signal to a master latch of the register, and provide a delayed slave clock (CLKS) signal to a slave latch of the register.