609 results about "Slave clock" patented technology

Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).

A system and method for time synchronization on a network is provided. According to the system and method for time synchronization, a slave clock device does not continuously receive a time synchronization message periodically transferred from a master clock device and thus does not correct its time upon all such occasions. Rather, the slave clock device requests time information from the master clock device only when the slave clock device needs to correct its time, and receives a time synchronization message transferred from the master clock device and compensates for its time deviation only while the slave clock device is activated, thereby reducing its power consumption and amount of computation.

Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.

The invention discloses a method and a device for synchronizing a master clock and a slave clock, the method comprises: sending synchronous request message to the master clock for many times in a simultaneous cycle by the slave clock, recording the corresponding the time value, then, utilizing a median average filtering algorithm to obtain the optimum time migration amount, utilizing the time migration amount to adjust the slave clock, eliminating the delay inequality which is caused by stochastic disturbance and burst interference of a network communication channel between the master clock and the slave clock, guaranteeing the stability of slave clock signals, and increasing the synchronous preciseness of the master clock and the slave clock.

The invention discloses a method for realizing accurate time synchronization by utilizing an IEEE1588 protocol, comprising the following steps: a) a Sync message is transmitted to a slave clock by a master clock, a transmission timestamp TM1 and a receiving timestamp TS1 of the message are acquired by the slave clock; b) a Delay_Req message is transmitted to the master clock by the slave clock, and a transmission timestamp TM2 and a receiving timestamp TS2 of the message are acquired by the slave clock; c) transmission delay and time offset are calculated by the slave clock according to the timestamp; and d) the calculated Offset is corrected in a fixed adjustment frequency in the correction time by the slave clock. The invention realizes accurate time synchronization, calculates time offset and self-compensate through the slave time clock in a packet based network, and leads the slave clock to lock the master clock whether in clock frequency or on the clock time in a shorter time, and occupies little hardware resources.

An exemplary method of synchronizing a master clock and a slave clock comprises transmitting a plurality of packets between a master device and a slave device, calculating a first skew between a first pair of the plurality of packets at the slave device and a second skew between the first pair at the master device, calculating a ratio between the first skew and the second skew, providing a slave clock frequency correction to the slave device, calculating a first packet trip delay using a time that the master device initiates sending a packet to the slave device, a time the master device receives a response from the slave device, a corrected time the slave device receives the packet, and a corrected time the slave device initiates sending the response, calculating a first offset based on the first packet trip delay, and providing the first offset to the slave device.

A first level of control over operation of slave Digitally Controlled Frequency Selectors (DCFSs), such as DCOs or DDSs, may occur by periodic transmission of control words from the master clock to the slave clocks. To allow enhanced control over the output of the slave clocks, the frequency of the local oscillator used to generate the synthesized output of the master clock may also be conveyed to the slave clocks to allow a second level of control to take place. The second level of control allows the local oscillators at the slave clocks to lock onto the frequency of the master local oscillator to thereby allow the slave local oscillators to operate the slave DCFSs using the same local oscillator frequency. The first level of control synchronizes operation of the DCFSs while the second level control prevents instabilities in the local oscillators from causing long term drift between the slave and master clock outputs. Timestamps may be used to synchronize the master and slave local oscillators.

The invention relates to a real-time synchronization method based on PTP precision clock synchronization protocol of IEEE1588. The research on hardware of IEEE1588 protocol is still a blank at present. The method of the invention includes the following steps: sending messages; receiving messages; correcting the local system time; selecting the optimal master clock. And the synchronization action is different when the corresponding equipment is a master clock or a slave clock. The hardware method reduces the inherent fluctuation of data transmission time of internet technology, while not affecting the scope of precision control, thus resolving the problem of the clock uniformity and precision in a distributed network system.

Touch sensing can be accomplished using master/slave touch controllers that transmit drive signals to a touch surface and process sense signals including superpositions resulting from master/slave drive signals. The master/slave can drive and sense different sets of lines, respectively, of the touch surface. A communication link between master/slave can be established by transmitting a clock signal between master/slave, transmitting a command including sequence information to the slave, and initiating a communication sequence from the clock signal and sequence information. The slave can receive/transmit communications from/to the master during first/second portions of the communication sequence, respectively. Touch sensing operations can be synchronized between master/slave by transmitting a command including phase alignment information from master to slave, and generating slave clock signals based on the clock signal and the phase alignment information, such that sense signal processing by master clock signals are in-phase with sense signal processing by slave clock signals.

This invention relates to methods and devices for time synchronization. The invention has particular application in the alignment of slave clocks to a master clock and in dealing with packet delay variation and dynamic asymmetries in the network links between them. In embodiments of the invention, the slave clock uses the peer link delay and residence times measured by peer-to-peer transparent clocks to compensate for clock synchronization errors that arise due to variability in message transfer delays. Embodiments provide a simple linear approximation technique and a Kalman filter-based technique for estimating offset and skew of the slave clock.

The invention discloses a time synchronization method and a time synchronization system for synchronous messages of IEEE1588 master-slave clocks of an intelligent transformer substation. The method comprises the following steps of: establishing a master clock synchronous message, and sending the timestamp t1 of the sending moment of the message to the clock in a broadcasting manner; recording a receiving moment t2 of the master clock synchronous message; recording an absolute receiving moment TT2 when the master clock synchronous message is received by a slave clock; establishing a slave clock responding message, sending the slave clock responding message to the master clock in a peer-to-peer manner, and recording the timestamp t3 of the sending moment of the message; recording an absolute sending moment TT3 when the slave clock sends the clock responding message; recording an acquiring moment t4 when the master clock acquires the message; calculating a time deviation, and calculating asymmetry errors according to the timestamp t1, the absolute receiving moment TT2, the absolute sending moment TT3 and the acquiring moment t4; and carrying out time correction on the slave clock by the time deviation and the asymmetry errors. According to the time synchronization method and the time synchronization system for synchronous messages of IEEE1588 master-slave clocks of the intelligent transformer substation, the influences of the asymmetry errors can be eliminated, and the time synchronization precision of the master-slave clocks is improved.

The invention discloses a clock synchronization method in a transmission network. The method comprises the steps of obtaining the arrival time t2 and the sending time t1 of first message through the interaction of a slave clock and a master clock; adopting external clock source to detect the time delay of the master clock and the salve clock; seeking clock error Offset according to the time delay between the master clock and the slave clock, t1 and t2; and adjusting the clock of the slave clock according to Offset. The invention further discloses a clock synchronization method in other two transmission networks, and also discloses a clock synchronization system of three transmission networks. The clock synchronization method of the invention can accurately calculate clock error Offset, thereby ensuring the synchronization of the slave clock and the master clock.

Network timing synchronization for virtual machine (VM) host systems and related methods are disclosed that provide synchronization of master/slave clocks within VM host hardware systems. Master timing messages are sent from the master clocks to slave clocks within VM guest platforms hosted by the VM host hardware system within a virtualization layer, and return slave timing messages are communicated from the VM guest platforms to the master clock. Virtual switches within the virtualization layer use virtual transparent clocks to determine intra-switch delay times for the timing packets traversing the virtual switch. These intra-switch delay times are then communicated to target destinations and used to account for variations in packet transit times through the virtual switch. The VM guest platforms synchronize their timing using the timing messages. The master/slave timing messages can be PTP (Precision Time Protocol) timing messages and/or timing messages based upon some other timing protocol.

An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop comprises a primary loop having a first frequency error estimator for generating a first estimate of error between the master and slave clock frequencies, a second frequency error estimator outside of the primary loop for generating a second estimate of error between the master and slave clock frequencies, and an accumulator coupled between the second frequency error estimator and the primary loop. The second estimate is controllably injected into the primary loop via the accumulator.

A multiprocessor computer system comprises multiple data processors, each with an internal clock for providing time stamps to application software. The processors take turns as synchronization masters. The present master transmits a “request” time stamp (indicating the time of transmission according to the local clock) to the other (“slave”) processors. Each slave processor responds by returning a “response” time stamp (indicating the time of transmission of the response according to the local slave clock) of its own along with the received request time stamp. The master calculates clock adjustment values from the time of receipt of the responses and the included time stamps. This allows asynchronous clocks to be synchronized so that application time stamps can be validly compared across processors.

A method for realizing high precision time synchronization among synchronous digital hierarchy (SDH) equipment includes the step: a piece of SDH equipment as a slave clock and a piece of SDH equipment as a master clock use the idle bytes in section overhead of an SDH frame to conduct the interaction of PTP messages, the time difference between the slave clock and the master clock is calculated and the time difference is utilized to calibrate the slave clock. And a system for realizing high precision time synchronization among SDH equipment includes: the SDH equipment as the slave clock and the SDH equipment as the master clock. The slave clock uses the idle bytes in section overhead of the SDH frame to conduct the interaction of PTP messages with the master clock and calculates the time difference with the master clock, and then the time difference is used to calibrate the slave cock. The master clock uses the idle bytes in section overhead of the SDH frame to conduct the interaction of PTP messages with the slave clock. The adoption of the method and the system can ensure that the high precision time synchronization among the SDH equipment is realized and satisfy the requirements of all mobile communication systems at the present stage.

The invention discloses a system for measuring network clock synchronization, is applied to the communication and smart grid fields. The system comprises a pulse countering module, a time counting module, a clock reference module and a synchronization calculation module, wherein the pulse counting module calculates pulse frequency difference between a master clock and a slave clock, the master clock is synchronous with a remote reference clock, and the slave clock is synchronous with the master clock through a network so as to be synchronous with the remote reference clock; the time counting module measures the time difference between the master clock and the slave clock; the clock reference module inputs a reference clock, and the reference clock is synchronous with the remote reference clock; and the synchronization calculating module is used for calculating network clock synchronization parameters according to the time difference and the pulse frequency difference and outputting time synchronization parameters. The system disclosed by the invention can be used for evaluating the clock frequency synchronization accuracy and the time synchronization accuracy which can be reached at each node by an IEEE1588PTP (Institute of Electrical and Electronics Engineers 1588 Peer To Peer) clock synchronous network, and important reference data is provided for clock synchronization network optimization, and performance prediction on application and equipment depending on clock synchronization.

The invention discloses an IEEE 1588 accurate clock synchronization protocol-based synchronization system and a synchronization method thereof in the technical field of wireless communication. The system consists of master equipment and slave equipment which are connected through a network, wherein the master equipment comprises a main clock module and a central processing unit (CPU) management control module; and the slave equipment comprises a slave clock module and a CPU management control module. Due to the adoption of a frequency compensation clock provided by Balasubramanian and the like, a frequency adjustable clock counter is constructed and the frequency compensation function is realized; and an improved clock synchronization method is adopted, the limited machine precision of anembedded system, namely influence brought by truncation errors is considered; therefore, higher clock synchronization accuracy is achieved.