211 results about "Slave clock" patented technology

The invention discloses a clock tree synthesis method and related equipment, and the method comprises the steps: dividing a plurality of time sequence units which need to receive clock signals from a clock source into clustering clusters of different levels, and enabling the load capacitance of each clustering cluster of the same level to be balanced; according to a hierarchical sequence of clusters starting from the clock source, taking each cluster as a node of a clock tree, recursively constructing the clock tree, and inserting a target buffer at the position of each node for driving the corresponding node; analyzing the delay and offset of the constructed clock tree to obtain an analysis result; and if the analysis result indicates that the delay and offset of the clock tree do not meet the preset constraint condition, adjusting the clock tree until the adjusted delay and offset of the clock tree meet the preset constraint condition. According to the technical scheme, power consumption and offset can be effectively reduced, calculation efficiency and design reliability are improved, and the method is suitable for high-performance chip design under the advanced technology.

The invention discloses a synchronization method and device for time synchronization of a network system, and relates to the technical field of computers, and the method comprises the following steps: when a master station sends a dynamic compensation synchronization frame, recording a compensation sending timestamp in a sensing identification field of a sending end; when the frame is received and transmitted from the station, the identification field is sensed at the port to determine a compensation receiving timestamp and a compensation transmitting timestamp. And the slave station identifies the dynamic compensation synchronization frame after reverse return, calculates dynamic compensation time information based on the compensation receiving timestamp and the compensation sending timestamp corresponding to the slave station, and reads and writes the dynamic compensation time information to a corresponding field. And the master station analyzes the returned dynamic compensation synchronization frame, aggregates the dynamic compensation time information of each slave station, and solves the dynamic compensation values of the master and slave stations in combination with the fixed link delay. And the master station corrects a local high-precision clock according to the data, and writes a compensation value into a local time correction register of the slave station to trigger a hardware counter to correct so as to complete synchronization of the master and slave clocks. By realizing dynamic residence separation, the problem of overlarge error is solved.

The invention provides a time synchronization method based on an IEEE 1588 protocol, and relates to the technical field of time synchronization. Comprising the following steps: firstly, establishing a network-based master-slave clock model to characterize a clock frequency; secondly, acquiring a timestamp set of master and slave clocks of the current round, and calculating average transmission delay and time offset; thirdly, a clock synchronization equation of Kalman filtering is built based on a clock model, time offset and drift serve as input, an optimal time offset value is obtained, and a local clock is adjusted to complete synchronization of the current round. Then, a new timestamp set is obtained for the next round, the average transmission delay and the time offset are calculated, and the optimal offset value is determined through a Kalman filtering equation; meanwhile, the number of cycles is calculated according to the offset value and the receiving timestamp, and frequency compensation is carried out on the slave clock. According to the invention, the problem of low time synchronization precision in the prior art is effectively solved.

The invention discloses a wireless communication system and method based on an EtherCAT network. The system comprises a wireless gateway and a wireless slave station, the wireless gateway comprises an EtherCAT slave station module, a wireless communication module, a control module and an auxiliary function module. The control module carries out packaging conversion on an EtherCAT frame received by the EtherCAT slave station module and a wireless frame of the wireless communication module through hardware-level protocol conversion; the wireless communication module is an FHSS module or a WiFi module. The auxiliary function module comprises a timestamp module for recording time information and is used for assisting the control module to perform master-slave clock synchronization by adopting a multi-stage distributed clock synchronization optimization algorithm; the wireless slave station comprises an EtherCAT slave station module, a wireless communication module and a local control unit, wherein the EtherCAT slave station module is used for receiving the control instruction of the EtherCAT master station and is compatible with the wireless gateway; the wireless communication module is used for uploading a wireless frame packaged with an EtherCAT sub-message and has the same model as the wireless frame; and the local control unit is used for analyzing the control instruction of the EtherCAT master station to collect local data and packaging the local data into the EtherCAT sub-message. According to the invention, requirements of industrial automation on high-precision and high-reliability wireless communication can be met.

The invention relates to the technical field of clock synchronization, in particular to a clock synchronization method of a master station system based on EtherCAT, which comprises the following steps: when a master station periodically sends time synchronization frames to all slave stations, collecting slave station feedback time data, respectively calculating a clock offset value between master time and slave time, and simultaneously, calculating a clock offset value between the master time and the slave time; constructing a master-slave offset time feature matrix according to the collected multi-periodic data, extracting initial static offset, an offset fluctuation trend and offset collaboration features among multiple slave stations from the constructed master-slave offset time feature matrix, and determining an initial estimation set according to the extracted features; constructing a master-slave offset prediction set based on the initial estimation set, and performing master-slave clock offset adaptive compensation correction based on the determined master-slave offset prediction set; according to the method, the initial offset estimation set is constructed, the offset trend estimation function is introduced, secondary fitting of the offset sequence of each slave station node is achieved, and it is ensured that the prediction precision is remarkably improved through an error comparison mechanism.

Systems and methods for supporting multiple data rates are presented. A method includes generating a clock signal from a clock source, serializing, by an analog serializer, a data stream in response to the clock signal to output N data in parallel, coupling a pulse generation circuit to the clock signal, wherein a first switch and a second switch electrically communicate with the pulse generation circuit, and coupling a multiplexer to the pulse generation circuit, wherein the multiplexer receives the N data from the analog serializer and selects a subset of the N data when switching operation of the electronic circuit from a first mode to a second mode.

The invention discloses a filtering adjustment method and system based on an adaptive clock, and relates to the technical field of filtering adjustment, and the method comprises the steps: carrying out the time domain framing processing of a collected input signal through employing a sliding window, and combining DCT and compressed sensing to reconstruct the signal, and the main frequency of the signal and the dynamic change of the main frequency in the time sequence are accurately extracted through FFT, Gaussian pyramid layering and a multi-scale optical flow method, so that the frequency identification capability of the non-stationary signal is effectively enhanced, the frequency spectrum resolution is ensured, the data processing amount is remarkably reduced, the response speed of the signal frequency change is improved, and the method is suitable for popularization and application. Through the main-sub clock structure, the quick response of the center frequency of the filter to the change of the main frequency is ensured, the selectivity of the filter and the signal fidelity are improved, through the compensation adjustment of environmental factors, the influence of temperature and voltage changes on signal processing can be effectively reduced, and the robustness and stability of the system are enhanced.

The invention discloses a power grid time frequency change trend prediction method and system based on intelligent electric meter data fusion, and the method comprises the steps: measuring the network transmission delay and time deviation between a master clock and a slave clock of a power grid, obtaining an initial time frequency deviation sequence, carrying out the error calibration, carrying out the data fusion after time domain alignment, and carrying out the prediction of the time frequency change trend. Generating a fusion time sequence; performing recursive estimation on the fusion time sequence, outputting an optimal time frequency deviation sequence, and performing synchronous estimation to obtain a clock phase error, a frequency error and frequency drift as state characteristic quantities; and training a preset machine learning prediction model by taking the optimal time frequency deviation sequence as a supervision signal and taking the state characteristic quantity of the corresponding moment as input, and obtaining a prediction result of the power grid time frequency change trend in the future period based on the trained time frequency change trend prediction model. According to the method, the power grid time synchronization precision and prediction capability are remarkably improved, and reliable technical guarantee is provided for stable operation of a power system.

The invention relates to the field of data acquisition, in particular to a multi-sensor integrated special vehicle modular data acquisition device and system, the device comprises a switch, and a master clock module, a plurality of slave clock modules and a task computer which are respectively connected with the switch, and the master clock module is used for tracking the frequency and time of a GNSS (Global Navigation Satellite System) satellite; the plurality of slave clock modules are synchronized with the master clock module, each slave clock module comprises a trigger controller and an inertial measurement unit, and the plurality of slave clock modules form a distributed clock and are used for coordinating and accurately triggering a plurality of sensors and realizing hardware triggering or capturing a hardware timestamp on each sensor; the task computer is used for collecting data of multiple sensors and carrying out consistency calculation on hardware timestamps. Compared with the prior art, the device has the advantages that nanosecond clocks of multiple sensors are accurately synchronized, different trigger sources are adopted for different sensors, and the stability of the acquisition device is improved.

The invention discloses a time sequence synchronization method and system for data fusion of a multi-modal wearable sensor, a terminal and a storage medium. The method comprises the following steps: acquiring an absolute timestamp as a global clock source; taking the global clock source as a master clock of a precision time protocol, configuring the plurality of wearable sensors as slave clocks, and executing multiple rounds of message interaction between the master clock and the slave clocks through the precision time protocol to obtain a timestamp corresponding to each round of interaction; and calculating the current path time delay and the current clock offset according to the corresponding timestamps, carrying out iterative judgment on the current path time delay and the current clock offset according to a preset path time delay threshold value and a preset clock offset threshold value, and determining whether to correct the local clock according to the current clock offset according to an iterative judgment result. The slave clock and the global clock source achieve time sequence synchronization; and after time synchronization is achieved, phase alignment is carried out on the periodic data sampling tasks of the multiple wearable sensors. According to the invention, the time sequence synchronization precision is obviously improved.

The invention provides a clock synchronization method, a multi-axis drive control system and a computer storage medium, and the method comprises the steps: obtaining a clock synchronization signal which is sent by a master station timer and has a matched period at a slave station end, selecting any timestamp in the clock synchronization signal as a reference point, and carrying out the clock synchronization based on the reference point, determining the corresponding position of the reference point in the counting signal of the local timer, mapping the time information of the master station to a local time axis of the slave station, and calculating the phase difference between the corresponding position of the reference point in the counting signal of the local timer and the starting position of the next period of the counting signal of the local timer, and quantizing the real-time deviation of the master and slave clocks, and finally, dynamically adjusting and updating the period of a counting signal of a local timer to eliminate the phase difference, so that the slave station clock period is kept synchronous with the master station, and the time consistency of the action of each slave station in the multi-axis driving system is ensured.

The invention discloses a multi-modal data high-precision time synchronization acquisition system and method based on Syntaclos, and relates to the technical field of time synchronization, the system comprises a target determination module, a time division module, an index establishment module, a state evaluation module and a time synchronization module; the method is technically characterized by comprising the following steps: sending a time synchronization message to slave clock equipment through master clock equipment, extracting time granularity, dividing time partitions, establishing a corresponding time partition index for each time partition, and outputting a prediction index table through a synchronous topology network; determining an initial time partition of the multi-modal data based on the prediction index table, introducing a machine learning model, building a rule engine, analyzing the degree of influence, predicting a next time partition with deviation, marking a time deviation event once, and performing synchronous processing on the detected time deviation event in a Syntacalos synchronization interface; the time synchronization efficiency is improved, and time synchronization errors are reduced.

The invention relates to the technical field of testability design, and discloses an on-chip clock controller and test equipment, the on-chip clock controller comprises a main clock control circuit, the functional clock input end of the main clock control circuit is connected with a phase-locked loop output clock, and the clock output end of the main clock control circuit is connected to a main frequency domain receiving node so as to output a main frequency clock signal to the main frequency domain receiving node; the functional clock input end of the slave clock control circuit is connected with the clock output end of the master clock control circuit, and the clock output end of the slave clock control circuit is connected to a frequency division domain receiving node so as to output a frequency division clock signal to the frequency division domain receiving node; wherein the master clock control circuit and the slave clock control circuit are controlled by external slave enable signals, and a data interaction channel is arranged between the master frequency domain receiving node and the frequency division domain receiving node. By cascading the master clock control circuit and the slave clock control circuit and constructing the data interaction channel, dynamic collaborative testing of the master frequency domain and the frequency division domain is realized, and the problem of delay fault detection of the multi-frequency-domain integrated circuit is solved.

Embodiments of this application provide a clock synchronization method and an apparatus. The clock synchronization method is applied to a slave node. The clock synchronization method includes: receiving a synchronization packet sent by a master node, where the synchronization packet carries a master clock timestamp of the master node; establishing a mapping relationship between a master clock of the master node and a reference timescale of the slave node based on the master clock timestamp and a timestamp corresponding to a reference timescale of the slave node when the slave node receives the synchronization packet; obtaining a time combination of the timestamp corresponding to the reference timescale of the slave node and slave clock time of the slave node, where a collection moment of the reference timescale of the slave node and a collection moment of the slave clock time corresponding to the reference timescale are the same.

The invention discloses a task synchronization and scheduling method for compensating CAN bus clock drift, which relates to the technical field of industrial automation control, and comprises the following four steps: initializing a system, loading a real-time protocol stack, completing hardware self-inspection and clock calibration, and sending a ready signal after confirming that a link is smooth; performing synchronization parameter configuration and task planning, defining clock synchronization reference parameters, dividing four types of tasks and setting priorities; performing dynamic calibration and data buffering on master and slave clocks, broadcasting a synchronous message with a timestamp by a master station, correcting a local timer by a slave station through a soft phase-locked loop, and constructing an annular buffer area to realize time domain decoupling; task cooperative scheduling and abnormal fault tolerance are carried out, a control task is triggered based on a calibration clock, edge calculation is carried out to reconstruct a motion state and feed-forward compensation is carried out, a multi-dimensional state is monitored in real time, and a fault tolerance mechanism is triggered. According to the method, clock synchronization precision and control stability are greatly improved, bus bandwidth limitation is broken through, high dynamic tracking precision is achieved, and long-term stable operation of the system is guaranteed.

The invention discloses a periodic synchronous position interpolation control method and system for a servo driver, and relates to the technical field of servo control, and the method comprises the steps: receiving a synchronous position instruction at a fixed bus period, and recording a theoretical / actual arrival timestamp of the synchronous position instruction; converting the instruction into a position increment and storing the position increment into a buffer; calculating a cache saturation index reflecting instruction stream supply and demand balance in real time; based on the index and the change trend, dynamically calculating and smoothly adjusting a next position loop sampling period through a feedback control model; position loop processing is triggered in the post-adjustment period. According to the invention, by monitoring the instruction stream state and adaptively adjusting local processing, the influence caused by master and slave clock skew and network jitter is compensated, and continuous and uniform instruction input is ensured to be always obtained by a position ring, so that high-stability and high-precision motion control under bus communication is realized, and the anti-interference capability and the synchronization performance of the system are improved.

The invention discloses a PTP clock synchronization implementation method based on sliding mode control calibration, and the method comprises the steps: designing master and slave clock synchronization equipment, designing a slave clock into two DP83640 pieces for eliminating the problem of insufficient adjustment resolution of a local clock of a single chip, calculating the clock deviation through message transmission by the master and slave clocks, and carrying out the initial adjustment and compensation of the local clock, after preliminary adjustment is completed, a high-precision time interval counter is used for finely measuring master-slave clock skew, the master-slave clock skew is input into a designed sliding mode controller to generate a calibration control quantity, the clock skew is finely calibrated according to the calibration control quantity, and more accurate clock synchronization is completed. Experimental results show that the method provided by the invention can realize synchronization precision superior to 300ps, and has great reference value.

The present invention relates to the field of data acquisition, and in particular to a modular data acquisition device and system for special vehicles that integrates multiple sensors. The device includes a switch, a master clock module, multiple slave clock modules, and a mission computer, each of which is connected to the switch. The master clock module is used to track the frequency and time of GNSS satellites; the multiple slave clock modules are synchronized with the master clock module, each of which includes a trigger controller and an inertial measurement unit. The multiple slave clock modules constitute a distributed clock for coordinated and precise triggering between multiple sensors, implementing hardware triggering or capturing hardware timestamps on each sensor; the mission computer is used to collect data from multiple sensors and perform consistency calculations on the hardware timestamps. Compared with the existing technology, the present invention has the advantages of achieving precise nanosecond-level clock synchronization of multiple sensors, using different trigger sources for different sensors, and improving the stability of the acquisition device.

The application discloses a clock tree synthesis method and related equipment, including: dividing a plurality of timing units needing to receive a clock signal from a clock source into clustering clusters of different levels, wherein the load capacitances of each clustering cluster of the same level are balanced; according to the level order of the clustering cluster starting from the clock source, taking each clustering cluster as a node of a clock tree, recursively constructing the clock tree, and inserting a target buffer at the position of each node for driving the corresponding node; analyzing the delay and offset of the constructed clock tree to obtain an analysis result; if the analysis result indicates that the delay and offset of the clock tree do not satisfy a preset constraint condition, adjusting the clock tree until the delay and offset of the adjusted clock tree satisfy the preset constraint condition. The technical scheme of the embodiment of the application can effectively reduce power consumption and offset, improve computing efficiency and design reliability, and is suitable for high-performance chip design under advanced process.

The invention relates to the technical field of current transformer calibration equipment, and discloses a current transformer calibration device and a detection method. An integrated controller, a signal generation module, a data processing unit, a man-machine interaction unit, a signal processing unit, a communication relay unit and an error calculation module are arranged in the device, and a master-slave clock distributor is arranged in the communication relay unit. And the detection probe is internally provided with a plurality of current sensors, and each current sensor has a broadband response characteristic. The design is reasonable, the multi-station mutual inductor fixing clamp is in linkage with the bevel gear set through the driving motor, the driving shaft and the spiral groove connecting cylinder are driven to achieve synchronous rotating propelling, and the rotating frame and the arc-shaped connecting rod are matched to drive the clamping plate to retract in a self-adaptive mode. According to an original constant force control mechanism, after the clamping plate makes contact with the mutual inductor, the balance weight mechanism is triggered through axial displacement of the connecting cylinder to dynamically balance pressure, and it is ensured that constant clamping force is applied to all stations.

Techniques include receiving a message with time information from a clock leader by a clock follower in a time-synchronized network (TSN), the time information to synchronize a clock to a network time for the TSN, retrieving an actual time offset value for the message, the actual time offset value to comprise a value between an actual sending time and an actual receiving time of the message, retrieving an estimated time offset value for the message, the estimated time offset value to comprise a value between an estimated sending time and an estimated receiving time of the message, the estimated time offset value generated using a physics-aware model of the TSN and a clock adjustment value for the clock based on the time information, and determining whether the time information for the message was modified to cause the clock to desynchronize based on difference information. Other embodiments are described and claimed.

The invention relates to the technical field of wireless communication networks, and particularly discloses a high-robustness PTP time synchronization method and system for a wireless Mesh network. According to the method, global topology information and real-time link quality information of a wireless Mesh network are obtained through a centralized network controller, an optimal end-to-end synchronization path is dynamically calculated for a slave clock node, an intermediate node on the path performs residence time accumulation correction in a transparent clock mode, high-precision end-to-end synchronization of a slave clock and a master clock is realized, and the synchronization precision of the slave clock and the master clock is improved. And the synchronization stability is ensured through continuous monitoring and seamless switching of a backup path. The system comprises a centralized network controller, a PTP master clock and a plurality of enhanced Mesh nodes. According to the method, the problems of poor dynamic topology adaptation, large transmission delay jitter, multi-hop error accumulation and the like of a standard PTP protocol in a wireless Mesh network are solved, the synchronization precision and robustness are remarkably improved, and a core support is provided for deterministic scheduling of a wireless TSN network.

A method of synchronization of a slave master clock of a set of slave equipment with a master main clock of a set of master equipment, on the basis of a common time base, including receiving, by the master equipment and by the slave equipment, clock pulses from the common time base, performing, from the master equipment and the slave equipment, a master timestamping and a slave timestamping of clock pulses received on the basis of the common time base, on the base of the master and the slave main clocks, respectively, for generating the master and the slave timestamping information, communicating the master timestamping information to the slave equipment, and regulating, in the slave equipment, the slave main clock on the basis of the master timestamping information communicated and on the basis of the slave timestamping information generated.

The invention discloses an internal delay calibration method for a network time protocol measurement device, which comprises the following steps of: establishing a reference signal 1PPS as a unified time reference; sending a synchronous message and outputting message record receiving time; measuring the moment when the synchronous message is received, and outputting the actual receiving time; comparing the message record receiving time with the actual receiving time, and outputting the internal delay of a receiving path; the slave clock sends a delay request message, and outputs the message to record the sending time; measuring the moment of sending the request message, and outputting the actual sending time of the request message; comparing the message record sending time with the actual sending time, outputting the internal delay of a sending path, and separating a stable delay component; and taking the internal delay of the receiving path and the sending path as input, compensating the master-slave clock deviation, and outputting the real time deviation of the master-slave clock. According to the invention, internal delay calibration of the measuring device is realized.

The invention provides a multi-source data fusion state estimation method, device and equipment, and relates to the technical field of state estimation, and the method comprises the steps: S1, collecting original observation data from N heterogeneous sensors, writing a local hardware timestamp for each piece of original observation data, and converting the timestamp into a second timestamp under a unified reference time base through master-slave clock bidirectional synchronization to obtain an original data stream with a unified time scale. According to the multi-source data fusion state estimation method, device and equipment, sensor time delay is used as an explicit variable for online estimation, and late data is digested by using an independent compensation channel. The main filter always runs according to a high-frequency beat without pause and rollback, and the end-to-end delay of the system is less than 5 milliseconds; the sliding window can be dynamically expanded, the delay error is converged to a sampling interval through correlation sampling interpolation, and the state precision is improved by about 30% compared with that of a traditional loose coupling method.

The invention belongs to the field of bus communication, and provides a bus communication packet orderly self-adaptive transmission method and system. The method comprises a communication starting stage; in the pre-communication stage, the host sends a detection packet to the slave to identify whether a conflict detection sequence error exists or not; when a certain slave has a conflict detection sequence error, gradually increasing the first byte response time by taking the transmission time of each byte of the slave as a unit until the conflict disappears and updating the slave response time linked list; in the communication operation stage, the host requests response communication with the multiple slaves, when a conflict detection sequence error of a certain slave exists in the communication operation process, the host synchronizes the slave clock again by sending a synchronization packet, if the conflict detection sequence error disappears, the communication returns to normal, otherwise, the host sends a response pause request, and the slave clock resynchronizes the slave clock again by sending the synchronization packet. And according to the current slave response time linked list, increasing the first byte response time of the slave, and updating the slave response time offset so as to re-establish the host to request the multi-slave response communication.

This time synchronization device comprises: an internal clock and a slave clock; a frequency synchronization unit that synchronizes the frequency of the internal clock with the frequency of the clock of a time master apparatus; a calculation unit that calculates a downlink delay time, which is the time difference between a packet transmission time from the time master apparatus and a packet reception time stamped by the internal clock, and an uplink delay time, which is the time difference between a packet transmission time stamped by the internal clock and a packet reception time at the time master apparatus; a prediction unit that predicts the shortest downlink delay time on the basis of the calculated downlink delay time and predicts the shortest uplink delay time on the basis of the calculated uplink delay time; and a time synchronization unit that synchronizes the time of the slave clock with the time of the clock of the time master apparatus on the basis of the predicted shortest downlink delay time and the predicted shortest uplink delay time.

The application discloses a linear topology slave node synchronization method and system based on IEEE 1588 precision clock protocol, and the method comprises the following steps: step one, slave node 1 to slave node n-1 accepts PTP messages from a master node and forwards the PTP messages to the next level; step two, slave node 1 to slave node n-1 accepts PTP messages from slave node n and forwards the PTP messages to the previous level; step three, slave node 1 to slave node n takes an average value of round trip time to obtain an average link delay; step four, the master-slave clock offset is calculated according to the average transmission delay; and step five, dynamic frequency compensation calculation is performed. The application can increase the synchronization accuracy of the system and effectively reduce the clock deviation between nodes in the distributed system of the linear topology structure.

This invention relates to a time synchronization method for 5G and TSN converged networks based on a timestamp compensation algorithm, belonging to the field of cross-network time synchronization. It includes: introducing a 5G network as a TSN virtual bridge into the TSN network to form a cross-network, which includes a TSN1 network, a 5G network, and a TSN2 network. The cross-network uses the TSN switches in the TSN1 network as the master clock and the TSN devices in the TSN2 network as slave clocks. Synchronization is achieved by transmitting time synchronization information step-by-step across the NW-TT module, the 5G network clock domain, and the DS-TT module. The cross-network time synchronization includes TSN2 network time synchronization, 5G network time synchronization, and TSN2 network time synchronization. This invention improves the accuracy of time synchronization by calculating the frequency offset and dwell time between NW-TT and DS-TT within the 5G system and performing time compensation in the DS-TT.

The invention relates to the technical field of LED display, in particular to an LED display control system. The LED display control system comprises a sending card and a plurality of cascaded receiving cards, and the sending card comprises a video input module, a video data protocol packaging module, a first network data module, a main protocol module and a main clock module. The receiving card comprises an LED video driving control module, a video data protocol unpacking module, a second network data module, a slave protocol module, a slave clock module and a video frame frequency clock module, and the sending card and the receiving card carry out data interaction through the first network data module and the second network data module. The moment when each LED display box body uses the video frame frequency clock to reach the moment contained in the message is used as the starting moment of the next video frame, so that the asynchronization and jitter of the refresh frame frequency between the LED display box bodies caused by the transmission delay and jitter of the data packet in the cascade network can be eliminated.