64 results about "Delay calculation" patented technology

The invention belongs to the technical field of video monitoring and image recognition, and particularly relates to a video monitoring transmission delay detection method and system based on image recognition, and the method comprises the steps: extracting image stable texture features through SIFT to generate a 128-dimensional descriptor, capturing an inter-frame motion trend through a Lucas-Kanade algorithm to generate a time feature, and carrying out the detection of the transmission delay of the video monitoring through the Lucas-Kanade algorithm. Finally, dynamic weighted fusion is carried out through an attention mechanism, and a space-time joint feature vector is generated; then, a dynamic template containing spatial-temporal characteristics and a local clock is generated at a sending end, cross-end matching is carried out at a receiving end by using an FLANN algorithm, the influence of network jitter and clock skew is eliminated through a double-calibration mechanism of basic time delay calculation, clock skew calibration and jitter compensation, and finally time delay after calibration is output; based on this, the method has the advantages of avoiding the interference of network jitter on the delay detection precision and reducing the delay standard exceeding false alarm condition caused by instantaneous deviation through the design of double-calibration delay calculation and cross-end feature accurate matching.

The invention discloses a virtual power plant rapid frequency modulation control system and control method, and the method comprises the steps: adaptively adjusting a sampling period through a dynamic sampling algorithm based on a sliding window variance; low-delay calculation of high-frequency data is realized by adopting a multi-thread queue communication technology; a multi-core ARM processor running a real-time operating system is used for executing a multi-thread control model, and data acquisition, algorithm control, fault diagnosis and communication tasks are processed in parallel; according to the control algorithm, frequency prediction feedforward signals based on an AI model and SOC state feedback are fused, and dynamic optimization of PID parameters is achieved. According to the method, millisecond-level frequency modulation response can be realized, the instruction response delay is less than 80ms, the frequency adjustment error is less than + / -0.01 Hz, the frequency modulation performance of a virtual power plant and the stability of a power grid are remarkably improved, and meanwhile, the service life of energy storage equipment is prolonged through SOC collaborative optimization. The invention aims to solve the problems of slow response and low precision of the existing frequency modulation technology.

The invention belongs to the technical field of laser precision machining and control, and particularly relates to a femtosecond laser single-point trigger control system and method based on subnanosecond synchronization, and the method comprises the following steps: S1, building a system synchronization clock locked with a femtosecond laser pulse signal phase; the specific mode of establishing the system synchronous clock is that phase locking is carried out on pulse synchronous signals or frequency division signals output by an internal high-frequency clock source and a femtosecond laser source through a digital phase-locked loop technology, and the low-jitter system synchronous clock which is strictly synchronous with a laser pulse sequence is generated. According to the invention, a system clock locked with a laser pulse phase can be generated through a digital phase-locked loop, and the influence of inherent frequency drift of a laser and circuit delay temperature drift is effectively overcome by combining real-time delay calculation based on a prediction algorithm and a high-resolution DDS delay line technology; the synchronization precision between the triggering moment of the single pulse and the external instruction is stabilized at the subnanosecond level, and the requirement of leading-edge application for the extreme time sequence precision is met.

The invention discloses a GPU cluster task scheduling method and device, equipment and a medium. The method comprises the following steps: constructing a task dependency graph in response to a to-be-scheduled task; obtaining a matched scheduling strategy according to the task characteristics of the to-be-scheduled task, marking a node type for each computing node in the task dependency graph, and determining an available GPU resource pool according to the scheduling strategy and the node type; generating all candidate GPU allocation schemes, and calculating an end-to-end execution delay of each candidate GPU allocation scheme by using a preset delay calculation model; and according to each end-to-end execution time delay and the scheduling strategy, selecting a target GPU allocation scheme from all the candidate GPU allocation schemes, so that a cluster resource manager schedules a target GPU cluster to execute the to-be-scheduled task according to the target GPU allocation scheme. According to the method, a closed loop from task analysis, resource screening to scheme optimization is formed, and the accuracy, efficiency and adaptability of GPU cluster task scheduling are improved.

Techniques are disclosed for computing a cost of an advertised route to a next-hop network device along a path to a destination based at least in part on a preference for the path. In one example, a computing system computes a cost of a route to a next-hop network device along a path to a destination. The computed cost is based at least in part on (1) a metric for the route and (2) a preconfigured preference for the path. In some examples, the preference for the path is based at least in part on (a) a type of the path as compared to other types of other paths to the destination or (b) a latency of the path as compared to other latencies of the other paths. The computing system sends a route advertisement for the route that includes data indicative of the cost of the route.

A direct memory access (DMA) device includes a controller, a read request issuing circuit, a read buffer temporarily storing read data and an arrival time of the read data, and a read buffer managing circuit that calculates an average bus latency and an average buffer residence time. The read request issuing circuit adjusts the issuing capability based on the average bus latency and the average buffer residence time. The DMA device operates by issuing a read request based on an issuing capability, storing an issuing time of the read request, receiving read data corresponding to the read request, temporarily storing the read data and an arrival time of the read data in a read buffer, calculating an average bus latency based on the issuing time of the read request, calculating an average buffer residence time, adjusting the issuing capability, and issuing the read request based on the adjusted issuing capability.

The invention provides a maximum delay calculation method and device and a computer readable storage medium, relates to the technical field of integrated circuits, and is used for solving the problem of how to improve the efficiency and precision of analyzing the maximum delay time of an integrated circuit. The computing method comprises: providing a circuit comprising a victim network and a plurality of aggressor networks; selecting one of a plurality of output nodes of the victim network as a representative node, and obtaining the maximum delay time of the representative node; according to the maximum delay time, obtaining initial maximum delay time of each output node except the representative node; the representative node is updated at least once, in each update, an output node is selected from the output nodes which are not used as the representative node from beginning to serve as the representative node, and the maximum delay time of the updated representative node is obtained; and according to the updated maximum delay time of the representative node, obtaining the maximum delay time of each output node which is not used as the representative node. The calculation method can be used for timing sequence verification of an integrated circuit.

The application discloses a kind of delay calculation method, equipment and computer readable storage medium, the delay calculation method includes: obtaining data receiving end sends pull stream request signaling Request signaling sending time and data sending end receives pull stream request signaling Request signaling receiving time;Obtain the response signaling sending time of data sending end sending pull stream response signaling and the response signaling receiving time of data receiving end receiving pull stream response signaling;Data sending time and data receiving time are obtained, data sending time is the time that data sending end issues transmission data, data receiving time is the time that data receiving end receives transmission data;Network delay is calculated using Request signaling sending time, Request signaling receiving time, response signaling sending time, response signaling receiving time, data sending time and data receiving time.By the above-mentioned mode, the accuracy of delay calculation can be improved without time synchronization.

The invention relates to a Sencil calculation memory access concurrency performance prediction method based on a queuing theory. The method comprises the following steps: calculating memory access missing numbers under different cache capacities by utilizing a memory access missing number prediction model calculated by Stencil; obtaining CPU storage subsystem information, and extracting a processing process of the memory access request in the hardware device supporting memory access concurrency according to the CPU storage subsystem information; according to the CPU storage subsystem information, the memory access missing number, the processing process and the assumed condition, a memory access concurrency performance prediction model is constructed by using the queuing theory and the Littele law; calculating the memory access concurrency bottleneck of each memory access stream according to the memory access concurrency performance prediction model, and calculating the actual memory access bandwidth according to the memory access concurrency of the memory access concurrency bottleneck and the dynamic memory access delay by utilizing the Littele law; according to the actual execution bandwidth and the data access amount, the actual execution time of Sencil calculation is obtained through calculation. By adopting the method, the prediction precision of the Sencil calculation performance can be remarkably improved.

The invention provides a delay processing architecture for an ultrasonic chip, and the architecture comprises an ultrasonic core array which comprises a first ultrasonic core region and a second ultrasonic core region which are split along a horizontal axis, and each ultrasonic core region comprises a plurality of ultrasonic module arrays; each ultrasonic module comprises a plurality of ultrasonic sub-arrays; the double-zone time delay center comprises a first time delay zone and a second time delay zone, the first time delay zone is used for generating a time delay signal of the first ultrasonic core zone, and the second time delay zone is used for generating a time delay signal of the second ultrasonic core zone; wherein each time delay partition comprises a plurality of time delay calculation centers, each time delay calculation center is connected to a plurality of ultrasonic modules, ultrasonic sub-arrays in the ultrasonic modules are cascaded, and the time delay calculation centers are used for generating time delay signals of the ultrasonic sub-arrays in the corresponding ultrasonic modules. Different complexity and real-time requirements of delay can be adapted only by adjusting the command queue, and hardware modules do not need to be modified, so that the development period is greatly shortened.

The invention discloses an instruction scheduling optimization method aiming at RISC-V variable length vector instruction hardware characteristics. The method comprises the following steps: S1, obtaining a target vector instruction to be scheduled; s2, dynamically determining vector configuration information associated with the target vector instruction; s3, based on the vector configuration information, establishing a dynamic delay calculation model, and dynamically calculating an execution delay estimated value of the target vector instruction; and S4, providing the execution delay estimation value to an instruction scheduler, and performing scheduling optimization on the instruction sequence containing the target vector instruction by the instruction scheduler based on the execution delay estimation value. According to the instruction scheduling optimization method, a dynamic delay modeling and delay information dynamic injection mechanism is introduced, so that a compiler scheduler can sense and adapt to dynamic configuration parameters of the RISC-V variable-length vector instruction, and an accurate instruction delay estimated value is generated in real time.

The invention discloses a real-time audio and video end-to-end delay statistical method based on two-way time synchronization, and particularly relates to the technical field of real-time audio and video communication and network performance measurement, which comprises the following steps: S1, time synchronization: a plug flow client and a pull flow client respectively calculate clock skew with an SFU server through two-way message exchange; the method comprises the following steps: S1, a flow pushing end converts an acquisition timestamp and deviation into SFU reference time, and the SFU reference time and stage time consumption metadata are embedded into SEI information to be sent along with a video stream, S3, an SFU server forwards the video stream containing the SEI information, and S4, delay calculation and decomposition: a flow pulling end analyzes the SEI information, calculates total end-to-end delay in combination with the deviation of the flow pulling end, and decomposes the time consumption of each stage. Through high-precision time synchronization and time data losslessly carried by SEI information, non-intrusive, automatic, full-link-covered and decomposable end-to-end delay accurate statistics is realized, and the bottleneck problems that a traditional method is high in invasiveness, low in precision and incapable of positioning are effectively solved.

The invention provides a coding and decoding device and method and a storage medium. When id represents a lower time sub-layer other than the uppermost time sub-layer, the DPB output time [id] of the picture in the lower time sub-layer is calculated. A DPB output difference [id] provided for each sub-layer is subtracted from a common DPB output delay among a plurality of time sub-layers, and when max represents an uppermost sub-layer, the DPB output difference [id] is calculated by subtracting a CPB removal delay [max] and an offset [id] from the CPB removal delay [id]. Next, the offset [id] is stored in the bitstream, the offset [id] is subtracted to calculate a value equal to or less than the DPB output delay [maxid] as a DPB output difference [id], the offset [maxid] is estimated to be zero without writing the offset [maxid] to the bitstream for the uppermost time sub-layer, the offset [id] is subtracted to calculate a value equal to or less than the DPB output delay [maxid] as a DPB output difference [id] for the uppermost time sub-layer without using the DPB output difference [id], and the offset [maxid] is estimated to be zero without writing the offset [maxid] to the bitstream for the uppermost time sub-layer. The DPB output time [maxid] is calculated by adding the time calculated from the DPB output delay [maxid] to the CPB removal time [maxid].

The invention relates to the field of flash memory storage control, in particular to a delay monitoring device based on streaming timestamp sampling. Comprising a timestamp acquisition module which is arranged in the SSD controller and is used for acquiring a timestamp on an IO path; the delay calculation and classification module is used for calculating the collected timestamps to obtain sub-path delays; the streaming statistical unit is used for calculating average delay, maximum delay and minimum delay in real time and supporting generation of delay distribution percentile data; and the threshold value alarm and PMU linkage module is used for configuring a delay threshold value by firmware, triggering the threshold value alarm and PMU linkage module when the I / O delay exceeds the threshold value, giving an alarm and storing execution snapshots of N instructions before and after the abnormal I / O. On the premise that the area and the power consumption of the SSD controller are not obviously increased, delay monitoring with the precision of ten nanoseconds is achieved. The influence of the device on the IOPS performance is lower than 1%, and high-reliability delay diagnosis and QoS guarantee can be provided in a data center scene.

Embodiments of the present application provide an exception recovery method, device and electronic equipment, which are applied to a binary translation system, the binary translation system is used for translating a source program in a client into a target program in a host, and the method comprises the following steps: in the case of an exception, determining a source instruction corresponding to a target instruction triggering the exception and a basic block in the source program, and marking a target position corresponding to the source instruction in the source program; determining an offset value corresponding to a target register according to the target position and a register delay calculation algorithm; the target register comprises registers corresponding to each instruction between a start position of the basic block and the target position and within a correction range of the register delay calculation algorithm; and correcting a value of the target register according to the offset value. Embodiments of the present application can solve problems such as incorrect register values caused by register delay optimization in the binary translation process in the case of exceptions, self-modifying code and other special cases, and improve the exception recovery efficiency.

The present application provides a device delay calibration method, a terminal device and a storage medium. The terminal device communicates with a device group, and the method includes: sending a preset instruction to at least one device in the device group, and receiving a feedback signal corresponding to the preset instruction from the at least one device; calculating a round-trip delay of a signal transmission between the terminal device and the at least one device according to the preset instructions and the feedback signal; based on the round-trip delay, calculating a delay determination base corresponding to the at least one device; performing a delay calibration on the at least one device according to the delay determination base. The above method is used to enable the device group to perform a network synchronization when the device group does not have a timer or the timer is inaccurate.

A flow path delay index evaluation device (1) comprises a delay index calculation unit (210). The delay index calculation unit comprises a delay average calculation unit (211), a variance calculation unit (212), and a transfer delay calculation unit (213) that calculates, as flow path delay indices, an average transfer delay of packets, an average retransmission timer value of packets, and an average transfer delay of packets lost a predetermined number of times in a flow by applying the average and variance of delays to a predetermined relational expression with consideration given to past packet sorting results.

The embodiment of the invention provides an end-to-end time delay minimization method, which is applied to a distributed communication system and comprises the following steps: dynamically acquiring data information of data to be sent and node information of a plurality of nodes included in a plurality of concurrent clusters from an information source, and dynamically acquiring gateway parameters from an exit gateway; based on the data information, the node information and the gateway parameters, minimum end-to-end time delay calculation for the to-be-sent data is carried out, and corresponding optimal dynamic parameters are determined for the to-be-sent data according to a calculation result, the optimal dynamic parameter comprises a block parameter corresponding to the data to be sent, a cluster division parameter corresponding to the plurality of nodes, and a distribution relation parameter between a plurality of data blocks indicated by the block parameter and a plurality of cluster divisions indicated by the cluster division parameter; and controlling the sending of the data to be sent according to the optimal dynamic parameter so as to minimize the end-to-end delay of the data to be sent from the information source to the information sink. According to the scheme, the adaptability and robustness of the distributed communication system can be improved.

The invention relates to the technical field of artificial intelligence, and provides a large model first word delay test method and device, equipment and a medium, and the method comprises the steps: determining a target large model needing to be tested, and determining a target streaming interface, used for providing service, of the target large model; acquiring a request sending script, and acquiring a delay calculation script; executing a request sending script through the test tool, sending a service request to the target streaming interface, recording a sending moment of the service request, and recording a receiving moment of receiving a first response lexical element returned by the target streaming interface; and executing the delay calculation script through the test tool, and calculating the first word delay of the target large model according to the sending time and the receiving time. The method can be applied to the first word delay test of the large model in the business fields of financial science and technology, medical treatment, health and pension and the like, a new special test tool does not need to be developed, the capacity of an existing test tool can be reused, and the first word delay test of the large model can be achieved at low cost.

Provided is an operating method of a storage controller. The method includes fetching, by a processor, a command for a non-volatile memory received from a host, dividing, by the processor, the command into internal processing units, transmitting, by the processor, a first time point at which the command is divided into internal processing units to a latency calculation circuit, executing, by the processor, the command of an internal processing unit to a memory, transmitting, by the processor, a second time point at which the command of an internal processing unit is executed to the latency calculation circuit, calculating, by the latency calculation circuit, latency for the command based on the received first time point and the received second time point, and determining, by the latency calculation circuit, whether the calculated latency exceeds a preset threshold latency.

A method for integrated circuit design with delay verification includes storing configuration files of a slew rate machine learning (ML) model, a signal line delay ML model, and a cell delay ML model. A user design is received, slew rate feature values, signal line delay feature values, and cell delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew rate inference core are performed to calculate predicted slew rate values sent to a ML design tool. Operations of the signal line delay inference core are performed to calculate predicted signal line delay values sent to the ML design tool. Operations of the cell delay inference core are performed to generate predicted cell delay values sent to the ML design tool. The user design is iterated until a user design is obtained that has no timing violations.

A network quality detection method and device, electronic equipment and storage medium, in the kernel state, receive the original reply message sent by the destination, judge whether the third attribute information carried by the original reply message meets the preset filtering condition; when it is determined that the third attribute information meets the preset filtering condition, it is determined that the original reply message is a target reply message; the target reply message is transmitted from the kernel state to the user state, the first attribute information carried by the target reply message and the second attribute information carried by the target measurement message are judged; it is determined that the first attribute information and the second attribute information are the same, the first timestamp of the target measurement message and the second timestamp of the received target reply message are calculated, and the round trip delay calculation result is obtained; the round trip delay calculation result is stored; when it is determined that the number of stored round trip delay calculation results meets the preset number condition, all stored round trip delay calculation results are calculated, and the network quality score is obtained.

The invention relates to the technical field of GPU topological connection detection, in particular to a GPU topological connection detection method and system and a storage medium. The method comprises the following steps: performing grade identification on GPU equipment in a node one by one, and recording operation parameters of each GPU as an initial equipment list; based on the initial device list, link data corresponding to each GPU is obtained in sequence, link matching is carried out on any two GPU devices, delay calculation and bandwidth testing are carried out on a direct connection link and a cross-level link respectively, and a bidirectional link judgment result is formed; comparing the two-way link judgment result with the initial equipment list one by one; according to the method, the GPU equipment information is systematically collected when the computing node is started through topological connection detection, and the interconnection state between the GPUs in the node is comprehensively mastered in combination with two-way link judgment, so that the reliability of computing task allocation and the predictability of resource scheduling are improved.

Disclosed is an improved approach to implement sharing of delay calculations for replicated portions of a design, where input slews may be different between those replicated design portions. This allows the system to experience runtime improvements for timing analysis of electronic designs.

The invention discloses a method and a system for improving large-scale noise data superposition processing efficiency, and aims to solve the problems that system crash is caused by memory overflow in a large-scale noise data superposition scene, and conventional operation response consumes more than 30 minutes. The method comprises the following steps of: constructing an on-demand real-time calculation framework for storing original data and delay calculation, a hierarchical analysis mechanism (only loading a minimum data set required by interface display for the first time, and carrying out deep analysis delay until being triggered when data is actually called), and a data configuration management strategy of globally unique instance cache combined with local refreshing; the effects that the memory peak value is reduced by more than 70%, the crash risk is thoroughly eliminated, the first loading time is compressed to 0.8 min, the interactive operation is changed into real-time response from non-availability, and the whole-process mapping efficiency is improved to be within ten min from the hour level are achieved.

The application discloses a key extraction time synchronization method and system based on an atmospheric turbulence random channel, belongs to the technical field of laser communication and information security, and realizes high-precision time synchronization and dynamic key generation by bidirectional link delay calculation, combination of temperature compensation crystal oscillator compensation and global time reference, adoption of a time division duplex frame structure and an adaptive quantization threshold algorithm, effectively solves the problems of random changes of channel characteristics caused by atmospheric turbulence and clock drift, and can improve synchronization precision and key generation rate, and is suitable for a secure communication system in a complex atmospheric environment.

The application discloses a troposphere delay correction method fusing GNSS and numerical weather prediction products, comprising the following steps: when receiving a delay calculation request of a target point at a target time, determining a grid unit where the target point is located; inputting the coordinates and elevation of the target point into a fusion model constructed in the grid unit to output predicted values of zenith dry delay and zenith wet delay; for the grid unit with a GNSS site, the construction of the fusion model comprises the following steps: obtaining first delay data of the GNSS site at the target time through time extrapolation based on a sliding autoregressive model, synchronously obtaining second delay data of a numerical weather prediction product at the same target time, and aligning the first delay data and the second delay data with the target time; adopting a double dynamic weighting strategy of distance and accuracy to fuse the time-aligned first delay data and the second delay data on zenith dry delay and zenith wet delay respectively, and outputting predicted values of the target point at the target time.

The present application provides a device delay calibration method, a terminal device and a storage medium. The terminal device communicates with a device group, and the method includes: sending a preset instruction to at least one device in the device group, and receiving a feedback signal corresponding to the preset instruction from the at least one device; calculating a round-trip delay of a signal transmission between the terminal device and the at least one device according to the preset instructions and the feedback signal; based on the round-trip delay, calculating a delay determination base corresponding to the at least one device; performing a delay calibration on the at least one device according to the delay determination base. The above method is used to enable the device group to perform a network synchronization when the device group does not have a timer or the timer is inaccurate.

The invention discloses a time delay calculation method and device and a related product, belongs to the technical field of communication, and solves the problem of poor synchronization performance of a network. The method comprises the following steps: providing a first working clock for a media access control (MAC) layer, a physical layer and an FIFO module of the synchronization equipment through a first synchronous clock, and providing a second working clock for the physical layer and an asynchronous FIFO module of the synchronization equipment; the first working clock is used for triggering the MAC layer to send a synchronous message to the asynchronous FIFO module, and the second working clock is used for triggering the asynchronous FIFO module to send the synchronous message to the physical layer; determining a first target period according to a common multiple of the frequency or period of the first work clock and the frequency or period of the second work clock; controlling the MAC layer to send the synchronization message in the first target period; and determining the physical path time delay of the synchronization message transmitted from the MAC layer to the timestamp reference point of the physical layer. The embodiment of the invention is used in a scene of clock synchronization.

The invention discloses a key extraction time synchronization method and system based on an atmospheric turbulence random channel, belongs to the technical field of laser communication and information security, and aims at realizing key extraction time synchronization through bidirectional link delay calculation, combination of temperature compensation crystal oscillator compensation and global time reference and adoption of a time division duplex frame structure and a self-adaptive quantization threshold algorithm. High-precision time synchronization and dynamic key generation are realized, the problems of random change of channel characteristics and clock drift caused by atmospheric turbulence are effectively solved, the synchronization precision and the key generation rate can be improved, and the method is suitable for a secret communication system in a complex atmospheric environment.