130 results about "Delay calculation" patented technology

The invention relates to the technical field of GPU (Graphics Processing Unit), in particular to a GPU program optimization method based on a CUDA (Compute Unified Device Architecture) parallel environment, which comprises the following steps: acquiring a task request sent by a target GPU program, and carrying out priority queue classification on the task request based on a priority coefficient of the task request so as to divide the task request into different priority queues; the activity coefficient of each priority queue is calculated based on the delays of the different priority queues, resource scheduling is carried out on each priority queue through each calculation node in the calculation cluster based on the activity coefficient of each priority queue, and each calculation node is composed of a CPU and a GPU. According to the method, the task requests are subjected to priority queue classification, so that the tasks with high priorities can be preferentially processed, the response speed and efficiency of the whole system are improved, the tasks with different priorities can be effectively managed through task priority queue classification, resource conflicts are avoided, and the processing capacity of key tasks is improved.

The invention relates to an edge service cache optimization method and device, computer equipment and a storage medium. The method comprises the following steps: modeling an edge service cache optimization problem into an MDP model, and collecting state information of a current environment through an intelligent agent at each time step; based on the state information of the current environment, the intelligent agent adopts a depth deterministic strategy gradient algorithm to optimize a cache strategy, and generates a cache strategy through a strategy network; executing the caching strategy, calculating a service access delay after executing the caching strategy through a value network, and calculating a reward function according to the service access delay; and evaluating the execution effect of the cache strategy according to the reward function, and optimizing the strategy network to generate an optimal target network. According to the embodiment of the invention, through intelligent agent learning and cache strategy optimization, the storage resources of the edge server can be utilized more effectively, so that the cache hit rate, the resource utilization efficiency and the service quality are improved.

The invention relates to the technical field of solid state disk performance monitoring, in particular to a real-time performance detection method and system for a solid state disk. The method comprises the following steps: carrying out idle sector identification on the solid state disk, and carrying out tag block normalization operation implantation processing to obtain a plurality of normalization operation implantation tag blocks; carrying out sequential data access request on the plurality of normalized operation implantation mark blocks, carrying out hard disk magnetic head seeking trace analysis, and constructing a global seeking trace; carrying out mark block theoretical access speed calculation on the global seek tracking trajectory, and carrying out access delay calculation, so as to obtain hard disk normalized access delay data; and carrying out verification block progressive implantation analysis on the solid state disk, and carrying out hard disk load evolution so as to generate hard disk load data of each scheme. According to the invention, accurate and real-time solid state disk performance detection is realized.

The invention discloses a storage-efficient large model reasoning method for many-core supercomputing, and relates to the field of machine learning. The overall architecture of the method is based on video memory optimization of Attention and FFN modules in a Transform model, and high storage efficiency in a reasoning stage is realized through matrix block calculation and dynamic video memory management. The method comprises the following steps: firstly, carrying out parameter partitioning and serial calculation: in an Attention module, vertically cutting a Q and K parameter matrix into a plurality of sub-blocks along a column direction, and keeping the input complete; serially calculating the product of each sub-block and the input to obtain a local Q matrix and a local K matrix, and immediately performing QKT block multiplication to obtain a partial attention score; aggregating calculation results of all the sub-blocks to obtain a complete attention score matrix; afterwards, normalizing the attention score by using Softmax, carrying out serial multiplication on the normalized attention score and a V block subjected to delay calculation, and splicing a result to obtain Attention output; optimizing an FFN module, vertically cutting parameters of a full connection layer into sub-blocks, inputting complete data, sequentially carrying out serial calculation on the complete data and the sub-blocks, and splicing nonlinear transformation results of all the sub-blocks in real time.

The invention discloses an EtherCAT master station distributed clock synchronization method based on an ARM and an FPGA, and relates to the technical field of industrial control, the method comprises the following steps: S1, using an FPGA chip integrated with the ARM and programmable logic resources to construct an EtherCAT master station distributed clock module, the ARM and the programmable logic resources interacting through an internal AXI interconnection bus; s2, the programmable logic resource obtains an enable signal sent by the ARM end, and if the enable signal is 1, the master station performs topology scanning, delay calculation, clock compensation and dynamic drift compensation operations on the slave station to obtain a delay compensation value and a local clock compensation value of the slave station; s3, after compensation is completed, the state machine of the master station automatically jumps to a synchronous signal generation module, SYNC parameters are obtained from the ARM end, and SYNC signal starting time of the slave station is calculated according to the SYNC parameters; s4, respectively converting the delay compensation value, the local clock compensation value and the starting time of the slave station into message information, sending the message information to the slave station, adding 1 to the address of the slave station, and returning to the step S1 until the distributed clock configuration of all the slave stations is completed; the EtherCAT master station distributed clock synchronization method solves the problem that a synchronization (SYNC) signal generated after a distributed clock algorithm is started is unstable, and shows potential and value in the field of higher-frequency slave station synchronization.

The invention discloses a solid state disk customization test method and system, electronic equipment and a medium, and relates to the technical field of data processing. The method comprises the following steps: acquiring state data of a sample hard disk, wherein the state data comprises the number of bad blocks, erasing times and read-write delay; a loop test instruction is generated according to the erasing times and the read-write delay, and the execution duration of the loop test instruction is determined based on the number of bad blocks; writing the loop test instruction into non-bad block areas of a plurality of solid state disks in the to-be-tested solid state disk group, and respectively performing data read-write operation according to the execution duration; obtaining response delays of the solid state disks after the data read-write operation, and calculating delay growth rates corresponding to the solid state disks based on the response delays and the read-write delays; and determining any solid state disk of which the delay growth rate is greater than a growth rate threshold as an abnormal hard disk. By implementing the technical scheme provided by the invention, the effect of improving the testing accuracy of the solid state disk is achieved.

The invention belongs to the technical field of video monitoring and image recognition, and particularly relates to a video monitoring transmission delay detection method and system based on image recognition, and the method comprises the steps: extracting image stable texture features through SIFT to generate a 128-dimensional descriptor, capturing an inter-frame motion trend through a Lucas-Kanade algorithm to generate a time feature, and carrying out the detection of the transmission delay of the video monitoring through the Lucas-Kanade algorithm. Finally, dynamic weighted fusion is carried out through an attention mechanism, and a space-time joint feature vector is generated; then, a dynamic template containing spatial-temporal characteristics and a local clock is generated at a sending end, cross-end matching is carried out at a receiving end by using an FLANN algorithm, the influence of network jitter and clock skew is eliminated through a double-calibration mechanism of basic time delay calculation, clock skew calibration and jitter compensation, and finally time delay after calibration is output; based on this, the method has the advantages of avoiding the interference of network jitter on the delay detection precision and reducing the delay standard exceeding false alarm condition caused by instantaneous deviation through the design of double-calibration delay calculation and cross-end feature accurate matching.

The invention discloses a virtual power plant rapid frequency modulation control system and control method, and the method comprises the steps: adaptively adjusting a sampling period through a dynamic sampling algorithm based on a sliding window variance; low-delay calculation of high-frequency data is realized by adopting a multi-thread queue communication technology; a multi-core ARM processor running a real-time operating system is used for executing a multi-thread control model, and data acquisition, algorithm control, fault diagnosis and communication tasks are processed in parallel; according to the control algorithm, frequency prediction feedforward signals based on an AI model and SOC state feedback are fused, and dynamic optimization of PID parameters is achieved. According to the method, millisecond-level frequency modulation response can be realized, the instruction response delay is less than 80ms, the frequency adjustment error is less than + / -0.01 Hz, the frequency modulation performance of a virtual power plant and the stability of a power grid are remarkably improved, and meanwhile, the service life of energy storage equipment is prolonged through SOC collaborative optimization. The invention aims to solve the problems of slow response and low precision of the existing frequency modulation technology.

The invention belongs to the technical field of laser precision machining and control, and particularly relates to a femtosecond laser single-point trigger control system and method based on subnanosecond synchronization, and the method comprises the following steps: S1, building a system synchronization clock locked with a femtosecond laser pulse signal phase; the specific mode of establishing the system synchronous clock is that phase locking is carried out on pulse synchronous signals or frequency division signals output by an internal high-frequency clock source and a femtosecond laser source through a digital phase-locked loop technology, and the low-jitter system synchronous clock which is strictly synchronous with a laser pulse sequence is generated. According to the invention, a system clock locked with a laser pulse phase can be generated through a digital phase-locked loop, and the influence of inherent frequency drift of a laser and circuit delay temperature drift is effectively overcome by combining real-time delay calculation based on a prediction algorithm and a high-resolution DDS delay line technology; the synchronization precision between the triggering moment of the single pulse and the external instruction is stabilized at the subnanosecond level, and the requirement of leading-edge application for the extreme time sequence precision is met.

The invention discloses a GPU cluster task scheduling method and device, equipment and a medium. The method comprises the following steps: constructing a task dependency graph in response to a to-be-scheduled task; obtaining a matched scheduling strategy according to the task characteristics of the to-be-scheduled task, marking a node type for each computing node in the task dependency graph, and determining an available GPU resource pool according to the scheduling strategy and the node type; generating all candidate GPU allocation schemes, and calculating an end-to-end execution delay of each candidate GPU allocation scheme by using a preset delay calculation model; and according to each end-to-end execution time delay and the scheduling strategy, selecting a target GPU allocation scheme from all the candidate GPU allocation schemes, so that a cluster resource manager schedules a target GPU cluster to execute the to-be-scheduled task according to the target GPU allocation scheme. According to the method, a closed loop from task analysis, resource screening to scheme optimization is formed, and the accuracy, efficiency and adaptability of GPU cluster task scheduling are improved.

The invention discloses a calibration circuit and method for aperture delay of a multi-channel analog-to-digital converter, and belongs to the technical field of integrated circuits, and the calibration circuit comprises a configurable delay circuit, a sampling hold circuit, an analog-to-digital conversion circuit and an aperture delay calculation circuit. When aperture delay calibration is carried out on a chip, an input signal and a sampling clock signal are externally applied to each channel of the multi-channel analog-to-digital converter, are converted into a digital coding result through the analog-to-digital conversion circuit after passing through the sampling hold circuit, and are output to the aperture delay calculation circuit to calculate a delay configuration word; and the input configurable delay circuit compensates aperture delay. According to the method, the problem of inter-channel aperture delay deviation measurement is converted into inter-channel analog-to-digital conversion output result deviation, simultaneous calibration of multiple chips is carried out on the premise that no extra circuit is needed, automatic calibration of aperture delay in the chips is achieved by adding an aperture delay calculation circuit in the chips, and the accuracy of calibration of the aperture delay in the chips is improved. The test equipment requirement, the test time and the test cost are reduced, and the test efficiency is improved.

The invention discloses a time delay calculation algorithm based on implicit circuit modeling and a model reduction algorithm, and the algorithm comprises the steps: S1, traversing the serial number of a circuit to a node, and representing a topological structure through a vector; s2, creating an equivalent implicit differential model of the circuit; s3, solving a linear system; s4, model order reduction is carried out through an improved Arnoldi algorithm; and S5, calculating the final time delay of the circuit through an iterative algorithm. The invention discloses a time delay calculation algorithm based on implicit circuit modeling and a model order reduction algorithm, and the time delay calculation efficiency and precision are remarkably improved through the methods of circuit model optimization, order reduction processing, characteristic value calculation, incremental updating of an iterative algorithm result and the like.

The invention discloses a high-precision time keeping method and system based on a Beidou module and an RTC chip, and relates to the technical field of high-precision time synchronization, and the method comprises the steps: setting and initializing a time keeping system; receiving a Beidou time service signal, and recording a time message; writing and reading RTC time based on the time message, and calculating read-write delay; calculating an RTC punctuality error based on the read-write delay; based on the RTC punctuality error, first operation is carried out when Beidou time service is normal, and second operation is carried out when Beidou time service is abnormal; according to the invention, under the condition that signal loss of the Beidou module occurs on site, the time precision is obtained from the RTC by compensating the punctuality error of the RTC chip, so that the demand of on-site high-precision time synchronization is met; and compared with other high-precision time-keeping complex schemes, the cost is more advantageous.

Techniques are disclosed for computing a cost of an advertised route to a next-hop network device along a path to a destination based at least in part on a preference for the path. In one example, a computing system computes a cost of a route to a next-hop network device along a path to a destination. The computed cost is based at least in part on (1) a metric for the route and (2) a preconfigured preference for the path. In some examples, the preference for the path is based at least in part on (a) a type of the path as compared to other types of other paths to the destination or (b) a latency of the path as compared to other latencies of the other paths. The computing system sends a route advertisement for the route that includes data indicative of the cost of the route.

The invention discloses a clock signal delay alignment method and system in a circuit back-mark simulation environment. The clock signal delay alignment method comprises the following steps: determining a clock signal delay requirement of an input port of a module to be tested in the circuit back-mark simulation environment; determining a clock signal delay requirement of an output port of the module to be tested in the circuit back-standard simulation environment; combining the delay requirements of the two clock signals to obtain a required clock signal delay range; and according to the required clock signal delay range, carrying out delay alignment on the clock signals in the circuit back-mark simulation environment. The invention aims to improve the circuit back-mark simulation efficiency and accelerate the back-mark simulation progress, the delay alignment time of the clock signal is innovatively obtained through delay calculation, multiple iterative simulations in a back-mark simulation environment in a traditional method are avoided, and the simulation progress is effectively accelerated.

The invention discloses a precision test platform for delay calculation, and the platform comprises a test data collection module which is used for decomposing each time sequence path of an integrated circuit into a plurality of independent stages; the test database is used for storing information required by calculation of each stage in a standardized format; the test data modification and file generation module is used for modifying the stored stage data according to test requirements and reconstructing the modified data into a design file meeting the requirements of a specific EDA tool; and the test operation and evaluation module is used for executing the target test software and the benchmarking third-party software, analyzing the result and performing comparative analysis. According to the precision test platform for delay calculation disclosed by the invention, the complexity of calculation precision evaluation and the difficulty of independent module verification in ASIC (Application Specific Integrated Circuit) large-scale design are solved, and by providing a standardized and modularized test environment, the development efficiency and accuracy of VLSI (Very Large Scale Integration) design EDA (Electronic Design Automation) tools are remarkably improved; and meanwhile, an automatic process for comparing with a third-party software tool is provided.

A direct memory access (DMA) device includes a controller, a read request issuing circuit, a read buffer temporarily storing read data and an arrival time of the read data, and a read buffer managing circuit that calculates an average bus latency and an average buffer residence time. The read request issuing circuit adjusts the issuing capability based on the average bus latency and the average buffer residence time. The DMA device operates by issuing a read request based on an issuing capability, storing an issuing time of the read request, receiving read data corresponding to the read request, temporarily storing the read data and an arrival time of the read data in a read buffer, calculating an average bus latency based on the issuing time of the read request, calculating an average buffer residence time, adjusting the issuing capability, and issuing the read request based on the adjusted issuing capability.

The invention provides a maximum delay calculation method and device and a computer readable storage medium, relates to the technical field of integrated circuits, and is used for solving the problem of how to improve the efficiency and precision of analyzing the maximum delay time of an integrated circuit. The computing method comprises: providing a circuit comprising a victim network and a plurality of aggressor networks; selecting one of a plurality of output nodes of the victim network as a representative node, and obtaining the maximum delay time of the representative node; according to the maximum delay time, obtaining initial maximum delay time of each output node except the representative node; the representative node is updated at least once, in each update, an output node is selected from the output nodes which are not used as the representative node from beginning to serve as the representative node, and the maximum delay time of the updated representative node is obtained; and according to the updated maximum delay time of the representative node, obtaining the maximum delay time of each output node which is not used as the representative node. The calculation method can be used for timing sequence verification of an integrated circuit.

The application discloses a kind of delay calculation method, equipment and computer readable storage medium, the delay calculation method includes: obtaining data receiving end sends pull stream request signaling Request signaling sending time and data sending end receives pull stream request signaling Request signaling receiving time;Obtain the response signaling sending time of data sending end sending pull stream response signaling and the response signaling receiving time of data receiving end receiving pull stream response signaling;Data sending time and data receiving time are obtained, data sending time is the time that data sending end issues transmission data, data receiving time is the time that data receiving end receives transmission data;Network delay is calculated using Request signaling sending time, Request signaling receiving time, response signaling sending time, response signaling receiving time, data sending time and data receiving time.By the above-mentioned mode, the accuracy of delay calculation can be improved without time synchronization.

The present application relates to a delay testing method and apparatus, a computer device, a storage medium and a computer program product. The method comprises: performing screenshot processing on a preset clock video according to a first preset time period, so as to obtain a first screenshot data set; receiving a second screenshot data set sent by a slave control device, wherein the second screenshot data set comprises screenshot data of the preset clock video that is captured by the slave control device according to a second preset time period; and performing delay calculation on the basis of the first screenshot data set and the second screenshot data set, so as to obtain a target delay result. The present method can improve the accuracy of delay testing.

The invention relates to a Sencil calculation memory access concurrency performance prediction method based on a queuing theory. The method comprises the following steps: calculating memory access missing numbers under different cache capacities by utilizing a memory access missing number prediction model calculated by Stencil; obtaining CPU storage subsystem information, and extracting a processing process of the memory access request in the hardware device supporting memory access concurrency according to the CPU storage subsystem information; according to the CPU storage subsystem information, the memory access missing number, the processing process and the assumed condition, a memory access concurrency performance prediction model is constructed by using the queuing theory and the Littele law; calculating the memory access concurrency bottleneck of each memory access stream according to the memory access concurrency performance prediction model, and calculating the actual memory access bandwidth according to the memory access concurrency of the memory access concurrency bottleneck and the dynamic memory access delay by utilizing the Littele law; according to the actual execution bandwidth and the data access amount, the actual execution time of Sencil calculation is obtained through calculation. By adopting the method, the prediction precision of the Sencil calculation performance can be remarkably improved.

The invention provides a delay processing architecture for an ultrasonic chip, and the architecture comprises an ultrasonic core array which comprises a first ultrasonic core region and a second ultrasonic core region which are split along a horizontal axis, and each ultrasonic core region comprises a plurality of ultrasonic module arrays; each ultrasonic module comprises a plurality of ultrasonic sub-arrays; the double-zone time delay center comprises a first time delay zone and a second time delay zone, the first time delay zone is used for generating a time delay signal of the first ultrasonic core zone, and the second time delay zone is used for generating a time delay signal of the second ultrasonic core zone; wherein each time delay partition comprises a plurality of time delay calculation centers, each time delay calculation center is connected to a plurality of ultrasonic modules, ultrasonic sub-arrays in the ultrasonic modules are cascaded, and the time delay calculation centers are used for generating time delay signals of the ultrasonic sub-arrays in the corresponding ultrasonic modules. Different complexity and real-time requirements of delay can be adapted only by adjusting the command queue, and hardware modules do not need to be modified, so that the development period is greatly shortened.

The link delay between the detector and the ground is an important factor affecting the accuracy of timing, and is mainly obtained through test measurements during the AIT or large system docking test phase. Due to the different software and hardware design architectures of the on-board electronic equipment, some detectors have fuzzy matching problems in the output signal of the measurement of the link delay between the detector and the ground using the existing pulse time recording method for measuring the link delay between the detector and the ground. Based on the principle of device-to-ground timing, the on-board time code in the detector telemetry frame and the GPS time code attached by the ground time source at the moment of receiving the telemetry frame are obtained using the ground baseband equipment. A method and system for calculating the link delay between the detector and the ground based on the detector time code are proposed, which can be used to calculate the order of magnitude of the link delay between the detector and the ground and determine the exact value of the link delay between the detector and the ground in combination with the actual measurement results.

The invention relates to the technical field of power systems, and provides a passive clock synchronization method and system for distributed relay protection equipment, and the method comprises the steps: calculating the communication channel delay between a host and a slave, and executing the next step when the channel delay calculation is correct; checking the time of the host and the slave to synchronize the time of each slave; calculating the sampling beat time difference of the host and the slave; the sampling rhythm of the slave is adjusted, so that the sampling rhythms of the slave and the host are consistent in real time, and passive clock synchronization of the host and the slave is completed. According to the scheme of the invention, the passive clock synchronization method has the following advantages: the distance between the host and the slave is not limited, as long as the data transmission delay between the host and the slave is fixed or measurable; meanwhile, clock synchronization and beat synchronization of equipment in a local area are realized; the frequency is stable in the equipment beat adjusting process, and the synchronization precision between equipment is high; accidental data interruption does not affect sampling beat synchronization and time synchronization between devices.

The invention discloses an instruction scheduling optimization method aiming at RISC-V variable length vector instruction hardware characteristics. The method comprises the following steps: S1, obtaining a target vector instruction to be scheduled; s2, dynamically determining vector configuration information associated with the target vector instruction; s3, based on the vector configuration information, establishing a dynamic delay calculation model, and dynamically calculating an execution delay estimated value of the target vector instruction; and S4, providing the execution delay estimation value to an instruction scheduler, and performing scheduling optimization on the instruction sequence containing the target vector instruction by the instruction scheduler based on the execution delay estimation value. According to the instruction scheduling optimization method, a dynamic delay modeling and delay information dynamic injection mechanism is introduced, so that a compiler scheduler can sense and adapt to dynamic configuration parameters of the RISC-V variable-length vector instruction, and an accurate instruction delay estimated value is generated in real time.

The invention discloses a real-time audio and video end-to-end delay statistical method based on two-way time synchronization, and particularly relates to the technical field of real-time audio and video communication and network performance measurement, which comprises the following steps: S1, time synchronization: a plug flow client and a pull flow client respectively calculate clock skew with an SFU server through two-way message exchange; the method comprises the following steps: S1, a flow pushing end converts an acquisition timestamp and deviation into SFU reference time, and the SFU reference time and stage time consumption metadata are embedded into SEI information to be sent along with a video stream, S3, an SFU server forwards the video stream containing the SEI information, and S4, delay calculation and decomposition: a flow pulling end analyzes the SEI information, calculates total end-to-end delay in combination with the deviation of the flow pulling end, and decomposes the time consumption of each stage. Through high-precision time synchronization and time data losslessly carried by SEI information, non-intrusive, automatic, full-link-covered and decomposable end-to-end delay accurate statistics is realized, and the bottleneck problems that a traditional method is high in invasiveness, low in precision and incapable of positioning are effectively solved.

The invention provides a coding and decoding device and method and a storage medium. When id represents a lower time sub-layer other than the uppermost time sub-layer, the DPB output time [id] of the picture in the lower time sub-layer is calculated. A DPB output difference [id] provided for each sub-layer is subtracted from a common DPB output delay among a plurality of time sub-layers, and when max represents an uppermost sub-layer, the DPB output difference [id] is calculated by subtracting a CPB removal delay [max] and an offset [id] from the CPB removal delay [id]. Next, the offset [id] is stored in the bitstream, the offset [id] is subtracted to calculate a value equal to or less than the DPB output delay [maxid] as a DPB output difference [id], the offset [maxid] is estimated to be zero without writing the offset [maxid] to the bitstream for the uppermost time sub-layer, the offset [id] is subtracted to calculate a value equal to or less than the DPB output delay [maxid] as a DPB output difference [id] for the uppermost time sub-layer without using the DPB output difference [id], and the offset [maxid] is estimated to be zero without writing the offset [maxid] to the bitstream for the uppermost time sub-layer. The DPB output time [maxid] is calculated by adding the time calculated from the DPB output delay [maxid] to the CPB removal time [maxid].

The invention relates to the field of flash memory storage control, in particular to a delay monitoring device based on streaming timestamp sampling. Comprising a timestamp acquisition module which is arranged in the SSD controller and is used for acquiring a timestamp on an IO path; the delay calculation and classification module is used for calculating the collected timestamps to obtain sub-path delays; the streaming statistical unit is used for calculating average delay, maximum delay and minimum delay in real time and supporting generation of delay distribution percentile data; and the threshold value alarm and PMU linkage module is used for configuring a delay threshold value by firmware, triggering the threshold value alarm and PMU linkage module when the I / O delay exceeds the threshold value, giving an alarm and storing execution snapshots of N instructions before and after the abnormal I / O. On the premise that the area and the power consumption of the SSD controller are not obviously increased, delay monitoring with the precision of ten nanoseconds is achieved. The influence of the device on the IOPS performance is lower than 1%, and high-reliability delay diagnosis and QoS guarantee can be provided in a data center scene.

Embodiments of the present application provide an exception recovery method, device and electronic equipment, which are applied to a binary translation system, the binary translation system is used for translating a source program in a client into a target program in a host, and the method comprises the following steps: in the case of an exception, determining a source instruction corresponding to a target instruction triggering the exception and a basic block in the source program, and marking a target position corresponding to the source instruction in the source program; determining an offset value corresponding to a target register according to the target position and a register delay calculation algorithm; the target register comprises registers corresponding to each instruction between a start position of the basic block and the target position and within a correction range of the register delay calculation algorithm; and correcting a value of the target register according to the offset value. Embodiments of the present application can solve problems such as incorrect register values caused by register delay optimization in the binary translation process in the case of exceptions, self-modifying code and other special cases, and improve the exception recovery efficiency.

The present application provides a device delay calibration method, a terminal device and a storage medium. The terminal device communicates with a device group, and the method includes: sending a preset instruction to at least one device in the device group, and receiving a feedback signal corresponding to the preset instruction from the at least one device; calculating a round-trip delay of a signal transmission between the terminal device and the at least one device according to the preset instructions and the feedback signal; based on the round-trip delay, calculating a delay determination base corresponding to the at least one device; performing a delay calibration on the at least one device according to the delay determination base. The above method is used to enable the device group to perform a network synchronization when the device group does not have a timer or the timer is inaccurate.