9 results about "Delay calculation" patented technology

Techniques are disclosed for computing a cost of an advertised route to a next-hop network device along a path to a destination based at least in part on a preference for the path. In one example, a computing system computes a cost of a route to a next-hop network device along a path to a destination. The computed cost is based at least in part on (1) a metric for the route and (2) a preconfigured preference for the path. In some examples, the preference for the path is based at least in part on (a) a type of the path as compared to other types of other paths to the destination or (b) a latency of the path as compared to other latencies of the other paths. The computing system sends a route advertisement for the route that includes data indicative of the cost of the route.

A direct memory access (DMA) device includes a controller, a read request issuing circuit, a read buffer temporarily storing read data and an arrival time of the read data, and a read buffer managing circuit that calculates an average bus latency and an average buffer residence time. The read request issuing circuit adjusts the issuing capability based on the average bus latency and the average buffer residence time. The DMA device operates by issuing a read request based on an issuing capability, storing an issuing time of the read request, receiving read data corresponding to the read request, temporarily storing the read data and an arrival time of the read data in a read buffer, calculating an average bus latency based on the issuing time of the read request, calculating an average buffer residence time, adjusting the issuing capability, and issuing the read request based on the adjusted issuing capability.

The present application provides a device delay calibration method, a terminal device and a storage medium. The terminal device communicates with a device group, and the method includes: sending a preset instruction to at least one device in the device group, and receiving a feedback signal corresponding to the preset instruction from the at least one device; calculating a round-trip delay of a signal transmission between the terminal device and the at least one device according to the preset instructions and the feedback signal; based on the round-trip delay, calculating a delay determination base corresponding to the at least one device; performing a delay calibration on the at least one device according to the delay determination base. The above method is used to enable the device group to perform a network synchronization when the device group does not have a timer or the timer is inaccurate.

The present invention relates to the technical field of integrated circuits. Disclosed are an aperture delay calibration circuit and method for a multi-channel analog-to-digital converter. The calibration circuit comprises: a configurable delay circuit, a sample-and-hold circuit, an analog-to-digital conversion circuit, and an aperture delay calculation circuit. When aperture delay calibration is performed on a chip, an input signal and a sampling clock signal are externally applied to each channel of the multi-channel analog-to-digital converter, and are converted into a digital code by means of the analog-to-digital conversion circuit after passing through the sample-and-hold circuit, the digital code is outputted to the aperture delay calculation circuit to calculate a delay configuration word, and the delay configuration word is inputted to the configurable delay circuit to compensate for the aperture delay. The method of the present invention converts an inter-channel aperture delay deviation measurement problem into an inter-channel analog-to-digital conversion output result deviation, and performs multi-chip simultaneous calibration without the need for additional circuits. By adding the aperture delay calculation circuit inside the chip, the aperture delay is automatically calibrated inside the chip, thereby lowering the requirements on a test device, reducing the test time and costs, and improving the test efficiency.

A method and apparatus for evaluating operator performance are disclosed, relating to the field of computer technology. A computing device acquires an operator including a first instruction and a first matrix, and determines the first execution time of a first computing unit for the first instruction according to a first computing strategy. The first computing strategy indicates that the first execution time is the sum of the ratio of a first computational quantity to a set computational quantity, the processor's clock cycle, and a first delay time. The first computational quantity is the product of the size of the first matrix and the size of the weight matrix, and the first delay time indicates the time interval between processing two first sub-matrices during the execution of the first instruction by the first computing unit. The computing device also considers the delay in the first computing unit's processing of the first matrix during the determination of the first execution time. Based on the first computing strategy, the computing device can accurately determine the time it takes for the processor to process the first matrix using the operator, thereby improving the accuracy of operator performance prediction.

This invention discloses a spatiotemporal decoupling prediction and feedforward compensation method for visual servoing of a robotic arm, comprising the following steps: S1, target TF transformation acquisition and dynamic spatiotemporal sliding window construction; S2, spatiotemporal decoupling and spatial dimensionality reduction mapping of multi-degree-of-freedom poses; S3, low-dimensional Fourier modeling and fast optimization based on adaptive fundamental frequency estimation; S4, heterogeneous system composite delay calculation, absolute timestamp feedforward compensation, and pose reconstruction; S5, trajectory cascade shaping and closed-loop distribution based on exponentially weighted moving average (EMA). The feedforward compensation method proposed in this invention, which does not rely on expensive computing power for spatiotemporal decoupling, dimensionality reduction fitting, and filtering reconstruction, can achieve millisecond-level computation on ordinary industrial control computers, completing long-delay feedforward compensation up to 250ms, ensuring the high-frequency smoothness and physical safety of the robotic arm.

This invention discloses a method and system for calculating industrial time-series data with instantaneous high-frequency characteristics, belonging to the field of real-time computing for power system dispatch automation. The method employs a cache-based out-of-order data correction technique, a streaming-based dynamic delay calculation method, and a reentrant calculation window verification method to adaptively optimize instantaneous high-frequency time-series data. This achieves high-precision, high-frequency, and high-performance industrial time-series data calculation, effectively improving the power grid's operation monitoring level and ensuring its operational safety. This invention is particularly applicable to high-frequency data calculation and analysis of key equipment such as IGBTs and fault recording devices in flexible DC substations, improving the accuracy and real-time performance of power system fault analysis and diagnosis.

The present application relates to the field of communication technology, and discloses a kind of self-evaluation method of dual-mode communication link quality.The present application records the sending time of each frame and radio frequency / wired link receiving time, constructs two link receiving delay sequence;Through time check, extract common frame, based on its delay calculation single frame delay threshold and eliminate frame over threshold, obtain effective frame and delay, realize different link delay comparable and suppress outlier.Again, according to frame order, first-order difference is carried out and autoregressive prediction is established, the error square mean of actual and predicted difference is used to construct fluctuation energy index, the index is converted into two link quality score and summed as overall quality score, simultaneously, according to the amplitude of prediction error, the number of abnormal frame is determined, the output index containing score and abnormal frame is formed, and compared with preset interval threshold, the link state is automatically divided into high, medium and low quality, the burst jitter is highlighted and automatic determination is realized.

This invention discloses a method, system, device, and medium for improving the computation efficiency of delayed computing blocks. It belongs to the fields of artificial intelligence, in-memory computing, and delayed computing technologies, and includes: using an 8-bit unsigned number as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM The method converts an 8-bit unsigned number into an 8-bit signed number to obtain the binary code of the true value. Based on this binary code, a memory-based delayed computation circuit is used to perform delayed computation, completing the inner product calculation within one computation clock cycle. This invention's delayed computation block efficiency improvement method utilizes the concept of differential-mode and common-mode computation, converting an 8-bit unsigned number into an 8-bit signed number and converting weights into differential-mode and common-mode weights for delayed computation; within the delayed computation block, it restores the accumulated delay value corresponding to the differential-mode weight to the accumulated delay value corresponding to the common-mode weight.