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523 results about "Delay calculation" patented technology

Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and wire.

External pressure self-intensification cylinder and design calculation and manufacturing method thereof

The invention discloses an external pressure self-intensification cylinder and a design calculation and a manufacturing method thereof, which is used for improving the safety and the bearing capability of a pressure vessel and solving the phenomenon of lacking external pressure self-intensification vessel design calculation and manufacturing methods and the technical problems of unsafety and the like caused by complex or inaccurate design calculation of the existing internal pressure self-intensification technology. The invention has the following technical scheme key points: adopting a special bearing capability, plastic zone depth and cylinder wall thickness calculating formula to ensure that the equivalent stress of the total stress (the sum of stress caused by operation pressure and self-intensification residual stress) in the wall of the cylinder is not more than the yield strength sigma y of cylinder material; or ensuring that the equivalent stress of the residual stress in the whole cylinder wall of the self-intensification cylinder and the equivalent stress of the total stress are both not more than sigma y. The invention also provides a maximum diameter ratio which does not yield after the self-intensification pressure is removed no mater how deep the plastic zone is when the self-intensification technology is applied. The technical scheme of the invention is also suitable for an internal pressure self-intensification cylinder.
Owner:HUNAN NORMAL UNIVERSITY

An urban road network generalized road right calculating method considering comprehensive traffic management measures

The invention discloses an urban road network generalized road right calculating method considering comprehensive traffic management measures. The method comprises road section time impedance calculation with traffic management measures being taken into consideration and intersection delay calculation under a traffic control strategy, and specifically comprises road section basic traffic capacity analysis, influence correction of the traffic management measures on road section traffic capacity, road section time impedance analysis and correction of the traffic management measures on road section time impedance; and intersection entrance road lane group division based on turning relation, lane group motor basic traffic capacity analysis, influence correction of the traffic management measures on lane group traffic capacity and intersection delay analysis for traffic assignment. The method can reflect independent road rights of different types of vehicles in an urban road network, can enable simulation and prediction results to be more accurate, quantifies difference of different traffic management strategy combination schemes and provides powerful support for planning of current urban traffic management and control and formulation of traffic policies.
Owner:SOUTHEAST UNIV

Hardware framework for carrying out reasoning acceleration by aiming at convolution neural network, and working method thereof

ActiveCN108108809AIncrease bus transferImplement recursive utilizationNeural architecturesPhysical realisationComputer hardwareNeuron network
The invention relates to a hardware framework for carrying out reasoning acceleration by aiming at a convolution neural network, and a working method thereof. The hardware framework comprises a preprocessing unit, a hardware acceleration unit and a storage unit, wherein the preprocessing unit is used for preprocessing an original image frame which is originally input; the hardware acceleration unit is used for reading the preprocessed original image frame to be convoluted, a convolution kernel coefficient and an offset parameter for convolution, executing fully connected layer calculation after convolution is finished, and outputting a calculation characteristic judgment result after the fully connected layer calculation is finished; the storage unit is used for storing the original imageframe which is originally input, the convolution kernel coefficient, the offset parameter, output data obtained by each convolution and the output data of the fully connected layer. According to the hardware framework, the problems that a traditional processor is low in speed and high in time delay, real-time reasoning can not be realized and the like are solved, and a new solution is provided fordesigning the processor which carries out the reasoning calculation by aiming at the CNN (Convolution Neural Network).
Owner:SHANDONG LINGNENG ELECTRONIC TECH CO LTD
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