10results about "Delay line applications" patented technology

Systems, apparatuses, and methods for managing power and performance in a computing system. A system management unit detects a condition indicating a change in a power-performance state of a given computing unit is indicated. In response to detecting the indication, the system management unit is configured to initiate a change to a frequency of a clock signal generated by an adaptive oscillator by changing a voltage supplied to the adaptive oscillator. The adaptive oscillator is configured to rapidly change a frequency of the clock signal generated in response to detecting a change in a droopy supply voltage of the adaptive oscillator. The new frequency generated by the adaptive oscillator is based in part on a difference between the droopy supply voltage and a regulated supply voltage of the adaptive oscillator.

The apparatus includes a clock skew calibration circuit configured to be coupled to the multi-phase clock generator via a plurality of delay lines, wherein the first clock skew calibration unit comprises: a frequency multiplier configured to receive a plurality of multi-phase clock signals and to generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signals and to generate a reduced frequency signal based on the clock signals; and a delay line control circuit configured to compare a duty cycle of the reduced frequency signal with a predetermined duty cycle and to generate a first control signal to adjust the skew of the first multi-phase clock signals by adjusting a first delay applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved.

A multi-stream cross correlator for spiking neural networks, where each stream contains significant stochastic content. At least one event occurs, with a fixed temporal relationship across at least two streams. Each stream is treated as a Frame Of Reference (FOR), and subject to an adjustable delay based on comparison to the Other streams. For each spike of the FOR, a timing analysis, relative to the last and current FOR spikes, is completed by comparing Post and Pre accumulators. Also, a new timing analysis is begun, with the current FOR spike, by restarting the production of Post and Pre weighting functions, the values of which are accumulated, upon the occurrence of each Other spike, until a next FOR spike. A one-spike delay unit can be used, if time-neutral conflict resolution is used. The average spike rate of the FOR can be determined and used for the Post and Pre weighting functions.

An FPGA is disclosed, which includes a first delay line section to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input, a code conversion section that converts the order of the elements of a thermometer code output by the first delay line section and outputs it, and a calculation section that uses the converted code output by the code conversion section to determine the occurrence time difference, wherein the converted code is obtained by arranging the order of the elements of the thermometer code according to a predetermined standard, and the predetermined standard is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the first delay line section.

Aspects of this disclosure relate to an asynchronous sample rate converter (ASRC) comprising a signal input configured to receive an input signal having one or more input signal values at a first sample rate, a first clock input configured to receive an input clock signal corresponding to the first sample rate, a signal output configured to provide an output signal having one or more output signal values at a second sample rate, a second clock input configured to receive an output clock signal corresponding to the second sample rate, a zero-padding circuit configured to add a plurality of zero values following at least one of the one or more input signal values, and a filter configured to generate the output signal, the output signal having one or more output signal values based on the input signal.

A time capture circuit (20, 20') to measure time between events, in particular edges, of a logic input signal (EXT_SGL, D0), comprising a delay line (D) receiving at its input said input signal (EXT_SGL, D0) and generating a plurality of consecutive increasingly delayed replicas (D1out,...,Dmout,..., DMout) of said logic input signal (EXT_SGL, D0), each replica (Dmout) delayed by a fixed delay (TDm) with respect to the preceding replica (Dm-1out), a free running counter (CNT) which is clocked by a counter clock signal (CNT_CLK) corresponding to an external clock signal (CLK_SYS) multiplied by a clock scale factor (CLK_CNT_PRS) and supplies a counter value (x) to a counter value capture block (CAPT_CNT), said counter value capture block (CAPT_CNT) receiving also said input signal (EXT_SGL, D0) and being configured to capture said counter value (x) upon the occurrence of an event (E1, E2; C1, C2) in said input signal outputting a captured counter value (CAPT_CNTout) and issuing a trigger signal (CAPT_CNTtrg), a decoder module (CAPT_DECODE) receiving as inputs said input signal (EXT_SGL, D0), said plurality of delayed replicas (D1out,..., Dmout,..., DMout) and said captured counter value (CAPT_CNTout) and said trigger signal (CAPT_CNTtrg), said decoder module (CAPT_DECODE) being configured to determine a decoded value (CAPT_DCD)) on the basis of at least the values of said input signal (EXT_SGL, D0) and of said plurality of consecutive increasingly replicas (D1out,...,Dmout,..., DMout) when the trigger signal (CAPT_CNTtrg) is issued and to compute a capture value (HRS_CAPT_VAL) as the difference of said captured counter value (CAPT_CNTout) logical left shifted by a first scale factor (CLK_CAPT_PRS) and said decoded value (CAPT_DCD) logical right shifted by a second scale factor (N- CLK_CAPT_PRS).

For a scalable filtering infrastructure, a library of filters each usable at different control rates is provided by defining filters in a continuous time mode despite eventual use for digital filtering. For implementation, a filter is selected and discretized for the desired control rate. The discretized filter is then deployed as a discrete time realization for convolution. In a distributed system with multiple control rates, the library may be used to more rapidly and conveniently generate the desired filters.

an FPGA including a first delay line part to which an input pulse having a width corresponding to a time difference between generation times of a start signal and a stop signal is inputted; a code conversion part that converts and outputs an order of elements of a thermometer code outputted from the first delay line part; and a calculation part that determines the generation time difference using a conversion code outputted from the code conversion part, wherein the conversion code is an arrangement of an order of elements of the thermometer code according to a predetermined criterion, and the predetermined criterion is a data path delay from an output node of the input pulse to output nodes of each of a plurality of flip-flops included in the first delay line part.

An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit includes a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a negative signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to a positive signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the negative signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitors of the switched-capacitor circuits in parallel over a fourth time period.

A low-insertion synchronous circuit (10) providing data transfers across clock domains (14, 16) comprises a complementary waveform sampler (12) receiving clock inputs (gclka, gclkb) from both a first clock domain and a second clock domain to determine a phase relationship between domain clocks, A set of edge detectors (18, 19) identify clock edges (r1...r16, f1...f16) in sampled waveform outputs (ws(n)). A set of programmable delay circuits (20, 21) supply a specified delay to a clock of the first clock domain and a set of flying registers (22, 23) can then receive data from either of the clock domains, because those registers are clocked by a clock-specified programmable delay through precision pulse generators (24, 25).