23results about "Delay line applications" patented technology

An operation method includes measuring figure of merit (FoM) values for a first group of presets having different preset types, based on equalized signals output from a transmission equalizer included in an external device adjusted based on the first group, identifying a preset type of a first preset corresponding to first FoM value which is a greatest value from among the FoM values for the first group, measuring FoM values for a second group of presets having the identified preset type, based on equalized signals output from the transmission equalizer adjusted based on the second group, determining a second preset corresponding to second FoM value which is a greatest value from among the first FoM value and the FoM values for the second group, and transmitting an equalizing setup request that controls the transmission equalizer to the external device, based on the determined second preset.

Systems, apparatuses, and methods for managing power and performance in a computing system. A system management unit detects a condition indicating a change in a power-performance state of a given computing unit is indicated. In response to detecting the indication, the system management unit is configured to initiate a change to a frequency of a clock signal generated by an adaptive oscillator by changing a voltage supplied to the adaptive oscillator. The adaptive oscillator is configured to rapidly change a frequency of the clock signal generated in response to detecting a change in a droopy supply voltage of the adaptive oscillator. The new frequency generated by the adaptive oscillator is based in part on a difference between the droopy supply voltage and a regulated supply voltage of the adaptive oscillator.

A receiver includes a first receiving circuit that receives a first data including a first symbol transmitted using three signals over a first data lane, the first data lane including three signal lines respectively corresponding to the three signals. The first receiving circuit includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals.

A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

A digital logic controller including a first delay cell connectable to a signal input and operable to generate a first time delayed input signal, a second delay cell connectable to the signal input and operable to generate a second time delayed input signal, a counter connectable to the signal input via the first delay cell, two logic units to generate reset signal by one of logic units and to generate set signal by the other of logic units, and connected between the set of delay cells and a flip-flop operable to generate a counter valid signal at a flip-flop output, a first comparator connected to an output of the counter and operable to compare a counter output signal with a first target, a first logic gate connected to the flip-flop output, connected to the first comparator and operable to temporally deactivate processing of the counter output signal.

The apparatus includes a clock skew calibration circuit configured to be coupled to the multi-phase clock generator via a plurality of delay lines, wherein the first clock skew calibration unit comprises: a frequency multiplier configured to receive a plurality of multi-phase clock signals and to generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signals and to generate a reduced frequency signal based on the clock signals; and a delay line control circuit configured to compare a duty cycle of the reduced frequency signal with a predetermined duty cycle and to generate a first control signal to adjust the skew of the first multi-phase clock signals by adjusting a first delay applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved.

A multi-stream cross correlator for spiking neural networks, where each stream contains significant stochastic content. At least one event occurs, with a fixed temporal relationship across at least two streams. Each stream is treated as a Frame Of Reference (FOR), and subject to an adjustable delay based on comparison to the Other streams. For each spike of the FOR, a timing analysis, relative to the last and current FOR spikes, is completed by comparing Post and Pre accumulators. Also, a new timing analysis is begun, with the current FOR spike, by restarting the production of Post and Pre weighting functions, the values of which are accumulated, upon the occurrence of each Other spike, until a next FOR spike. A one-spike delay unit can be used, if time-neutral conflict resolution is used. The average spike rate of the FOR can be determined and used for the Post and Pre weighting functions.

A system and method for efficiently capturing data by sequential circuits across multiple operating conditions are described. In various implementations, an integrated circuit includes multiple signal arrival adjusters both at its I / O boundaries and across its die. The signal arrival adjuster includes two internal timing paths, each with a respective latency. The signal arrival adjuster receives an input signal, and generates an output signal from the a selected one of the first timing path and the second timing path. The signal arrival adjuster sends the output signal to a sequential circuit. The sequential circuit uses the output signal as one of an input data signal and an input clock signal. The selection between the two timing paths within the signal arrival adjuster aids satisfying the setup and hold time requirements of the sequential circuit.

An FPGA is disclosed, which includes a first delay line section to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input, a code conversion section that converts the order of the elements of a thermometer code output by the first delay line section and outputs it, and a calculation section that uses the converted code output by the code conversion section to determine the occurrence time difference, wherein the converted code is obtained by arranging the order of the elements of the thermometer code according to a predetermined standard, and the predetermined standard is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the first delay line section.

A multi-stream cross correlator for spiking neural networks, where each stream contains significant stochastic content. At least one event occurs, with a fixed temporal relationship across at least two streams. Each stream is treated as a Frame Of Reference (FOR), and subject to an adjustable delay based on comparison to the Other streams. For each spike of the FOR, a timing analysis, relative to the last and current FOR spikes, is completed by comparing Post and Pre accumulators. Also, a new timing analysis is begun, with the current FOR spike, by restarting the production of Post and Pre weighting functions, the values of which are accumulated, upon the occurrence of each Other spike, until a next FOR spike. A one-spike delay unit can be used, if time-neutral conflict resolution is used. The average spike rate of the FOR can be determined and used for the Post and Pre weighting functions.

The present disclosure provides a device for signal delay. The device comprises: a frame of insulation material; multiple signal electrodes provided in the frame and electrically connected to each other in series; an input terminal electrically connected to a first of the multiple signal electrodes and configured to receive an input signal; and an output terminal electrically connected to a second of the multiple signal electrodes and configured to output an output signal that is delayed by the multiple signal electrodes with respect to the input signal, wherein at least one of the multiple signal electrodes is located at a different height than those of other signal electrodes with respect to a surface on which the device is to be mounted.

Aspects of this disclosure relate to an asynchronous sample rate converter (ASRC) comprising a signal input configured to receive an input signal having one or more input signal values at a first sample rate, a first clock input configured to receive an input clock signal corresponding to the first sample rate, a signal output configured to provide an output signal having one or more output signal values at a second sample rate, a second clock input configured to receive an output clock signal corresponding to the second sample rate, a zero-padding circuit configured to add a plurality of zero values following at least one of the one or more input signal values, and a filter configured to generate the output signal, the output signal having one or more output signal values based on the input signal.

Systems / Methods are disclosed that are configured to perform operations comprising: receiving information; selecting a geographic area responsive to the information received; wirelessly identifying a first motor vehicle that is within the geographic area selected; wirelessly communicating with the first motor vehicle; and wirelessly controlling a first distance between the first motor vehicle and a second motor vehicle. According to some embodiments, said receiving information comprises receiving information regarding a weather condition, a time-of-day and / or an event, wherein according to some embodiments the event comprises an accident. According to further embodiments, a payment is made from an account associated with said first motor vehicle responsive to said controlling.

A method for performing a time-to-digital conversion, comprising: Receiving an input pulse (PIN) indicating time information; Feeding back a representation of the input pulse (PIN) in at least one delay line (807, 1007, 1115, 1117, 1207, 1405) using a feedback signal based on a delay line output signal of the at least one delay line (807, 1007, 1115, 1117, 1207, 1405); Generating an output pulse corresponding to the input pulse (PIN) based at least in part on the delay line output signal of the at least one delay line (807, 1007, 1115, 1117, 1207, 1405); and Supplying the output pulse N times to an integrator coupled to the delay line (807, 1007, 1115, 1117, 1207, 1405), where N is an integer greater than one.

A time capture circuit (20, 20') to measure time between events, in particular edges, of a logic input signal (EXT_SGL, D0), comprising a delay line (D) receiving at its input said input signal (EXT_SGL, D0) and generating a plurality of consecutive increasingly delayed replicas (D1out,...,Dmout,..., DMout) of said logic input signal (EXT_SGL, D0), each replica (Dmout) delayed by a fixed delay (TDm) with respect to the preceding replica (Dm-1out), a free running counter (CNT) which is clocked by a counter clock signal (CNT_CLK) corresponding to an external clock signal (CLK_SYS) multiplied by a clock scale factor (CLK_CNT_PRS) and supplies a counter value (x) to a counter value capture block (CAPT_CNT), said counter value capture block (CAPT_CNT) receiving also said input signal (EXT_SGL, D0) and being configured to capture said counter value (x) upon the occurrence of an event (E1, E2; C1, C2) in said input signal outputting a captured counter value (CAPT_CNTout) and issuing a trigger signal (CAPT_CNTtrg), a decoder module (CAPT_DECODE) receiving as inputs said input signal (EXT_SGL, D0), said plurality of delayed replicas (D1out,..., Dmout,..., DMout) and said captured counter value (CAPT_CNTout) and said trigger signal (CAPT_CNTtrg), said decoder module (CAPT_DECODE) being configured to determine a decoded value (CAPT_DCD)) on the basis of at least the values of said input signal (EXT_SGL, D0) and of said plurality of consecutive increasingly replicas (D1out,...,Dmout,..., DMout) when the trigger signal (CAPT_CNTtrg) is issued and to compute a capture value (HRS_CAPT_VAL) as the difference of said captured counter value (CAPT_CNTout) logical left shifted by a first scale factor (CLK_CAPT_PRS) and said decoded value (CAPT_DCD) logical right shifted by a second scale factor (N- CLK_CAPT_PRS).

For a scalable filtering infrastructure, a library of filters each usable at different control rates is provided by defining filters in a continuous time mode despite eventual use for digital filtering. For implementation, a filter is selected and discretized for the desired control rate. The discretized filter is then deployed as a discrete time realization for convolution. In a distributed system with multiple control rates, the library may be used to more rapidly and conveniently generate the desired filters.

Disclosed is an FPGA comprising: a first delay line part into which an input pulse having, as a width, a generation time difference between a start signal and an end signal is input; a code conversion part that converts the order of elements of thermometer code output by the first delay line part and outputs same; and an operation part that determines the generation time difference by using conversion code output by the code conversion part, wherein the conversion code is obtained by aligning the order of elements of the thermometer code according to a predetermined standard, and the predetermined standard is a data path delay from an output node of the input pulse to output nodes of each of a plurality of flipflops included in the first delay line part.

an FPGA including a first delay line part to which an input pulse having a width corresponding to a time difference between generation times of a start signal and a stop signal is inputted; a code conversion part that converts and outputs an order of elements of a thermometer code outputted from the first delay line part; and a calculation part that determines the generation time difference using a conversion code outputted from the code conversion part, wherein the conversion code is an arrangement of an order of elements of the thermometer code according to a predetermined criterion, and the predetermined criterion is a data path delay from an output node of the input pulse to output nodes of each of a plurality of flip-flops included in the first delay line part.

An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit includes a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a negative signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to a positive signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the negative signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitors of the switched-capacitor circuits in parallel over a fourth time period.

The present invention relates to a multi-stream cross-correlator for a spiking neural network, wherein each stream contains significant random content. At least one event occurs with a fixed temporal relationship across at least two streams. Each stream is considered a reference frame (FOR) and is subject to an adjustable delay based on comparison with the other streams. For each spike in the FOR, a timing analysis relative to the last and current FOR spike is performed by comparing the Post accumulator with the Pre accumulator. Furthermore, a new timing analysis is started with the current FOR spike by restarting the generation of Post and Pre weighting functions, accumulating the values ​​of the Post and Pre weighting functions immediately after each additional spike until the next FOR spike. If time-neutral collision resolution is used, a single spike delay unit can be used. The average spike rate of the FOR can be determined and used in the Post and Pre weighting functions.

A low-insertion synchronous circuit (10) providing data transfers across clock domains (14, 16) comprises a complementary waveform sampler (12) receiving clock inputs (gclka, gclkb) from both a first clock domain and a second clock domain to determine a phase relationship between domain clocks, A set of edge detectors (18, 19) identify clock edges (r1...r16, f1...f16) in sampled waveform outputs (ws(n)). A set of programmable delay circuits (20, 21) supply a specified delay to a clock of the first clock domain and a set of flying registers (22, 23) can then receive data from either of the clock domains, because those registers are clocked by a clock-specified programmable delay through precision pulse generators (24, 25).