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3results about "Delay line applications" patented technology

Method and apparatus for cross correlation

A multi-stream cross correlator for spiking neural networks, where each stream contains significant stochastic content. At least one event occurs, with a fixed temporal relationship across at least two streams. Each stream is treated as a Frame Of Reference (FOR), and subject to an adjustable delay based on comparison to the Other streams. For each spike of the FOR, a timing analysis, relative to the last and current FOR spikes, is completed by comparing Post and Pre accumulators. Also, a new timing analysis is begun, with the current FOR spike, by restarting the production of Post and Pre weighting functions, the values of which are accumulated, upon the occurrence of each Other spike, until a next FOR spike. A one-spike delay unit can be used, if time-neutral conflict resolution is used. The average spike rate of the FOR can be determined and used for the Post and Pre weighting functions.
Owner:NETBASE SOLUTIONS INC

TDC and FPGA including the same that can increase time resolution

An FPGA is disclosed, which includes a first delay line section to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input, a code conversion section that converts the order of the elements of a thermometer code output by the first delay line section and outputs it, and a calculation section that uses the converted code output by the code conversion section to determine the occurrence time difference, wherein the converted code is obtained by arranging the order of the elements of the thermometer code according to a predetermined standard, and the predetermined standard is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the first delay line section.
Owner:SDT INC

TDC for enhancing time resolution, and FPGA including same

PendingEP4701082A2Delay line applicationsLogic circuits using elementary logic circuit components
an FPGA including a first delay line part to which an input pulse having a width corresponding to a time difference between generation times of a start signal and a stop signal is inputted; a code conversion part that converts and outputs an order of elements of a thermometer code outputted from the first delay line part; and a calculation part that determines the generation time difference using a conversion code outputted from the code conversion part, wherein the conversion code is an arrangement of an order of elements of the thermometer code according to a predetermined criterion, and the predetermined criterion is a data path delay from an output node of the input pulse to output nodes of each of a plurality of flip-flops included in the first delay line part.
Owner:SDT INC