The utility model discloses a high-speed serial
bus transmission circuit, which comprises a main
control circuit, and the main
control circuit comprises an FPGA (
field programmable gate array), a CLKIO (
clock line input / output), a DATAIO (data address input / output) and an LTC2879XMS8E
chip. An acquisition node circuit, wherein the acquisition node circuit comprises an FPGA (
Field Programmable Gate Array), a CLKIO, a DATAIO and an LTC2879XMS8E
chip; and a level conversion circuit, wherein the level conversion circuit comprises a
resistor and an LTC2879XMS8E
chip. According to the utility model, the circuit structure design is optimized, through the arrangement of the master
control circuit, the acquisition node circuit and the level conversion circuit, the communication between one master control and a plurality of acquisition nodes is realized, the acquisition nodes are distinguished by different addresses, the communication efficiency is high, the external common-mode
noise can be completely counteracted, and the reliability is high. Signals are transmitted in a differential mode, the anti-interference capacity of communication is improved, the structural design that the two sets of shielding twisted pairs are combined is adopted, the two wires are close to each other and equal in
signal amplitude, the amplitudes of
coupling electromagnetic fields between the two wires and the ground wire are also equal, the
signal polarities of the two wires and the ground wire are opposite, and according to the right-hand spiral rule, the
signal polarities of the two wires are different. The magnetic lines of force are mutually offset, and the anti-
electromagnetic interference capability is strong.