21 results about "Fixed length" patented technology

The invention relates to the technical field of data storage, and discloses a numerical data variable-length coding storage method, device, equipment and medium, which comprises the following steps: converting target numerical data into fixed-length binary representation according to definition precision, executing filling removal interception processing on an integer part, executing digital-level packet compression coding on a decimal part, and performing variable-length coding on the target numerical data; and generating a variable-length binary sequence containing length information and symbol information, and writing the sequence into a storage medium to realize compact storage of numerical data. According to the method, redundant filling bytes are eliminated from an integer part, compressed encoding is performed on a decimal part according to effective digits, and unified processing of sign bits is combined, so that a storage space dynamically changes along with actual numerical digits on the premise of keeping numerical precision and analyzability, space waste of fixed-length numerical types is reduced, and the method is suitable for large-scale popularization and application. Meanwhile, the precision error of the floating-point number is avoided, and the storage efficiency and the data reliability are improved.

Methods and systems are provided for decoding variable-length codes in a parallel process. A stream of variable-length code words is divided into fixed length words. A plurality of parallel sets of decoder circuits each receive, in parallel, a current fixed length word and a prior fixed length word. Each decoder circuit has a respective fixed leftover bit-count. Each decoder circuit generates a respective output that may include a decoded symbol and a new leftover bit-count. Each respective output is determined based on the respective current fixed length word, the respective prior fixed length word, and the respective fixed leftover bit-count. A set of selected decoder circuit outputs is generated for each set of the parallel sets of decoder circuits based on a set of first leftover bit-counts. One output from each set of selected decoder circuit outputs is selected as a final output based on a second prior leftover bit-count.

The invention provides a multi-version management method for database fixed-length fields, a medium and a product. The multi-version management method for the database fixed-length fields comprises the steps of configuring a preset shadow version number for target fixed-length fields or target fixed-length field groups in a database table; constructing a shadow column set for the target fixed-length field or the target fixed-length field group in the row of the database table; constructing a plurality of shadow versions in the shadow column set into an end-to-end circular queue, and setting an identifier to record a serial number of a current writable version in the circular queue; and in response to a data read-write request, performing read-write operation on the shadow version in the circular queue based on the visibility auxiliary information corresponding to the shadow version, the serial number of the writable version and a preset visibility judgment rule, thereby realizing multi-version management of the target fixed-length field or the target fixed-length field group. According to the scheme, the method is adaptive to a specific scene in which the fixed-length fields are frequently updated and only a limited historical version is needed; and constant storage occupation and stable read-write performance are ensured.

The application provides a high-efficiency KV encoding storage method based on a Redis protocol, and has the characteristics that all Key meta information of a data object is stored in an object key; and descriptive information of the data object, keys of each field in the data object, and values of each field in the data object are all stored in an object value. Preferably, in the high-efficiency KV encoding storage method based on the Redis protocol, the object value is encoded in blocks in a fixed length, a block header of each block stores descriptive information of the data object value, and the rest of each block stores the keys and values of the fields. Preferably, in the high-efficiency KV encoding storage method based on the Redis protocol, the fixed length of the block is an integer multiple of an operating system block. The encoding and storage method of the application reduces the number of I / Os, the number of Key encodings, saves computing resources, and improves the read-write efficiency.

The embodiment of the present application provides a data processing method, which comprises: determining first information, the first information being used for indicating a preset byte length of a data segment of a target field, the target field being a field in a database table, and the data type being a fixed-length string type; writing a target string into the data segment of the target field, the byte length of the data segment being equal to the byte length of the target string, and the byte length of the data segment being smaller than the preset byte length; and writing second information into a data header, the second information being used for indicating the byte length of the target field. The writing of the target string is completed. The byte length of the field after the writing is still the actual data length of the target string. Thus, the storage space occupied by the field of the fixed-length string type is optimized. Furthermore, by also writing the first information into the field, the preset byte length can be read when the target string is read subsequently, so as to perform other operations.

Disclosed in the present invention is a real-time recursive CRC method. The method comprises: sequentially extracting from a real-time bit stream a1a2a3… binary sequences S1S2…Si… at non-fixed lengths; bisecting into left and right parts each binary sequence segment Si, so as to obtain sub-sequences, and repeatedly bisecting into left and right parts the sub-sequences until the lengths of finally obtained sub-sequences are less than a preset value; and calculating a CRC check value and check matrix of each final sub-sequence, and performing level-by-level upward merging calculation on left and right sub-sequences, so as to obtain a final check value of the entire real-time bit stream. Further disclosed in the present invention are a corresponding CRC apparatus and a computer storage medium and a program for implementing the CRC method. In the present invention, a method combining iteration with recursion is used to calculate, in real time, a check value of a variable-length binary sequence stream, thereby achieving logarithmic calculation time complexity and meeting CRC operation requirements of a real-time ultra-high-speed data stream.

There are provided systems and methods for reducing quantization errors, including method of optimizing a routine for a hardware-based processing system having a fixed length two's complement binary representation, the method comprising: receiving an instruction sequence arranged to perform the routine, wherein the instruction sequence comprises a set of arithmetic operations, wherein the outputs of the arithmetic operations exceed a precision of the hardware-based processing system; identifying one or more pairs of sub-sets of instructions in the sequence of instructions, the sub-sets of each pair having a respective comparable truncation error; and generating an optimized routine by modifying one of the sub-sets of each pair to invert the sign of one or more inputs to said sub-sets and modifying the instruction sequence to compensate for the said inversion.

This invention discloses a caching method and system for structured streaming data. The method includes: setting up a cache space using different pre-allocation methods based on the type and length of the structured streaming data to be received; wherein, when the data is fixed-length, a fixed-length cache space is pre-allocated; when the data is variable-length, a variable-length cache space or a composite cache space is pre-allocated; receiving structured streaming data, when the data is fixed-length, storing the structured streaming data in the pre-allocated fixed-length cache space; when the data is variable-length, dynamically expanding the pre-allocated cache space according to the actual length of the received structured streaming data until the structured streaming data is completely stored. This invention fundamentally solves the overflow problem that fixed-length cache spaces may face, while the application of the variable-length caching mechanism also greatly saves storage space, balancing the needs of memory resource optimization and caching performance.

The invention discloses a short character string monotonic order-preserving materialized compression coding method, which comprises the following steps of: performing a series of bit operations such as byte inversion, length information embedding, logic right shift and high-order mask shielding on an original variable-length character string with a limited length, and losslessly mapping the original variable-length character string into a fixed-length integer value; the lexicographical order of the character string before and after mapping is completely consistent with the numerical order of the integer; according to the method, the fixed-length integer code is used for directly replacing an original character string to participate in sequencing, aggregation and comparison operation of the database, so that the problems of branch prediction failure, discontinuous memory access, vectorization difficulty and the like caused by processing variable-length data in a traditional scheme are greatly avoided, the memory occupancy is greatly reduced, and meanwhile, the vectorization efficiency is improved. And the CPU execution efficiency and the cache utilization rate are greatly improved.

The invention relates to the technical field of graph data processing, and provides a graph data processing method based on cache optimization, which comprises the following steps: constructing a cache optimization representation of graph data, and distributing a bit vector GT-vector with a fixed length of k for each vertex in a graph, each bit representing whether the vertex belongs to a pre-calculated maximum independent set; reserving adjacency list representation of the graph data, and storing the adjacency list representation as reference data in a memory; for an edge query request, reading GT-vectors of two vertexes from a CPU cache, and executing bit and operation; if the bit and the result are non-zero, judging that the edge is non-edge and immediately returning a first Boolean result indicating that the edge does not exist; and if the bit and result is zero, querying the adjacency list in the memory for verification, and returning a second Boolean result indicating that the edge exists or does not exist. According to the method and the device, the hybrid architecture combining the bit vector representation of cache optimization and the adjacency list is constructed, so that the magnitude order improvement of the graph data processing performance is realized on the premise of ensuring that the query result is completely accurate.

The embodiment of the present application provides a time delay reporting method, which comprises the following steps: reporting target time delays corresponding to data in multiple specific positions in a data stream, wherein the multiple specific positions are spaced apart by a fixed length; wherein: the period of the multiple specific positions corresponds to the length of one or more convolution interleaving sequences, the specific positions correspond to delay lines with the maximum or minimum introduced time delay in the convolution interleaving; or, the period of the multiple specific positions corresponds to the length of one or more distribution sequences, each of the distribution sequences corresponds to eight sub-sequences after distribution; or, the period of the multiple specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponds to a forward error correction (FEC) code word, N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits. According to the scheme, time delay can be accurately reported.

The application discloses a DNA storage coding method with local GC content balance, which adopts a four-element sequence coding method for original data, and adopts a splicing method to splice a GC content globally balanced code word set for several times, so that a new four-element code satisfies the GC content local balance, so that the four-element DNA sequence composed of A, T, C and G can be more conveniently corresponded, and the base substitution error and the base insertion and deletion error can be respectively corrected by combining a Hamming code and a VT code. Furthermore, the GC content of the DNA coding can be finally ensured to be globally stable at 40% to 60% by selecting the code word satisfying the GC content in the Hamming code, and the DNA segment in each fixed length sliding window satisfies the GC content stable at 30% to 70%.

Provided in the embodiments of the present application is a delay reporting method. The method comprises: reporting target delays corresponding to data at a plurality of specific positions in a data stream, wherein the plurality of specific positions are spaced apart from each other by a fixed length, the period of the plurality of specific positions corresponds to the length of one or more convolutional interleaving sequences, and the specific positions correspond to delay lines having the maximum or minimum delay introduced in convolutional interleaving, alternatively, the period of the plurality of specific positions corresponds to the length of one or more distribution sequences, and each distribution sequence corresponds to eight distributed sub-sequences, alternatively, the period of the plurality of specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponds to one forward error correction (FEC) codeword, N is a positive integer, and the length of each data block is 120 bits, 128 bits, 110 bits or 126 bits. By using the present solution, a delay can be accurately reported.

The application relates to the chip technical field, in particular to a method, equipment and medium for generating function coverage based on indefinite-length data packets, which comprises the following steps: S1, initially setting i=1, C i =0, L i =0; S2, when a first i data packet file header is read, obtaining a data packet length U i , updating L i =U i ; S3, continuously reading and updating C i =C i +B i ; S4, storing the read data into D i , and stopping storing data into D i when D i is full or C i =L i ; S5, when C i =L i , judging whether the data packets in the chip code are read completely, if yes, executing S6, otherwise, updating a next to-be-read position as a current start position, updating i=i+1, updating C i =0, L i =0, and returning to S2; S6, generating function coverage based on all data packet data in a preset fixed-length buffer area. The application improves the collection efficiency of chip function coverage.

The invention discloses an efficient topology and attribute storage method and device oriented to an RAG knowledge graph, graph topology and attribute data are separately stored, so that the size of a storage file of an obtained topological structure does not exceed the maximum use space of a memory, and therefore, when topological structure traversal is carried out, the storage efficiency of the storage file is greatly improved. According to the method, the topological structure can be completely read into the memory, so that the problem that the disks need to jump one by one along a chain structure in the traditional technology is avoided, and the topological access efficiency is improved; meanwhile, initial offset and length information during storage of variable-length attribute data are maintained in fixed-length attribute records, and the fixed-length attributes are sequentially stored according to IDs and are loaded through memory mapping, so that direct access can be realized within O (1) time without deserialization, the variable-length attributes are accessed through offset indexes, and the access efficiency is improved. The problem of multi-layer structure analysis is also avoided; therefore, the graph data access performance and the system concurrency capability are remarkably improved.

The embodiment of the invention provides a method, a device, equipment and a medium for judging the packet receiving length in a control packet receiving process, and the method comprises the steps: obtaining an operation code of a control packet when the control packet is received; obtaining a first subsequent data length contained in a packet header in the control packet according to a length field of the control packet; determining the packet receiving length of the control packet according to the operation code and the first subsequent data length; wherein the packet receiving length of the control packet is the data length after the length field. The length field of the packet header is verified through the operation code of the control packet, inconsistency of the length field of the packet header and the fixed length corresponding to the operation code can be found in the packet receiving process, errors can be found in real time, and time delay of a sending mode is avoided. By determining the real packet receiving length, it is ensured that the receiving mode and the sending mode of the current connection interval are switched at the correct time point, and the time sequence is correct. Especially in a high throughput rate scene, invalid transmission in the interval is reduced, the overall speed is improved, and the throughput rate is improved.

This invention discloses a method, system, device, storage medium, and program product for expanding the capacity of a fixed-length counting array based on address translation to prevent overflow. The method includes the following steps: Step 1: Determine the data type and length of the array counting, and allocate contiguous memory; Step 2: Check if the highest column of the array counting has overflowed. If not, increment the count; if overflowed, jump to Step 3; Step 3: Check the non-highest bit. If the lower 15 bits of the address are not all zeros, jump to Step 4; if they are all zeros, jump to Step 5; Step 4: Calculate the new address position based on the offset of the lower 15 bits, and jump to Step 6; Step 5: Allocate a new memory block, record the offset between the new and old addresses in the lower 15 bits of the original address, and jump to Step 6; Step 6: Increment the uint32 type count of the new address by 1, check if the highest bit is 1. If the highest bit is 1, overflow occurs again, and steps 5 to 6 are repeated. This invention provides an address translation-based scheme that can continue to collect counts and avoid copying existing memory, thus avoiding memory waste, and providing efficient statistical and query performance.

This invention provides a simple lossless image compression and decoding method, including: S1, lossless compression: S1.1, calculate the difference between the current pixel and the previous pixel; determine if the difference is 0? S1.2, if it is 0, update the counter and the next pixel value; if the next pixel is empty, perform Golomb encoding on the counter to S1.4; if not empty, return to S1.1; S1.3, if it is not 0, first perform Golomb encoding on the non-zero Count, then use 5-bit or 8-bit fixed-length encoding for pixels with non-zero differences, and set a 5-bit difference threshold; update the next pixel; if the next pixel is empty, go to S1.4; if not empty, return to S1.1; S1.4, encoding ends; S2, lossless decoding: S2.1, record the current bit; determine if the current bit is 0? S2.2, if it is 0, then perform 0th order Columbus decoding; then proceed to S2.4; S2.3, if it is not 0, then perform right shift of the bit by 2+5 or 2+8 bits for decoding, with the first two bits as an identifier, then proceed to S2.4; S2.4, determine if the bit is empty? If yes, end; otherwise, return to S2.1.

The invention relates to a data encapsulation and extraction method based on a custom mark, electronic equipment and a medium. The method comprises the following steps: opening or creating a target file and positioning to the end of the file; sequentially writing to-be-stored to-be-packaged files at the tail of the target file, wherein each to-be-packaged file comprises a preset start mark, a length identifier and a data entity which are sequentially written into the target file; the start mark is composed of a beginning 0xFF and a plurality of ASCII characters written behind the 0xFF; the length identifier is used for representing the byte length of the to-be-packaged file, adopts an integer with a fixed length and is written according to a certain byte order; the data entity is the data content of the to-be-packaged file; meanwhile, the invention discloses an extraction method for extracting the file, electronic equipment formed according to the method and a medium. According to the method, heterogeneous data can be closely and efficiently stored in a single file in an associated mode, and any part of data in the heterogeneous data can be rapidly and independently extracted.

The present subject matter relates to a procedure as follows. A current proof state can be encoded in a vector of real numbers of fixed length. The current proof state defines a task for proving at least part of the statement. The vector can be encoded in a quantum state of a quantum system of the quantum computer. The quantum state can be used as an input quantum state by a quantum computer learning model to generate an output quantum state, the measurement of which constitutes a proof step for the defined task. The proof step can be provided to the proof assistant. In response to the provision of the proof step, a next proof state can be received by the proof assistant. It can be determined whether the received proof state indicates that the proof is complete.If it is determined that the evidence is not complete, the received state of evidence can be used as the current state of evidence for repeating the proceedings.

The application discloses a method for determining operation instructions in a frame synchronization process, which is applied to the technical field of frame synchronization and is executed by a server. The server is connected with at least two clients. The method comprises the following steps: receiving operation instructions sent by at least one client in the at least two clients; determining a first length of a current frame based on a fixed number of operation instructions carried by a single frame; determining a second length of a redundant frame based on network parameters between the server and the at least two clients; obtaining a residual length of at least one data packet according to a fixed length of a single data packet, the first length and the second length; and determining an extended number of instructions of the current frame according to the residual length of the at least one data packet. Under the premise of meeting the required number of redundant frames, the current frame is dynamically extended to carry more operation instructions, more operation instructions can be sent from the server to the clients, and the game experience of players can be improved.