A method and apparatus for reporting latency

Abstract

The embodiment of the present application provides a time delay reporting method, which comprises the following steps: reporting target time delays corresponding to data in multiple specific positions in a data stream, wherein the multiple specific positions are spaced apart by a fixed length; wherein: the period of the multiple specific positions corresponds to the length of one or more convolution interleaving sequences, the specific positions correspond to delay lines with the maximum or minimum introduced time delay in the convolution interleaving; or, the period of the multiple specific positions corresponds to the length of one or more distribution sequences, each of the distribution sequences corresponds to eight sub-sequences after distribution; or, the period of the multiple specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponds to a forward error correction (FEC) code word, N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits. According to the scheme, time delay can be accurately reported.

Description

[0001] This application claims priority to the Chinese Patent Application No. 202410565639.8, filed on May 8, 2024, and entitled "A Time Delay Reporting Method and Device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication, and in particular to a time delay reporting method and device. BACKGROUND

[0003] Data interaction can be performed between communication devices. A sender can send a message to a receiver, and the sender can add a sending timestamp of the message in the message sent to the receiver. Correspondingly, after receiving the message sent by the sender, the receiver can record a receiving timestamp of the message, so as to perform subsequent processing measures based on the sending timestamp and the receiving timestamp. For example, in a time synchronization scenario, the receiver can perform time synchronization based on the sending timestamp and the receiving timestamp. The sender can be understood as a communication device as the sender, and the receiver can be understood as a communication device as the receiver.

[0004] The accuracy of the sending timestamp and the accuracy of the receiving timestamp directly affect the accuracy of the results obtained by performing subsequent processing measures. For example, in the time synchronization scenario, the accuracy of the sending timestamp and the receiving timestamp directly affects the precision of time synchronization.

[0005] Therefore, how the sender accurately determines the sending timestamp of the message and how the receiver accurately determines the receiving timestamp of the message are problems to be solved. SUMMARY

[0006] Embodiments of the present application provide a time delay reporting method and device, which can accurately report time delay.

[0007] In a first aspect, the present application provides a method for reporting a time delay. The method can be applied to a first module. The first module can report a target time delay corresponding to data at a plurality of specific positions in a data stream. The plurality of specific positions are spaced apart by a fixed length. In one specific example, a period of the plurality of specific positions corresponds to a length of one or more convolution interleaving sequences. When the first module corresponds to a sending end, the specific positions correspond to delay lines that introduce a maximum time delay in a convolution interleaving. When the first module corresponds to a receiving end, the specific positions correspond to delay lines that introduce a minimum time delay in a convolution interleaving. In this scenario, when the first module corresponds to the sending end, the target time delay corresponding to data at the specific positions is equivalent to a maximum time delay introduced by the convolution interleaving. When the first module corresponds to the receiving end, the target time delay corresponding to data at the specific positions is equivalent to a minimum time delay introduced by the de-convolution interleaving. In another specific example, a period of the plurality of specific positions corresponds to a length of one or more distribution sequences. Each of the distribution sequences corresponds to eight sub-sequences after distribution. In this scenario, when the first module corresponds to the sending end, the target time delay corresponding to data at the specific positions is equivalent to a maximum time delay introduced by the distribution. When the first module corresponds to the receiving end, the target time delay corresponding to data at the specific positions is equivalent to a minimum time delay introduced by the multiplexing. In yet another specific example, a period of the plurality of specific positions corresponds to an integer multiple of N data blocks. Each of the N data blocks corresponds to a forward error correction (FEC) code word. N is a positive integer. The length of each data block is 120 bits, or 128 bits, or 110 bits, or 126 bits. In this scenario, when the first module corresponds to the sending end, the target time delay corresponding to data at the specific positions is equivalent to a maximum time delay introduced by FEC encoding. When the first module corresponds to the receiving end, the target time delay corresponding to data at the specific positions is equivalent to a minimum time delay introduced by FEC decoding. Therefore, in the embodiments of the present application, if the first module corresponds to the sending end, the target time delay corresponding to data at the specific positions is equivalent to a maximum time delay. If the first module corresponds to the receiving end, the target time delay corresponding to data at the specific positions is equivalent to a minimum time delay. Thus, the present application can accurately report a time delay.

[0008] In a possible implementation, the convolution interleaving corresponds to three delay lines. The delay line that introduces the maximum or minimum time delay is the first delay line among the three delay lines. Specifically, when the first module corresponds to the sending end, the delay line that introduces the maximum time delay is the first delay line among the three delay lines. When the first module corresponds to the receiving end, the delay line that introduces the minimum time delay is the first delay line among the three delay lines.

[0009] In a possible implementation, for the sending end, when performing the convolution interleaving operation, the first delay line is configured to delay each data unit received thereby by 2*Q*D bits, the second delay line of the three delay lines is configured to delay each data unit received thereby by Q*D bits, and the third delay line of the three delay lines does not perform delay operation on each data unit received thereby, where D is the number of bits included in each data unit, and Q is a positive integer. For the receiving end, when performing the inverse convolution deinterleaving operation, the third delay line is configured to delay each data unit received thereby by 2*Q*D bits, the second delay line is configured to delay each data unit received thereby by Q*D bits, and the first delay line does not perform delay operation on each data unit received thereby.

[0010] In an example, the value of Q is related to the interface rate. When the interface rate corresponds to 200G BASE-R, Q=544. When the interface rate corresponds to 400G BASE-R, Q=272. When the interface rate corresponds to 800G BASE-R, Q=136. When the interface rate corresponds to 1.6T BASE-R, Q=68.

[0011] In a possible implementation, the convolution interleaving corresponds to three delay lines, and the delay line that introduces the maximum or minimum delay is the third delay line of the three delay lines. Specifically, when the first module corresponds to the sending end, the delay line that introduces the maximum delay is the third delay line of the three delay lines in the convolution interleaving, and when the first module corresponds to the receiving end, the delay line that introduces the minimum delay is the third delay line of the three delay lines in the convolution interleaving.

[0012] In a possible implementation, for the sending end, when performing the convolution interleaving operation, the first delay line does not perform delay operation on each data unit received thereby, the second delay line of the three delay lines is configured to delay each data unit received thereby by 6*D bits, and the third delay line of the three delay lines is configured to delay each data unit received thereby by 12*D bits, where D is the number of bits included in each data unit. For the receiving end, when performing the convolution interleaving operation, the third delay line does not perform delay operation on each data unit received thereby, the second delay line is configured to delay each data unit received thereby by 6*D bits, and the first delay line is configured to delay each data unit received thereby by 12*D bits.

[0013] In a possible implementation, the number of data units included in each of the convolution interleaving sequences is equal to the number of delay lines of the convolution interleaving. For example, the number of delay lines can be 3 lines, in which case each convolution interleaving sequence can include 3 data units. In an example, each of the 3 data units includes 40 bits. In other words, each convolution interleaving sequence can include 120 bits.

[0014] In a possible implementation, the sending end can perform a 1:8 distribution operation on a distribution sequence, i.e., distribute the distribution sequence into 8 streams. In this case, each distribution sequence can include 8 data blocks, and each stream can be distributed with one data block. The data block distributed in each stream can also be referred to as a sub-sequence of the distribution sequence. In other words, after a distribution sequence is subjected to a 1:8 distribution operation, 8 sub-sequences can be obtained. Correspondingly, the receiving end can perform an 8:1 multiplexing operation on the data blocks in the 8 streams to obtain a distribution sequence. In this case, since the data block distributed in the first stream has the longest waiting time when the sending end performs the 1:8 distribution operation, and the data block in the first stream has the shortest waiting time when the receiving end performs the 8:1 multiplexing operation, the specific position can correspond to the first stream among the aforementioned 8 streams.

[0015] In a possible implementation, if the sending end needs to perform 8:1 code word interleaving after performing inner code FEC encoding, the value of N can be 8. In other words, the period of the plurality of specific positions corresponds to an integer multiple of 8 data blocks, and each of the 8 data blocks corresponds to an FEC code word.

[0016] In a possible implementation, if the sending end needs to perform 32:1 code word interleaving after performing inner code FEC encoding, the value of N can be 32. In other words, the period of the plurality of specific positions corresponds to an integer multiple of 32 data blocks, and each of the 32 data blocks corresponds to an FEC code word.

[0017] In a possible implementation, the FEC code word is an FEC inner code code word subjected to outer code FEC encoding and then inner code FEC encoding. In this case, the data stream can be a data stream subjected to outer code FEC encoding and received by an attachment unit interface (AUI) of a module performing inner code FEC.

[0018] In a possible implementation, the FEC inner code code word is a Hamming code code word. In a specific example, the sending end can perform inner code FEC encoding by using Hamming code encoding, and perform 8:1 code word interleaving on the obtained FEC inner code code word.

[0019] In a possible implementation, the FEC inner code codeword is a Bose Chaudhuri Hocquenghem (BCH) code codeword. In one specific example, the sending end can perform inner code FEC encoding by using BCH code encoding, and perform 32:1 codeword interleaving on the obtained FEC inner code codeword.

[0020] In a possible implementation, after the receiving end receives the FEC inner code codeword that is subjected to inner code FEC encoding, the receiving end can perform inner code FEC decoding on the FEC inner code codeword. In one example, if the first module corresponds to the receiving end, the data stream can also be a data stream obtained by the receiving end performing inner code FEC decoding.

[0021] In a possible implementation, considering that, for the sending end, the starting position of the convolution interleaving sequence introduces the maximum time delay when the sending end performs convolution interleaving operation, and for the receiving end, the starting position of the convolution interleaving sequence introduces the minimum time delay when the receiving end performs inverse convolution deinterleaving operation, the specific position corresponds to the starting position of the one or more convolution interleaving sequences. The starting position can be the first bit, the first symbol, or the first byte.

[0022] In a possible implementation, considering that, for the sending end, the starting position of the distribution sequence introduces the maximum time delay when the sending end performs distribution operation, and for the receiving end, the starting position of the distribution sequence introduces the minimum time delay when the receiving end performs multiplexing operation, the specific position corresponds to the starting position of the one or more distribution sequences.

[0023] In a possible implementation, considering that, for the sending end, the starting position of the N data blocks introduces the maximum time delay when the sending end performs inner code FEC encoding, and for the receiving end, the starting position of the N data blocks introduces the minimum time delay when the receiving end performs inner code FEC decoding, the specific position corresponds to the starting position of an integer multiple of the N data blocks.

[0024] In a possible implementation, each of the data of the plurality of specific positions can correspond to a first time delay. Therefore, the data of the plurality of specific positions can correspond to a plurality of first time delays. It is considered that the institute of electrical and electronics engineers (IEEE) 802.3cx chapter 90 defines a corresponding maximum time delay register and a minimum time delay register for each layer of the physical layer. Therefore, in order to be compatible with the mechanism of the current IEEE 802.3cx chapter 90 for reporting the time delay of the physical layer, the maximum value and / or the minimum value of the plurality of first time delays can be reported. In other words, the target time delay can be the maximum value and / or the minimum value of the plurality of first time delays. In this case, the first module can further measure the first time delay corresponding to each of the data of the plurality of specific positions to obtain a plurality of first time delays, so as to report the maximum value and / or the minimum value of the plurality of first time delays, and to realize the reporting of the time delay information.

[0025] In a possible implementation, the first module reports the target time delay. In a specific implementation, the target time delay can be reported to a second module. In an example, the second module can be a media access control (MAC) layer module of the communication device, so that the MAC layer module can compensate for a time stamp recorded by itself based on the target time delay, so that the time stamp after compensation is more accurate.

[0026] In a second aspect, the present application provides a time delay reporting device, the device comprising: a sending unit configured to report a target time delay corresponding to data of a plurality of specific positions in a data stream, the plurality of specific positions being spaced apart by a fixed length; wherein: a period of the plurality of specific positions corresponds to a length of one or more convolution interleaving sequences, the specific positions corresponding to delay lines introducing maximum or minimum time delays in convolution interleaving; or, a period of the plurality of specific positions corresponds to a length of one or more distribution sequences, each of the distribution sequences corresponding to eight sub-sequences after distribution; or, a period of the plurality of specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponding to a forward error correction (FEC) code word, N being a positive integer, and a length of each of the data blocks being: 120 bits, or 128 bits, or 110 bits, or 126 bits.

[0027] In a possible implementation, the delay line introducing the maximum or minimum time delay is a first delay line of three delay lines in convolution interleaving.

[0028] In a possible implementation, the first delay line is configured to delay each data unit received thereby by 2*Q*D bits, the second delay line in the three delay lines is configured to delay each data unit received thereby by Q*D bits, and the third delay line in the three delay lines is not configured to delay each data unit received thereby, where D is the number of bits included in each data unit, and Q is a positive integer; or, the third delay line is configured to delay each data unit received thereby by 2*Q*D bits, the second delay line is configured to delay each data unit received thereby by Q*D bits, and the first delay line is not configured to delay each data unit received thereby.

[0029] In a possible implementation, Q is equal to 544, 272, 136, or 68.

[0030] In a possible implementation, the delay line with the maximum or minimum introduced delay is the third delay line in the three delay lines in the convolution interleaving.

[0031] In a possible implementation, the first delay line is not configured to delay each data unit received thereby, the second delay line in the three delay lines is configured to delay each data unit received thereby by 6*D bits, and the third delay line in the three delay lines is configured to delay each data unit received thereby by 12*D bits, where D is the number of bits included in each data unit; or, the third delay line is not configured to delay each data unit received thereby, the second delay line is configured to delay each data unit received thereby by 6*D bits, and the first delay line is configured to delay each data unit received thereby by 12*D bits.

[0032] In a possible implementation, each convolution interleaving sequence includes 3 data units, and each data unit in the 3 data units includes 40 bits.

[0033] In a possible implementation, each distribution sequence includes 8 data blocks, each distribution sequence is configured to perform 1:8 distribution processing, or each distribution sequence is a sequence corresponding to the first stream in 8 streams corresponding to 1:8 distribution processing or 8:1 multiplexing processing.

[0034] In a possible implementation, N is equal to 8 or 32; or the FEC code word is an FEC inner code code word obtained by performing outer code FEC encoding and then inner code FEC encoding; or, the FEC inner code code word is a Hamming code code word or a BCH code code word; or, the data stream is a data stream received through an attachment unit interface (AUI); or, the data stream is a data stream obtained by performing inner code FEC decoding.

[0035] In a possible implementation, the specific position corresponds to a starting position of the one or more convolution interleaving sequences; or, the specific position corresponds to a starting position of the one or more distribution sequences; or, the specific position corresponds to a starting position of an integer multiple of the N data blocks; the starting position is a first bit, a first symbol, or a first byte.

[0036] In a possible implementation, the apparatus further includes a processing unit configured to measure a first time delay corresponding to data at each of the plurality of specific positions, to obtain a plurality of first time delays; and the target time delay includes a maximum value and / or a minimum value of the plurality of first time delays.

[0037] In a possible implementation, the sending unit is configured to report the target time delay corresponding to data at the plurality of specific positions in the data stream to a medium access control (MAC) layer.

[0038] In a third aspect, an embodiment of the present application provides a time delay reporting apparatus, including a circuit configured to perform the method in the first aspect and any one of the embodiments of the first aspect.

[0039] In a fourth aspect, an embodiment of the present application provides a physical layer (PHY) chip, configured to perform the method in the first aspect and any one of the embodiments of the first aspect.

[0040] In a fifth aspect, an embodiment of the present application provides an optical module, configured to perform the method in the first aspect and any one of the embodiments of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0042] Figure 1a A structural schematic diagram of a communication apparatus provided by an embodiment of the present application is shown in FIG. 1;

[0043] Figure 1b A structural schematic diagram of another communication apparatus provided by an embodiment of the present application is shown in FIG. 2;

[0044] Figure 1c A structural schematic diagram of another communication apparatus provided by an embodiment of the present application is shown in FIG. 3;

[0045] Figure 1d A schematic diagram of operations included in an inner code FEC provided for an embodiment of the present application;

[0046] Figure 1e A schematic diagram of convolution interleaving provided for an embodiment of the present application;

[0047] Figure 1f A schematic diagram of deconvolution deinterleaving provided for an embodiment of the present application;

[0048] Figure 1g A schematic diagram of time delay introduced by convolution interleaving and deconvolution deinterleaving provided for an embodiment of the present application;

[0049] Figure 1h A schematic diagram of 120-bit block distribution provided for an embodiment of the present application;

[0050] Figure 1i A schematic diagram of time delay introduced by 120-bit block distribution and 120-bit block multiplexing provided for an embodiment of the present application;

[0051] Figure 1j A schematic diagram of time delay introduced by inner code FEC encoding or decoding function provided for an embodiment of the present application;

[0052] Figure 1k A schematic diagram of operations included in an inner code FEC provided for an embodiment of the present application;

[0053] Figure 1L A schematic diagram of convolution interleaving provided for an embodiment of the present application;

[0054] Figure 1m A schematic diagram of time delay introduced by convolution interleaving and deconvolution deinterleaving provided for an embodiment of the present application;

[0055] Figure 1n A schematic diagram of time delay introduced by inner code FEC encoding or decoding function provided for an embodiment of the present application;

[0056] Figure 2 A schematic diagram of a flow of a time delay reporting method provided for an embodiment of the present application;

[0057] Figure 3 A schematic diagram of a structure of a first module provided for an embodiment of the present application;

[0058] Figure 4 A schematic diagram of a structure of a time delay reporting apparatus provided for an embodiment of the present application;

[0059] Figure 5 A schematic diagram of a structure of a PHY chip or optical module provided for an embodiment of the present application;

[0060] Figure 6 A structural schematic diagram of a device provided for an embodiment of the present application is shown in FIG. 1.

[0061] Figure 7 A structural schematic diagram of a device provided for an embodiment of the present application is shown in FIG. 1. DETAILED DESCRIPTION

[0062] Embodiments of the present application provide a time delay reporting method and device, which can accurately report time delay.

[0063] For the convenience of understanding, first, the application scenario of reporting time delay is introduced.

[0064] In the time synchronization scenario, the communication devices can perform time synchronization through the interaction of messages. The communication device mentioned in the embodiments of the present application can be a network device such as a switch, a router, a slicing packet network (SPN) device, or an optical transmission network (OTN) device, can be a part of the network device, for example, a single board or a line card or an interface of the network device, can be a functional module of the network device, can be a chip, can be a pluggable optical module of the network device, can be a server, a network card of the server, or a network card of other devices, and the embodiments of the present application do not make specific limitations. The communication devices can be directly connected through, for example, but not limited to, an Ethernet cable or an optical cable.

[0065] 1588 protocol is a high-precision time synchronization protocol. The 1588 protocol can provide nanosecond (ns) level time synchronization accuracy. Currently, international telecommunication union-telecommunication (ITU-T) G.8273.2 defines four levels of time synchronization accuracy requirements, which are class A, class B, class C, and class D. Among them, the time accuracy corresponding to class A is ±100 ns; the time accuracy corresponding to class B is ±70 ns; the time accuracy corresponding to class C is ±30 ns; and the time accuracy corresponding to class D is ±5 ns. Therefore, in an example, the communication devices can perform time synchronization through the interaction of 1588 messages. The 1588 message mentioned here can be understood as a message complying with the 1588 protocol.

[0066] In a specific implementation, the communication device sending the 1588 message can add a sending timestamp in the 1588 message, where the sending timestamp indicates the sending time of the 1588 message. Correspondingly, the communication device receiving the 1588 message can record a receiving timestamp of the 1588 message, where the receiving timestamp indicates the receiving time of the 1588 message. Further, the communication device receiving the 1588 message can perform time synchronization based on the sending timestamp and the receiving timestamp. Since the sending timestamp and the receiving timestamp are input parameters for time synchronization, the accuracy of the sending timestamp and the receiving timestamp directly affects the precision of time synchronization. In other words, it is particularly important to ensure the accuracy of the sending timestamp and the receiving timestamp.

[0067] Currently, the communication device records the timestamp in the following manner: the MAC layer of the communication device records the timestamp. In a specific scenario, for a communication device including an Ethernet interface, the MAC layer of the communication device can record the timestamp.

[0068] Next, the manner in which the communication device records the timestamp is introduced in combination with the structure of the communication device.

[0069] Referring to Figure 1a FIG. 1 is a structural schematic diagram of a communication device according to an embodiment of the present application, which includes the structure of a sending-end communication device and the structure of a receiving-end communication device.

[0070] As shown in Figure 1a , whether the communication device is a sending-end communication device or a receiving-end communication device, the communication device can include a MAC layer and a physical layer, and the physical layer can include a physical coding sublayer (PCS), a physical medium attachment (PMA), and a physical medium dependent (PMD). In addition, the communication device can also include an application layer, which can correspond to an upper-layer service, for example.

[0071] As a sending-end communication device, the MAC layer of the communication device can generate a MAC frame and send the MAC frame to the physical layer. For example, the MAC layer can receive data sent by an upstream device or an upper-layer service, encapsulate the data to form a MAC frame. For another example, if the MAC layer does not receive data sent by an upstream device or an upper-layer service, the MAC layer can generate a corresponding MAC frame based on an IDLE code stream.

[0072] The MAC layer of the sending end sends the MAC frame to the physical layer of the sending end. The physical layer can include a PCS, a PMA and a PMD. The MAC layer of the sending end can record a timestamp of sending the MAC frame to the physical layer as the aforementioned sending timestamp.

[0073] The PCS can process the received data stream and send the processed data to the PMA. The data stream mentioned herein can be a bit stream including a plurality of bits, and the data stream can be obtained by processing the MAC frame.

[0074] The PMA can modulate the data from the PCS into a signal supported by a channel for transmission.

[0075] The PMD is a signal transmitter for transmitting the signal modulated by the PMA through a transmission medium.

[0076] The physical layer of the receiving end receives the signal transmitted through the aforementioned transmission medium and transmits the processed signal to the MAC layer of the receiving end. As described above, the physical layer of the receiving end also includes a PMD, a PMA and a PCS.

[0077] The PMD of the receiving end first receives the signal transmitted through the transmission medium. Then, the PMA demodulates the signal. The data obtained by the PMA demodulation is transmitted to the PCS, and the PCS performs corresponding operations on the received data. The operations performed by the PCS of the receiving end are inverse operations of the operations performed by the PCS of the sending end. Further, the PCS can send the processed data stream to the MAC layer. At this point, after the MAC layer of the receiving end receives the data stream sent by the PCS, the MAC layer of the receiving end can obtain the MAC frame sent by the sending end and further process the MAC frame, for example, parse the MAC frame and send it to an upstream device or an upper layer service. When the MAC of the receiving end receives the data stream processed by the PCS, the MAC layer of the receiving end can record a timestamp of receiving the data stream as a receiving timestamp.

[0078] In order to support the high-precision time synchronization feature of 1588, the physical layer of the communication device can report the time delay of the data stream passing through the physical layer to the MAC layer, so that the MAC can compensate the recorded timestamps when recording the sending and receiving timestamps of the 1588 packet based on the time delay of the data stream passing through the physical layer, thereby making the sending and receiving timestamps of the 1588 packet recorded by the MAC layer more accurate after compensation. Specifically:

[0079] For the sending end, the MAC layer can add the aforementioned time delay of the data stream passing through the physical layer to the timestamp recorded by the MAC layer to obtain the sending timestamp. It is not difficult to understand that the sending timestamp can be considered as a timestamp of actually sending the data stream by the physical layer of the sending end.

[0080] For the receiving end, the MAC layer can subtract the aforementioned time delay of the data stream passing through the physical layer from the time stamp recorded by itself to obtain a receiving time stamp. It can be understood that the receiving time stamp can be considered as the time stamp of the actual receiving of the data stream by the physical layer of the receiving end.

[0081] As described above, the data stream transmitted in the physical layer is a bit stream including multiple bits. The physical layer cannot identify which part of the bit stream corresponds to the 1588 message. Therefore, the physical layer cannot accurately perform the delay statistics for the 1588 message. In order to solve this problem, in some scenarios, it is necessary to ensure the stability of the physical layer delay. That is, the time delay of the data stream passing through the physical layer is stabilized around a fixed value, so that the physical layer can report the fixed value to the MAC layer, and the MAC layer can compensate the time stamp based on the fixed value.

[0082] It should be noted that for any communication device, it can act as a sending end and a receiving end. In other words, Figure 1a The roles of the sending end and the receiving end shown can be interchanged, and if Figure 1a The roles of the sending end and the receiving end shown are interchanged, the flow direction of the data stream will also change accordingly, that is, the flow direction of the data stream can be from the sending end after the role interchanging to the receiving end after the role interchanging.

[0083] In some scenarios, the PCS of the physical layer of the communication device can include the FEC function. For details, please refer to Figure 1b , Figure 1b Another structure schematic diagram of a communication device provided by the embodiment of the present application. Figure 1b The structure of the communication device shown is basically the same as the structure of the communication device shown in Figure 1a The difference is that Figure 1b The PCS of the communication device shown includes the FEC function.

[0084] For the communication device shown in Figure 1b The FEC function of the sending end will perform FEC encoding, and the encoding process includes adding check bits. In addition, the sending end will also perform the data stream interleaving operation. Similarly, the PCS of the receiving end will perform FEC decoding, and the decoding process includes deleting check bits. In addition, the receiving end will also perform the deinterleaving operation on the data stream.

[0085] In one example, the FEC function of the PCS can also be referred to as the outer code FEC function. The FEC code word obtained by the sending end of the PCS performing the FEC encoding can be referred to as the FEC outer code word.

[0086] In addition, the current IEEE 802.3dj task force (B400G standard) defines that the physical layer supports a concatenated coding function. Specifically, an inner code FEC is inserted between the PMA and the PMD, and is used for FEC inner code encoding and decoding. As an example, the FEC code word obtained by the inner code FEC of the sending end after inner code FEC encoding can be referred to as an FEC inner code code word.

[0087] For a better understanding of the present application, Figure 1c For a better understanding of the present application, Figure 1c A schematic structural diagram of another communication apparatus provided by an embodiment of the present application is shown in FIG. 2. As shown in FIG. 2, the physical layer of the communication apparatus supporting concatenated coding includes a PCS, a PMA 101, a PMA 102, an inner code FEC, and a PMD. Figure 1c

[0088] The PMA 101 and the PMA 102 interact through an AUI. Specifically:

[0089] The PCS and the PMA 101 can belong to a first chip, and the PMA 102, the inner code FEC, and the PMD can belong to an optical module.

[0090] The inner code FEC is required to perform operations related to the inner code.

[0091] In an example, the operations included in the inner code FEC can be understood with reference to Figure 1d For a better understanding of the present application, Figure 1d A schematic diagram of the operations included in the inner code FEC provided by an embodiment of the present application is shown in FIG. 3.

[0092] As shown in FIG. 3: Figure 1d

[0093] For the sending end, the operations performed by the inner code FEC include a convolutional interweaver, a 120b block distribution, an inner code FEC processing, an 8:1 pulse amplitude modulation 4 (PAM4) interweaver, a 1024b pad insertion, and other processings. The inner code FEC processing can include a circular shift and an inner code FEC encoding, and the other processings can include a PAM4 encoding processing.

[0094] ​​Correspondingly, for the receiving end, the operations performed by the inner code FEC include other processing, inner code FEC synchronization and padding data removal, 1:8 PAM4 de-interleaving, inner code FEC processing, 120b block mux, and de-convolutional de-interleaver. The inner code FEC processing can include cyclic shift and inner code FEC decoding, and the other processing includes PAM4 encoding processing.

[0095] Wherein:

[0096] Convolution interleaving involves various design parameters, including delay line number, delay block length, delay block number, etc. In one example, the delay line number of convolution interleaving can be 3 lines, corresponding to line0, line1, and line2 in Figure 1e and Figure 1f The delay block length can correspond to D in Figure 1e and Figure 1f For example, D can be 40 bits, and the delay block number can correspond to Q in Figure 1e and Figure 1f The delay block numbers of the delay lines are different, for example, the delay block numbers of the 3 delay lines can be 0, D, and 2D respectively, and the number of bits delayed are 0 (no delay operation), 2*Q*D, and Q*D respectively. For another example, when the selected delay block numbers are different, the number of bits delayed by each delay line can be 0 (no delay operation), 6*D, and 12*D in Figure 1L .

[0097] As a specific example, the convolution interleaving operation of the sending end will send each 40 bits (wherein each 40 bits is referred to as a data unit) to 3 delay lines in a round-robin manner. Referring to Figure 1e , a schematic diagram of convolution interleaving provided by an embodiment of the present application is shown. Figure 1e The 3 delay lines correspond to line0, line1, and line2 shown in Figure 1e . Among them, line0 is also referred to as the first delay line, line1 is also referred to as the second delay line, and line2 is also referred to as the third delay line. As shown in Figure 1e , line0 (i.e. the first delay line) can delay each data unit (corresponding to Figure 1eD) in the leftmost and rightmost small boxes in FIG. 1A, line1 (i.e., the second delay line) can delay each data unit it receives by Q*D bits, and line2 (i.e., the third delay line) does not perform a delay operation on each data unit it receives. Wherein:

[0098] 2*Q*D and D in 2*Q*D is the number of bits included in each data unit, i.e., the value of D in 2*Q*D is 40. Q is a positive integer, in an example, the value of Q is related to the interface rate of the communication device, when the interface rate corresponds to 200GBASE-R, Q=544. When the interface rate corresponds to 400GBASE-R, Q=272, when the interface rate corresponds to 800GBASE-R, Q=136. When the interface rate corresponds to 1.6T BASE-R, Q=68.

[0099] Similarly, the deconvolutional deinterleaving operation at the receiving end also sends each 40 bits to the three delay lines in a polling manner, and the processing operations of the three delay lines at the receiving end are opposite to those of the three delay lines at the sending end. For reference, Figure 1f Figure 1f a schematic diagram of deconvolutional deinterleaving provided by an embodiment of the present application. As shown in Figure 1f line2 (i.e., the third delay line) can delay each data unit it receives by 2*Q*D bits, line1 (i.e., the second delay line) can delay each data unit it receives by Q*D bits, and line0 (i.e., the first delay line) does not perform a delay operation on each data unit it receives.

[0100] In an example, the 3 data units sent to the three delay lines in sequence can also be referred to as a convolutional interleaving sequence, in other words, when the number of delay lines is 3, a convolutional interleaving sequence can include 3 data units (i.e., 120 bits). When the number of delay lines is N, the number of data units included in the convolutional interleaving sequence is also N.

[0101] Because the three delay lines delay data units differently when performing convolutional interleaving or deconvolutional deinterleaving operations, convolutional interleaving and deconvolutional deinterleaving operations introduce time delays in the shape of a sawtooth wave. For reference, Figure 1g for understanding, Figure 1g a schematic diagram of time delays introduced by convolutional interleaving and deconvolutional deinterleaving provided by an embodiment of the present application. Figure 1g The abscissa in the diagram represents the bit stream processed by convolutional interleaving or deconvolutional deinterleaving, and the ordinate represents the time delay. Wherein, TX represents the time delay introduced by the convolutional interleaving operation at the sending end, and RX represents the time delay introduced by the deconvolutional deinterleaving operation at the receiving end. ​

[0102] In Figure 1g , the period of the sawtooth wave corresponds to the length of 3 data blocks, and the length of 3 data blocks corresponds to the time of:

[0103] 3*40 / (106.25G*2)≈0.5647ns.

[0104] The amplitude of the sawtooth wave is: 2*Q*40 / (106.25G*2), and the amplitude of the sawtooth wave is different with different Q values, and specifically:

[0105] If Q is equal to 544, the amplitude of the sawtooth wave is: 2*544*40 / (106.25G*2)≈204.8ns;

[0106] If Q is equal to 272, the amplitude of the sawtooth wave is: 2*272*40 / (106.25G*2)≈102.4ns;

[0107] If Q is equal to 136, the amplitude of the sawtooth wave is: 2*136*40 / (106.25G*2)≈51.2ns;

[0108] If Q is equal to 68, the amplitude of the sawtooth wave is: 2*68*40 / (106.25G*2)≈25.6ns.

[0109] In the above calculation formula: 106.25G*2 is the bit rate of the convolution interleaving (or inverse convolution deinterleaving) processing of the data stream, and 2 in "2*Q*40" represents that 1 symbol includes 2 bits, and 40 is the number of bits included in a data unit.

[0110] As described above for the description of the convolution interleaving performed by the sending end and the inverse convolution deinterleaving performed by the receiving end, for the sending end, the time delay introduced by the first delay line is the largest, and the time delay corresponding to the data at the starting position in a convolution interleaving sequence corresponds to the maximum time delay introduced by the convolution interleaving operation performed by the sending end. For the receiving end, the time delay introduced by the first delay line is the smallest, and the time delay corresponding to the data at the starting position in a convolution interleaving sequence corresponds to the minimum time delay introduced by the inverse convolution deinterleaving operation performed by the receiving end. Specifically, Figure 1g The positions circled by the hollow circles and the solid circles in correspond to the first delay line, and the positions correspond to the starting positions of a convolution interleaving sequence.

[0111] In the embodiments of the present application, the starting position includes but is not limited to the first bit, the first symbol, or the first byte.

[0112] In Figure 1gIn the diagram, the period of the empty circle and the period of the solid circle both correspond to 120 bits, which is the length of 3 data units, with each data unit being 40 bits long.

[0113] The sending end's 120-bit block distribution operation distributes each 120-bit data block to eight Inner FEC flows using a round-robin approach, and then sends them out uniformly. (See reference...) Figure 1h To understand, Figure 1h This is a schematic diagram illustrating a 120-bit block distribution as provided in an embodiment of this application. Figure 1h As shown, these 8 Inner FEC flows correspond to Inner FEC flow0 to Inner FEC flow7. Inner FEC flow0 can be considered the first flow among these 8 Inner FEC flows, Inner FEC flow1 can be considered the second flow, and so on, with Inner FEC flow7 being the eighth flow. Figure 1h As shown, 120-bit blocks 0 to 120-bit blocks 7 are distributed sequentially to Inner FEC flows 0 to 7, and 120-bit blocks 8 to 120-bit blocks 15 are distributed sequentially to Inner FEC flows 0 to 7. This 120-bit block distribution process results in the longest data latency for flow 0 and the shortest for flow 7. The 120-bit block multiplexing at the receiving end is the reverse process of 120-bit block distribution. The receiving end merges the data from the eight Inner FEC flows into one, resulting in the shortest data latency for flow 0 and the longest for flow 7.

[0114] Because the waiting times for data on each Inner FEC flow differ between the sending and receiving ends, the distribution and multiplexing of 120-bit blocks introduce a sawtooth-shaped delay. (See reference...) Figure 1i To understand, Figure 1i This is a schematic diagram illustrating the delay introduced by 120-bit block distribution and 120-bit block multiplexing, as provided in an embodiment of this application. Figure 1i The horizontal axis represents the bit stream after 120-bit block distribution or 120-bit block multiplexing, and the vertical axis represents the delay. TX represents the delay introduced by the 120-bit block distribution operation at the transmitting end, and RX represents the delay introduced by the 120-bit block multiplexing operation at the receiving end.

[0115] existFigure 1i In the diagram, the period of the sawtooth wave corresponds to eight 120-bit lengths, and the time corresponding to eight 120-bit lengths is:

[0116] 8*120 / (106.25G*2)≈4.5176ns.

[0117] The amplitude of the sawtooth wave is also approximately 4.5176 ns.

[0118] In one example, the eight 120-bit sequences sequentially distributed to eight inner FEC flows can also be referred to as a distribution sequence. In other words, a distribution sequence can include 8 * 120 = 960 bits. That is, the length of the distribution sequence corresponds to the product of the number of data streams after distribution and the length of the convolutional interleaving sequence. When the number of streams after distribution is N, the number of bits included in the distribution sequence is also N * 120 bits.

[0119] As described above regarding the 120-bit block distribution performed by the sending end and the 120-bit block multiplexing performed by the receiving end, for the sending end, the delay introduced by the beginning position of a distribution sequence is the largest. In other words, the delay corresponding to the data at the beginning position of a distribution sequence corresponds to the maximum delay introduced by the sending end in performing a 120-bit block distribution operation. For the receiving end, the delay introduced by the beginning position of a distribution sequence is the smallest. In other words, the delay corresponding to the data at the beginning position of a distribution sequence corresponds to the minimum delay introduced by the receiving end in performing a 120-bit block multiplexing operation. The beginning position in the distribution sequence corresponds to Inner FEC flow0. Specifically... Figure 1i The positions circled by the hollow and solid circles in the diagram correspond to the starting positions of the distribution sequence and also correspond to Inner FEC flow0.

[0120] exist Figure 1i In the diagram, the period of both the free circle and the solid circle corresponds to 960 bits.

[0121] The transmitting end's internal code FEC encoding could, for example, insert 8 parity bits for every 120 message bits. Combined with the 8:1 codeword interleaving after internal code FEC encoding, this is equivalent to inserting 64 parity bits every 960 message bits. The receiving end performs the reverse process, removing 64 parity bits every 960 message bits. In this scenario, the FEC codeword obtained after internal code FEC encoding can be a Hamming codeword.

[0122] Adding or removing parity bits during FEC encoding and decoding introduces a sawtooth-shaped delay. (See reference...) Figure 1j To understand, Figure 1jA schematic diagram of a time delay introduced by an inner code FEC encoding or decoding function provided in an embodiment of the present application. Wherein:

[0123] The sawtooth wave period is: 1024 / 113.4375G / 2≈4.5ns, and the sawtooth wave amplitude is about 64 / 113.4375G / 2≈0.28125ns.

[0124] In the formula 1024 / 113.4375G / 2:

[0125] 1024 corresponds to the number of bits contained in 8 FEC inner code codewords, and one FEC inner code codeword includes 128 bits;

[0126] 113.4375G corresponds to the baud rate of a single physical lane;

[0127] 2 indicates that in the scenario of PAM4 encoding of a data stream, one symbol includes 2 bits;

[0128] In the formula 64 / 113.4375G / 2:

[0129] 64 indicates that in 8:1 codeword interleaving, the first bit of the ninth virtual lane is located at the 65th bit in the interleaved data, and needs to wait for the transmission of the previous 64 bits to be completed before being transmitted;

[0130] 113.4375G corresponds to the baud rate of a single physical lane;

[0131] 2 indicates that one symbol includes 2 bits.

[0132] As described above for the description of Figure 1j , the period of the sawtooth wave corresponds to 8 data blocks, and one data block corresponds to one FEC inner code codeword as a Hamming code codeword. For example, one data block can include 128 bits, which correspond to one FEC inner code codeword encoded by a Hamming code. For another example, one data block can include 120 bits, which, after being encoded by a Hamming code, can obtain a 128-bit FEC inner code codeword. In Figure 1i , the positions circled by the hollow circles and the solid circles correspond to the starting positions of the aforementioned 8 data blocks. For the sending end, the time delay corresponding to the positions circled by the hollow circles corresponds to the maximum time delay introduced by the sending end performing the inner code FEC encoding operation. For the receiving end, the time delay corresponding to the positions circled by the solid circles corresponds to the minimum time delay introduced by the receiving end performing the FEC inner code decoding operation.

[0133] In Figure 1gIn some embodiments, the period of the empty circle and the period of the solid circle both correspond to 8 data blocks, in one example, one data block includes 128 bits, in another example, one data block includes 120 bits.

[0134] In some embodiments, the data blocks can be numbered sequentially, and the interval between two adjacent circles is m data blocks, which can be the difference between the numbers of the data blocks corresponding to the two adjacent circles. In this case, the period of the position corresponding to the aforementioned circles is also m. For example, the interval between the data blocks corresponding to two empty circles is 8 data blocks, which can be the difference between the numbers of the data blocks corresponding to the two empty circles. Accordingly, the period of the position marked by the empty circle is 8.

[0135] In another example, the operations included in the inner code FEC can be understood with reference to Figure 1k In another example, the operations included in the inner code FEC can be understood with reference to Figure 1k In another example, the operations included in the inner code FEC can be understood with reference to Figure 1k The operations included in the inner code FEC shown in FIG. 1 are different from the scenario shown in FIG. 2. Generally, Figure 1d The operations included in the inner code FEC shown in FIG. 1 can be applicable to a short distance communication scenario, Figure 1d The operations included in the inner code FEC shown in FIG. 1 can be applicable to a short distance communication scenario, Figure 1k The operations included in the inner code FEC shown in FIG. 1 can be applicable to a short distance communication scenario,

[0136] As shown in FIG. 1, the operations included in the inner code FEC include: Figure 1k As shown in FIG. 1, the operations included in the inner code FEC include:

[0137] For the sending end, the operations performed by the inner code FEC include: alignment lock and lane deskew, lane reorder, permutation, convolutional interleaving, BCH encoding, cyclic shift, BCH interleaving, pilot insertion, dual polarization 16-state quadrature amplitude modulation (DP-16QAM) encoding, digital to analog conversion via a digital to analog converter (DAC).

[0138] Correspondingly, for the receiving end, the operations performed by the inner code FEC include: analog to digital conversion via an analog to digital converter (ADC), DP-16QAM decoding, BCH deinterleaving, pilot removal, cyclic shift, BCH decoding, inverse convolutional deinterleaving, inverse permutation.

[0139] In some embodiments, the data blocks can be numbered sequentially, and the interval between two adjacent circles is m data blocks, which can be the difference between the numbers of the data blocks corresponding to the two adjacent circles. In this case, the period of the position corresponding to the aforementioned circles is also m. For example, the interval between the data blocks corresponding to two empty circles is 8 data blocks, which can be the difference between the numbers of the data blocks corresponding to the two empty circles. Accordingly, the period of the position marked by the empty circle is 8.

[0140] The convolution interleaving operation of the sending end sends each 40 bits (each 40 bits is called a data unit) to three delay lines in a polling manner. For details, please refer to Figure 1L , Figure 1L A schematic diagram of convolution interleaving provided by an embodiment of the present application. The three delay lines correspond to line0, line1, and line2 shown in Figure 1L . Among them, line0 is also called the first delay line, line1 is also called the second delay line, and line2 is also called the third delay line. As shown in Figure 1L , line0 (i.e., the first delay line) does not perform a delay operation on each data unit received by it, line1 (i.e., the second delay line) can delay each data unit received by it by 6*D bits, and line2 (i.e., the third delay line) can delay each data unit received by it by 12*D bits. Among them: D is the number of bits included in each data unit, that is, the value of D is 40.

[0141] Similarly, the deconvolution deinterleaving operation of the receiving end also sends each 40 bits to three delay lines in a polling manner. The processing operation of the three delay lines of the receiving end is opposite to that of the three delay lines of the sending end. Line2 (i.e., the first delay line) does not perform a delay operation on each data unit received by it, line1 (i.e., the second delay line) can delay each data unit received by it by 6*D bits, and line0 (i.e., the third delay line) can delay each data unit received by it by 12*D bits.

[0142] In an example, the 3 data units sent to the three delay lines in sequence can also be called a convolution interleaving sequence. In other words, a convolution interleaving sequence can include 3 data units (i.e., 120 bits).

[0143] Because the three delay lines have different delays on the data units when performing convolution interleaving or deconvolution deinterleaving operations, convolution interleaving and deconvolution deinterleaving operations introduce time delays in the form of sawtooth waves. For details, please refer to Figure 1m for understanding, Figure 1m A schematic diagram of the time delay introduced by convolution interleaving and deconvolution deinterleaving provided by an embodiment of the present application. Figure 1m The abscissa represents the bit stream processed by convolution interleaving or deconvolution deinterleaving, and the ordinate represents the time delay. Among them, TX represents the time delay introduced by the convolution interleaving operation of the sending end, and RX represents the time delay introduced by the deconvolution deinterleaving operation of the receiving end.

[0144] In Figure 1mIn the figure, the period of the sawtooth wave corresponds to the length of 3 data blocks, and the length of 3 data blocks corresponds to a time of:

[0145] 3*40 / (106.25G / 4)≈4.5176ns.

[0146] The amplitude of the sawtooth wave corresponds to a time of 12*D bits: 12*40 / (106.25G / 4)≈18.0706ns. Wherein:

[0147] 106.25G / 4 is the bit rate of the convolutional interleaving (or inverse convolutional deinterleaving) processing of the data stream.

[0148] As described above for the convolutional interleaving performed by the sending end and the inverse convolutional deinterleaving performed by the receiving end, for the sending end, the time delay introduced by the third delay line is the largest. For the receiving end, the time delay introduced by the third delay line is the smallest. Specifically, Figure 1m The positions circled by the hollow circles and the solid circles in the figure correspond to the third delay line.

[0149] In the figure, Figure 1m In the figure, the period of the idle circle and the period of the solid circle both correspond to 120 bits.

[0150] The inner code FEC encoding of the sending end may be, for example, 16 bits of check bits are inserted for every 110 bits of information bits. In combination with the 32:1 code word interleaving after the inner code FEC encoding, it is equivalent to 512 bits of check bits are inserted for every 3520 bits of information bits. The receiving side is a reverse process, and 512 bits of check bits are deleted for every 3520 bits of information bits.

[0151] The check bit addition and deletion in the inner code FEC encoding and decoding process will introduce a time delay in the shape of a sawtooth wave. For understanding, Figure 1n Figure 1n is a schematic diagram of the time delay introduced by an inner code FEC encoding or decoding function provided by an embodiment of the present application. Wherein:

[0152] The period of the sawtooth wave is: 126*32 / (106.25G / 4)≈151.7929ns, and the amplitude of the sawtooth wave is about 512 / (106.25G / 4)≈19.2753ns.

[0153] As described above for the convolutional interleaving performed by the sending end and the inverse convolutional deinterleaving performed by the receiving end, for the sending end, the time delay introduced by the third delay line is the largest. For the receiving end, the time delay introduced by the third delay line is the smallest. Specifically, Figure 1n ​The description can know that the period of the sawtooth wave corresponds to 32 data blocks, and one data block corresponds to one FEC inner code codeword as a BCH codeword. For example, one data block can include 126 bits, and the 126 bits correspond to one FEC inner code codeword encoded by the BCH code. For another example, one data block can include 110 bits, and after the 110 bits are encoded by the BCH code, the FEC inner code codeword of 126 bits can be obtained. In Figure 1n , the positions circled by the hollow circles and the solid circles correspond to the starting positions of the aforementioned 32 data blocks. For the sending end, the time delay corresponding to the positions circled by the hollow circles corresponds to the maximum time delay introduced by the sending end performing the inner code FEC encoding operation. For the receiving end, the time delay corresponding to the positions circled by the solid circles corresponds to the minimum time delay introduced by the receiving end performing the FEC inner code decoding operation.

[0154] In Figure 1n , the period of the idle circle and the period of the solid circle both correspond to 32 data blocks. In one example, one data block includes 126 bits, and in another example, one data block includes 110 bits.

[0155] For the aforementioned time delay introduced by the inner code FEC function, the institute of electrical and electronics engineers (IEEE) 802.3cx standard stipulates that for the sending end, the reported time delay is equivalent to the maximum time delay, and for the receiving end, the reported time delay is equivalent to the minimum time delay.

[0156] However, the IEEE 802.3cx standard does not stipulate the specific implementation manner of the sending end reporting the maximum time delay and the specific implementation manner of the receiving end reporting the minimum time delay in the scenario of supporting the cascaded encoding function at the physical layer.

[0157] In addition, the existing IEEE 802.3cx chapter 90 requires that the physical layer of the communication device reports the maximum time delay and the minimum time delay respectively when reporting the time delay. Specifically, the IEEE 802.3cx chapter 90 defines registers for reporting the maximum time delay and the minimum time delay by each layer, for example, the IEEE 802.3cx chapter 90 defines a TX maximum time delay register of PMA / PMD, a TX minimum time delay register of PMA / PMD, an RX maximum time delay register of PMA / PMD, and an RX minimum time delay register of PMA / PMD, wherein:

[0158] The TX maximum time delay register of PMA / PMD is used to report the maximum time delay of PMA / PMD when the communication device is used as a sending end.

[0159] TX minimum latency register of the PMA / PMD, used for reporting the minimum latency of the PMA / PMD when the communication device is as a sending end;

[0160] RX maximum latency register of the PMA / PMD, used for reporting the maximum latency of the PMA / PMD when the communication device is as a receiving end;

[0161] RX minimum latency register of the PMA / PMD, used for reporting the minimum latency of the PMA / PMD when the communication device is as a receiving end.

[0162] Therefore, the embodiment of the present application provides a latency reporting method, for a plurality of operations performed by the inner code FEC, the latency corresponding to each operation in the plurality of operations can be determined respectively, so as to report the latency corresponding to each operation to the MAC layer. The scheme provided by the embodiment of the present application can accurately report the latency in the case of complying with the "for the sending end, the reported latency is equivalent to the maximum latency, for the receiving end, the reported latency is equivalent to the minimum latency" specified in the EEE 802.3cx standard in the scenario of supporting the cascaded coding function in the physical layer.

[0163] Next, the latency reporting method provided by the embodiment of the present application will be introduced in combination with the drawings.

[0164] Before introducing the latency reporting method provided by the embodiment of the present application, it needs to be explained that:

[0165] For the communication device, it can include a physical layer module, which is used to implement the functions implemented by the aforementioned physical layer. For the physical layer, it can include a plurality of sub-modules, each of which is used to implement a specific physical layer function. For example, the physical layer module includes a PCS sub-module, a PMA sub-module and a PMD sub-module, the PCS sub-module is used to implement the functions implemented by the aforementioned PCS, the PMA sub-module is used to implement the functions implemented by the aforementioned PMA, and the PMD sub-module is used to implement the functions implemented by the aforementioned PMD.

[0166] In addition, the communication device can also include an optical module, which can also include corresponding sub-modules for implementing corresponding functions. For example, for the communication device with the structure as shown in the structure Figure 1c The optical module can include a PMA sub-module, an inner code FEC module and a PMD sub-module. The inner code FEC module is used to implement the inner code FEC function.

[0167] In addition, time synchronization is only one application scenario provided by the embodiments of the present application, and the scheme of the embodiments of the present application can also be applied to other scenarios. For example, in a flow detection scenario, the communication device can also determine the sending timestamp or the receiving timestamp of a packet by using the scheme of the embodiments of the present application. The application scenarios of the embodiments of the present application are not listed one by one here.

[0168] Referring to Figure 2 FIG. 1 is a flow diagram of a time delay reporting method provided by an embodiment of the present application.

[0169] Figure 2 The time delay reporting method shown in the figure can be applied to a first module, and the first module can be a module in a communication device. The communication device mentioned here can be a communication device as a sending end or a communication device as a receiving end, which is not limited in the embodiments of the present application. The structure of the first module can be as shown in Figure 3 Figure 3 FIG. 2 is a structure diagram of a first module provided by an embodiment of the present application. As shown in the figure, the first module includes a bit stream processing module, a time delay determination module, and a time delay reporting module. The bit stream processing module can include an FEC module and other modules interacting with the FEC module. The time delay determination module is configured to determine a time delay, and the time delay reporting module is configured to report the determined time delay to a second module. Figure 3

[0170] In one example, the first module can be a PHY module or an optical module. As a specific example, the structure of a communication device including the first module is as shown in Figure 1c Figure 3 For this case, the FEC module shown in the figure can be a module for implementing an inner code FEC function, and the module for implementing an inner code FEC function can also be referred to as an "inner code FEC module".

[0171] The PHY module mentioned in the embodiments of the present application can be, for example, a PHY chip for implementing a PHY function.

[0172] Figure 2 The method can include the following S101-S102.

[0173] ​​​S101: determine target time delay corresponding to data in multiple specific positions in the data stream, the multiple specific positions are spaced by a fixed length, a period of the multiple specific positions corresponds to a length of one or more convolution interleaving sequences, the specific positions correspond to delay lines with maximum or minimum time delay introduced in convolution interleaving; or, a period of the multiple specific positions corresponds to a length of one or more distribution sequences, each of the distribution sequences corresponds to 8 sub-sequences after distribution; or, a period of the multiple specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponds to one forward error correction (FEC) code word respectively, N is a positive integer, and a length of each of the data blocks is: 120 bits, or 128 bits, or 110 bits, or 126 bits.

[0174] In the embodiments of the present application, the data stream is a bit stream including multiple bits.

[0175] In one example, the first module can be Figure 1d The inner code FEC corresponds to the module shown. If the first module is a module corresponding to the sending end, the first module can perform convolution interleaving operation, 120-bit block distribution operation and inner code FEC encoding operation on data entering the first module. Correspondingly, if the first module is a module corresponding to the receiving end, the first module can perform FEC inner code decoding operation, 120-bit block multiplexing operation and inverse convolution de-interleaving operation on data entering the first module. For this case:

[0176] In one example, the target time delay can be time delay introduced by convolution interleaving performed by the sending end. At this time, a period of the multiple specific positions corresponds to a length of one or more convolution interleaving sequences. As described above, one convolution interleaving sequence can include 3 40-bit, i.e., one convolution interleaving sequence includes 120 bits. For this case, it can be known from the description of the foregoing Figure 1g that time delay corresponding to positions circled by the hollow circle in the foregoing Figure 1g is the maximum time delay corresponding to convolution interleaving operation performed by the sending end. Therefore, a period of the multiple specific positions corresponds to a period of the hollow circle in Figure 1g , for example, the period of the multiple specific positions can be an integer multiple of the period of the hollow circle in Figure 1g . In other words, the period of the multiple specific positions can correspond to a length of one or more convolution interleaving sequences. In this scenario, Figure 1gThe area circled in the hollow circle corresponds to the delay line with the largest introduced delay, while the delay line with the smallest introduced delay is the first of the three delay lines. Specifically, for the transmitting end, the first delay line delays each received data unit by 2*Q*D bits, the second delay line delays each received data unit by Q*D bits, and the third delay line does not perform any delay operation on each received data unit. For the values ​​of data unit, Q, and D, please refer to the previous section on... Figure 1g The relevant descriptions will not be repeated here.

[0177] In this scenario, the data stream can be either the data stream entering the convolutional interleaving module at the sending end, or the data stream processed by the convolutional interleaving module, whereby the convolutional interleaving module performs convolutional interleaving processing. Prior to entering the convolutional interleaving module, the data stream may have undergone external code FEC encoding processing via the PCS at the sending end. (See reference...) Figure 1c It is understood that the data stream that performs the external code FEC encoding process can be passed to the PMA101 of the PCS and then to the PMA102 of the optical module via the AUI. Furthermore, the PMA102 of the optical module passes it to the internal code FEC so that the convolutional interleaving module of the internal code FEC can further perform convolutional interleaving processing.

[0178] As before Figure 1g As can be seen from the description of the position circled by the hollow circle, the position circled by the hollow circle can correspond to the starting position of the convolutional interleaving sequence. In other words, the specific position corresponds to the starting position of one or more convolutional interleaving sequences.

[0179] In another example, the target latency can be the latency introduced by the receiving end performing deconvolution deinterleaving. In this case, the periods at the multiple specific positions correspond to the lengths of one or more convolutional interleaving sequences. As described earlier, a convolutional interleaving sequence can include three 40-bit sequences, i.e., a convolutional interleaving sequence includes 120 bits. For this case, refer to the previous section on... Figure 1g As can be seen from the description above, the aforementioned Figure 1g The time delay corresponding to the position circled in the solid circle is the minimum time delay required for the receiving end to perform the deconvolution deinterleaving operation. Therefore, the period of the multiple specific positions can correspond to... Figure 1g The period of the solid circle, for example, the period of the multiple specific positions can be... Figure 1g The period of the solid circle is an integer multiple of its period. In other words, the periods at the multiple specific positions can correspond to the lengths of one or more convolutional interleaving sequences. In this scenario, Figure 1gThe position circled by the solid circle corresponds to the delay line with the minimum introduced delay, which is the first delay line among the three delay lines. Among them, the first delay line corresponding to the receiving end does not perform a delay operation on each data unit received by it, the second delay line corresponding to the receiving end can delay each data unit received by it by Q*D bits. The third delay line corresponding to the receiving end can delay each data unit received by it by 2*Q*D bits. For the values of Q and D, please refer to the previous description of the related part of Figure 1g , which will not be repeated here.

[0180] In this scenario, as an example, the data stream can be a data stream sent by the sending end to the receiving end, which can be a data stream entering the convolution interleaving module of the receiving end. As another example, the data stream can also be a data stream processed by the convolution interleaving module of the receiving end, wherein the convolution interleaving module of the receiving end is used to perform inverse convolution deinterleaving processing.

[0181] As previously described in the description of the position circled by the solid circle in Figure 1g , the position circled by the solid circle can correspond to the starting position of the convolution interleaving sequence, in other words, the specific position corresponds to the starting position of one or more convolution interleaving sequences.

[0182] In the embodiments of the present application, the first module is a module corresponding to the sending end, which can be understood as a module in the communication device of the sending end; the first module is a module corresponding to the receiving end, which can be understood as a module in the communication device of the receiving end. Among them, the first module corresponding to the receiving end can also be understood as the first module corresponding to the receiving end, and the first module corresponding to the sending end can also be understood as the first module corresponding to the sending end.

[0183] In one example, the target delay can be the delay introduced by the sending end performing 120-bit block distribution. At this time, the period of the plurality of specific positions corresponds to the length of one or more distribution sequences. The sending end can perform 1:8 distribution processing on the distribution sequence to distribute a plurality of data blocks including 120 bits to 8 inner FEC flows. As previously described, one distribution sequence can include 8 120-bit, that is, one distribution sequence includes 960 bits. For this case, please refer to the previous description of Figure 1i , which will not be repeated here. Figure 1i The delay corresponding to the position circled by the hollow circle in the foregoing Figure 1i is the maximum delay corresponding to the 120-bit block distribution operation of the sending end. Therefore, the period of the plurality of specific positions corresponds to the period of the hollow circle in Figure 1iinteger multiple of the period of the hollow circles. In other words, the period of the plurality of specific positions can correspond to the length of one or more distribution sequences. In this scenario, Figure 1i the position circled by the solid circle corresponds to the starting position of the distribution sequence and the first stream (i.e., the first inner FEC flow) corresponding to the 1 :8 distribution process.

[0184] In yet another example, the target latency can be the latency introduced by the receiving end performing 120-bit block multiplexing. In this case, the period of the plurality of specific positions corresponds to the length of one or more distribution sequences. The receiving end can perform 8: 1 multiplexing on the distribution sequence to combine the 120-bit data blocks on the 8 inner FEC flows into one data stream. For this case, it is known from the foregoing description of Figure 1i that the latency corresponding to the position circled by the hollow circle is the maximum latency corresponding to the receiving end performing 120-bit block multiplexing. Therefore, the period of the plurality of specific positions corresponds to the period of the hollow circles in Figure 1i for example, the period of the plurality of specific positions can be an integer multiple of the period of the hollow circles in Figure 1i for example, the period of the plurality of specific positions can be an integer multiple of the period of the hollow circles in Figure 1i In other words, the period of the plurality of specific positions can correspond to the length of one or more distribution sequences. In this scenario, Figure 1i the position circled by the solid circle corresponds to the starting position of the distribution sequence and the first stream (i.e., the first inner FEC flow) corresponding to the 8: 1 multiplexing process.

[0185] In one example, the target latency can be the latency introduced by the sending end performing inner code FEC encoding. In this case, the period of the plurality of specific positions corresponds to an integer multiple of N data blocks. For this case, it is known from the foregoing description of Figure 1j that the latency corresponding to the position circled by the hollow circle is the maximum latency corresponding to the sending end performing inner code FEC encoding. Therefore, the period of the plurality of specific positions corresponds to the period of the hollow circles in Figure 1j for example, the period of the plurality of specific positions can be an integer multiple of the period of the hollow circles in Figure 1j for example, the period of the plurality of specific positions can be an integer multiple of the period of the hollow circles in Figure 1j As known from the foregoing description of Figure 1j , the period of the hollow circles is 8 data blocks, therefore, in one example, the foregoing N is equal to 8. In other words, the period of the plurality of specific positions can correspond to an integer multiple of 8 data blocks. In this scenario, Figure 1jThe positions circled in the hollow circle correspond to the starting positions of integer multiples of the aforementioned 8 data blocks. Each of these 8 data blocks can include either 128 bits or 120 bits, where the 128 bits are the FEC codeword obtained after Hamming encoding, and the 120 bits are the data before Hamming encoding.

[0186] In this scenario, as an example, the data stream can be the data stream entering the internal code FEC encoding module at the sending end, where the internal code FEC encoding module is used to perform internal code FEC encoding. Prior to entering the internal code FEC encoding module, the data stream may have undergone external code FEC encoding processing via the PCS at the sending end. (See reference...) Figure 1c Understanding this, the data stream undergoing external code FEC encoding can be passed to the PMA101 of the PCS, and then to the PMA102 of the optical module via the AUI. Further, the PMA102 of the optical module passes it to the internal code FEC, so that the convolutional interleaving module of the internal code FEC can further perform convolutional interleaving processing. As another example, the data stream can also be a data stream processed by the internal code FEC encoding module; in other words, the data stream can include FEC internal code codewords that have undergone external code FEC encoding and then internal code FEC encoding.

[0187] In yet another example, the target latency can be the latency introduced by the receiver performing internal code FEC decoding. In this case, the periods at the multiple specific locations correspond to integer multiples of N data blocks. For this situation, refer to the previous section on... Figure 1j As can be seen from the description above, the aforementioned Figure 1j The time delay corresponding to the position circled in the solid circle is the minimum time delay required for the receiver to perform the internal code FEC decoding operation. Therefore, the period of the plurality of specific positions corresponds to... Figure 1j The period of the solid circle, for example, the period of the multiple specific positions can be... Figure 1j An integer multiple of the period of the solid circle. As before for... Figure 1j As described, the period of the solid circle is 8 data blocks; therefore, in one example, N equals 8. In other words, the period at the multiple specific positions can correspond to an integer multiple of 8 data blocks. In this scenario, Figure 1j The positions circled in the solid circle correspond to the starting positions of integer multiples of the aforementioned 8 data blocks. Each of these 8 data blocks can include either 128 bits or 120 bits, where the 128 bits are the FEC codeword obtained after Hamming code encoding, and the 120 bits are the data before Hamming code encoding.

[0188] In this scenario, as an example, the data stream can be a data stream entering an inner code FEC decoding module of a receiving end, where the inner code FEC decoding module is configured to perform inner code FEC decoding. As another example, the data stream can also be a data stream obtained by performing inner code FEC decoding via the inner code FEC decoding module.

[0189] In yet another example, the first module can be Figure 1k The inner code FEC corresponding module is shown. If the first module is a module corresponding to a sending end, the first module can perform convolution interleaving operation and inner code FEC encoding operation on data entering the first module. Correspondingly, if the first module is a module corresponding to a receiving end, the first module can perform FEC inner code decoding operation and inverse convolution deinterleaving operation on data entering the first module. For this case:

[0190] In one example, the target delay can be a delay introduced by the sending end performing convolution interleaving. At this time, the period of the plurality of specific positions corresponds to the length of one or more convolution interleaving sequences. As previously described, one convolution interleaving sequence can include 3*40 bits, i.e., one convolution interleaving sequence includes 120 bits. For this case, referring to the description of the foregoing Figure 1m , the delay corresponding to the positions circled by the hollow circle in the foregoing Figure 1m is the maximum delay corresponding to the sending end performing convolution interleaving operation. Therefore, the period of the plurality of specific positions corresponds to the period of the hollow circle in the foregoing Figure 1m , for example, the period of the plurality of specific positions can be an integer multiple of the period of the hollow circle in the foregoing Figure 1m . In other words, the period of the plurality of specific positions can correspond to the length of one or more convolution interleaving sequences. In this scenario, the positions circled by the hollow circle in the foregoing Figure 1m correspond to the delay line introducing the maximum delay, which is the third delay line among the three delay lines. Among them, for the sending end, the first delay line corresponding thereto can not perform delay operation on each data unit received by it, the second delay line among the three delay lines corresponding thereto can delay each data unit received by it by 6*D bits, and the third delay line among the three delay lines corresponding thereto can delay each data unit received by it by 12*D bits. For the value of D, refer to the related description of the foregoing Figure 1m , which is not repeated here.

[0191] In this scenario, the data stream can be either the data stream entering the convolutional interleaving module at the sending end, or the data stream processed by the convolutional interleaving module, whereby the convolutional interleaving module performs convolutional interleaving processing. Prior to entering the convolutional interleaving module, the data stream may have undergone external code FEC encoding processing via the PCS at the sending end. (See reference...) Figure 1c It is understood that the data stream that performs the external code FEC encoding process can be passed to the PMA101 of the PCS and then to the PMA102 of the optical module via the AUI. Furthermore, the PMA102 of the optical module passes it to the internal code FEC so that the convolutional interleaving module of the internal code FEC can further perform convolutional interleaving processing.

[0192] In another example, the target latency can be the latency introduced by the receiving end performing deconvolution deinterleaving. In this case, the periods at the multiple specific positions correspond to the lengths of one or more convolutional interleaving sequences. As described earlier, a convolutional interleaving sequence can include three 40-bit sequences, i.e., a convolutional interleaving sequence includes 120 bits. For this case, refer to the previous section on... Figure 1m As can be seen from the description above, the aforementioned Figure 1m The time delay corresponding to the position circled in the solid circle is the minimum time delay required for the receiving end to perform the deconvolution deinterleaving operation. Therefore, the period of the multiple specific positions can correspond to... Figure 1m The period of the solid circle, for example, the period of the multiple specific positions can be... Figure 1m The period of the solid circle is an integer multiple of its period. In other words, the periods at the multiple specific positions can correspond to the lengths of one or more convolutional interleaving sequences. In this scenario, Figure 1m The area circled in the solid circle corresponds to the delay line with the minimum introduced delay, which is the third of the three delay lines. Specifically, the third delay line at the receiving end does not perform a delay operation on each received data unit. The second delay line at the receiving end delays each received data unit by 6*D bits. The first delay line at the receiving end delays each received data unit by 12*D bits. For the value of D, please refer to the previous section on... Figure 1m The relevant descriptions will not be repeated here.

[0193] In this scenario, as an example, the data stream can be a data stream sent from the sending end to the receiving end, and this data stream can be a data stream entering the convolutional interleaving module of the receiving end. As another example, the data stream can also be a data stream processed by the convolutional interleaving module of the receiving end, wherein the convolutional interleaving module of the receiving end is used to perform deconvolutional deinterleaving processing.

[0194] In one example, the target latency can be the latency introduced by the inner FEC encoding performed by the transmitting end. In this case, the period of the plurality of specific positions corresponds to an integer multiple of N data blocks. For this case, it can be appreciated from the foregoing description of Figure 1n that the latency corresponding to the positions circled by the hollow circle in Figure 1n is the maximum latency corresponding to the inner FEC encoding operation performed by the transmitting end. Therefore, the period of the plurality of specific positions corresponds to the period of the hollow circle in Figure 1n , e.g., the period of the plurality of specific positions can be an integer multiple of the period of the hollow circle in Figure 1n . As can be appreciated from the foregoing description of Figure 1n , the period of the hollow circle is 32 data blocks, therefore, in one example, the foregoing N is equal to 32. In other words, the period of the plurality of specific positions can correspond to an integer multiple of 32 data blocks. In this scenario, the positions circled by the hollow circle in Figure 1n correspond to the starting positions of the integer multiples of the foregoing 32 data blocks. Each of the 32 data blocks can include 126 bits, which is the FEC inner code word after BCH encoding, or 110 bits, which is the data before BCH encoding.

[0195] In this scenario, as an example, the data stream can be the data stream entering the inner FEC encoding module of the transmitting end, where the inner FEC encoding module is configured to perform inner FEC encoding. The data stream can be subjected to outer FEC encoding by the PCS of the transmitting end before entering the inner FEC encoding module. As can be appreciated from Figure 1c , the data stream subjected to outer FEC encoding can be passed to the PMA 101 of the PCS and to the PMA 102 of the optical module via the AUI, and further passed from the PMA 102 of the optical module to the inner FEC for further convolution interleaving processing by the convolution interleaving module of the inner FEC. As another example, the data stream can also be the data stream after being processed by the inner FEC encoding module, in other words, the data stream can include the FEC inner code word subjected to outer FEC encoding and then inner FEC encoding.

[0196] In yet another example, the target latency can be the latency introduced by the inner FEC decoding performed by the receiving end. In this case, the period of the plurality of specific positions corresponds to an integer multiple of N data blocks. For this case, it can be appreciated from the foregoing description of Figure 1n that the latency corresponding to the positions circled by the hollow circle in Figure 1nThe time delay corresponding to the position circled in the solid circle is the minimum time delay required for the receiver to perform the internal code FEC decoding operation. Therefore, the period of the plurality of specific positions corresponds to... Figure 1n The period of the solid circle, for example, the period of the multiple specific positions can be... Figure 1n An integer multiple of the period of the solid circle. As before for... Figure 1n As described, the period of the solid circle is 32 data blocks; therefore, in one example, N equals 32. In other words, the period at the multiple specific positions can correspond to an integer multiple of 32 data blocks. In this scenario, Figure 1n The positions circled in the solid circle correspond to the starting positions of integer multiples of the aforementioned 32 data blocks. Each of these 32 data blocks can include either 126 bits or 110 bits, where the 126 bits are the FEC codeword obtained after BCH encoding, and the 110 bits are the data before BCH encoding.

[0197] In this scenario, as an example, the data stream can be a data stream entering the internal code FEC decoding module at the receiving end, wherein the internal code FEC decoding module is used to perform internal code FEC decoding. As yet another example, the data stream can also be a data stream obtained by performing internal code FEC decoding via the internal code FEC decoding module.

[0198] In one example, the data from the aforementioned multiple specific locations can correspond to a first time delay for each specific location. Therefore, the data from the aforementioned multiple specific locations can correspond to multiple first time delays.

[0199] In the embodiments of this application, the plurality of first delays may be the same, or may not be completely the same or completely different, and the embodiments of this application do not make specific limitations.

[0200] As mentioned earlier, the existing IEEE 802.3cx Chapter 90 defines corresponding maximum and minimum delay registers for each layer of the physical layer. Therefore, to be compatible with the current IEEE 802.3cx Chapter 90 mechanism for reporting physical layer delays, the maximum and / or minimum value among the plurality of first delays can be reported. In other words, the aforementioned target delay can be the maximum and / or minimum value among the plurality of first delays.

[0201] As mentioned above, the plurality of first delays may be the same, not exactly the same, or completely different. When the plurality of first delays are the same, the maximum value and the minimum value are the same. When the plurality of first delays are not exactly the same or completely different, the maximum value is less than the minimum value.

[0202] In one example, the first module can measure the first time delay corresponding to the data of each specific position in the data of the plurality of specific positions, to obtain a plurality of first time delays. For example:

[0203] The embodiment of the present application does not limit the specific implementation of determining the first time delay.

[0204] In one example, the first module can record the time delay of the data of the specific position in the data stream, to determine the first time delay. In another example, the first module can determine the time delay of the data of a plurality of positions in the data stream passing through the first module, to obtain a plurality of time delays corresponding to the plurality of positions. The plurality of positions mentioned herein can include the specific position, for example, the plurality of positions can be each position in the target data. Correspondingly, the first time delay can be determined from the plurality of time delays. That is, the time delay corresponding to the specific position is extracted from the plurality of time delays, to obtain the first time delay. For example, for the data stream, the first module can determine the time delay of each bit of data in the data stream passing through the first module, and extract the time delay of the data of the specific position (for example, the starting position of each convolution interleaving sequence) in the data stream passing through the first module, to obtain the first time delay.

[0205] The embodiment of the present application does not limit the determination method of the time delay of the data of any position in the data stream passing through the first module, and two possible implementation methods are introduced below.

[0206] In one implementation method, the first module can record the first time when the data of the position is received by itself, and record the second time when the data of the position is sent out by itself, and determine the time delay of the data of the position passing through the first module as the difference between the second time and the first time.

[0207] In another example, the first module can cache the data of the position after receiving the data of the position. Correspondingly, the first module can send out the cached data in sequence according to the data already cached in the cache. Therefore, the position of the data of the position in the cache can represent the time length that the data of the position needs to wait in the cache, and the time length can represent the time delay of the data of the position passing through the first module. Therefore, the first module can determine the time delay of the data of the position passing through the first module according to the position of the data of the position in the cache.

[0208] S102: reporting the target time delay corresponding to the data of a plurality of specific positions in the data stream.

[0209] In the embodiments of the present application, the first module can report the target time delay to the second module. In one example, the second module can be a MAC layer module of the communication device, so that the MAC layer module can compensate the time stamp recorded by itself based on the target time delay, so that the time stamp after compensation is more accurate.

[0210] In one example, the first module can report the target time delay to the second module, or report the target time delay and the time delay of other operations in the inner code FEC after addition, without specific limitation of the embodiments of the present application.

[0211] The first module can report the target time delay to the second module by using corresponding registers. In the scenario where the target time delay includes the maximum value and / or the minimum value, in one example, the first module can report the maximum value and / or the minimum value to the second module by using corresponding registers, and the following introduces several specific implementation manners of the first module reporting the maximum value and / or the minimum value to the second module by using corresponding registers.

[0212] In one example, if the first module corresponds to a sending end, the first module can report the target time delay to the second module by using a TX maximum time delay register of the inner code FEC.

[0213] As a specific example, a new register can be defined to report the maximum value and / or the minimum value to the second module. For example, a TX maximum time delay register and / or a TX minimum time delay register of the inner code FEC is defined, the TX maximum time delay register is used to report the maximum value, and the TX minimum time delay register is used to report the minimum value. In other words, the first module can report the maximum value to the second module by using the TX maximum time delay register of the inner code FEC, and / or report the minimum value to the second module by using the TX minimum time delay register of the inner code FEC.

[0214] As another specific example, the first module can report the maximum value to the second module by using a TX maximum time delay register of the PMA / PMD. Similarly, the first module can report the minimum value to the second module by using a TX minimum time delay register of the PMA / PMD. In this way, the existing register can be used to implement the reporting of the target time delay.

[0215] In one example, if the first module corresponds to a receiving end, the first module can report the target time delay to the second module by using a RX maximum time delay register of the inner code FEC.

[0216] As another specific example, a new register can be defined to report the maximum value and / or the minimum value to the second module. For example, a RX maximum delay register of inner code FEC and / or a RX minimum delay register of inner code FEC is defined to report the maximum value and / or the minimum value. In other words, the first module can report the maximum value to the second module by using the RX maximum delay register of inner code FEC, and / or report the minimum value to the second module by using the RX minimum delay register of inner code FEC.

[0217] As another specific example, the first module can report the maximum value to the second module by using a RX maximum delay register of PMA / PMD. Similarly, the first module can report the minimum value to the second module by using a RX minimum delay register of PMA / PMD.

[0218] From the above description, it can be known that, by using the scheme of the embodiments of the present application, for the delay part of dynamic periodicity (i.e. the delay part in sawtooth wave shape), the first module can accurately report the delay to the second module by following the rule that, for the sending end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay.

[0219] The above describes the delay reporting method provided by the embodiments of the present application. Next, the scheme provided by the embodiments of the present application is described in combination with a specific scenario.

[0220] In this scenario, the structure of the communication device can adopt the structure shown in Figure 1d The first module can be an optical module of the communication device, which includes a PMA 102, an inner code FEC, and a PMD.

[0221] Embodiment 1

[0222] For the communication device as the sending end, the optical module thereof can perform the following operations:

[0223] S1: records the delay of the i th convolution interleaving sequence in the data stream sent by it after the convolution interleaving operation, to obtain DelayTX1 (1, i), wherein:

[0224] 1 represents the starting position, which can be the 1st bit, the 1st byte, or the 1st symbol.

[0225] The value of i can be 1, 2, 3, … s.

[0226] S2: determines the maximum value DelayTX_max1 of DelayTX1 (1, i) and the minimum value DelayTX_min1 of DelayTX1 (1, i).

[0227] S3: report DelayTX_max1 and DelayTX_min1 to the MAC layer module, or report (DelayTX_max1+sum11) and (DelayTX_min1+sum12) to the MAC layer module.

[0228] In one example, DelayTX_max1 or (DelayTX_max1+sum11) can be reported to the MAC layer module through the TX maximum delay register of inner code FEC, and DelayTX_min1 or (DelayTX_min1+sum12) can be reported to the MAC layer module through the TX minimum delay register of inner code FEC.

[0229] In another example, DelayTX_max1 or (DelayTX_max1+sum11) can be reported to the MAC layer module through the TX maximum delay register of PMA / PMD, and DelayTX_min1 or (DelayTX_min1+sum12) can be reported to the MAC layer module through the TX minimum delay register of PMA / PMD.

[0230] Wherein, sum11 can be the maximum value of the sum of the time delays of the data stream via other operations, and sum12 can be the minimum value of the sum of the time delays of the data stream via other operations. sum11 and sum12 can be the same, or sum11 can be greater than sum12. The other operations mentioned herein can be, for example, 120-bit block distribution operation in inner code FEC, inner code FEC encoding operation, etc.

[0231] For the communication device as the receiving end, the optical module thereof can perform the following operations:

[0232] S1': record the time delay of the i-th convolution interleaving sequence in the data stream sent by the communication device via convolution interleaving operation, to obtain DelayRX1(1,i), wherein:

[0233] 1 represents the starting position, which can be the 1st bit, the 1st byte or the 1st symbol.

[0234] The value of i can be 1, 2, 3, …s.

[0235] S2': determine the maximum value DelayRX_max1 of DelayRX1(1,i) and the minimum value DelayRX_min1 of DelayRX1(1,i).

[0236] S3': report DelayRX_max1 and DelayRX_min1 to the MAC layer module, or report (DelayRX_max1 + sum11') and (DelayRX_min1 + sum12') to the MAC layer module.

[0237] In one example, DelayRX_max1 or (DelayRX_max1 + sum11') can be reported to the MAC layer module through the RX maximum delay register of the inner code FEC, and DelayRX_min1 or (DelayRX_min1 + sum12') can be reported to the MAC layer module through the RX minimum delay register of the inner code FEC.

[0238] In another example, DelayRX_max1 or (DelayRX_max1 + sum11') can be reported to the MAC layer module through the RX maximum delay register of the PMA / PMD, and DelayRX_min1 or (DelayRX_min1 + sum12') can be reported to the MAC layer module through the RX minimum delay register of the PMA / PMD.

[0239] Wherein, sum11' can be the maximum value of the sum of the time delays of the data stream via other operations, and sum12' can be the minimum value of the sum of the time delays of the data stream via other operations. sum11' and sum12' can be the same, or sum11' can be greater than sum12'. The other operations mentioned herein can be, for example, 120-bit block multiplexing operation in the inner code FEC, FEC inner code decoding operation, etc.

[0240] Embodiment 2:

[0241] For the communication device as a sending end, the optical module thereof can perform the following operations:

[0242] S4: record the time delay of the i-th distribution sequence in the data stream sent by the communication device via the 120-bit block distribution operation, to obtain DelayTX2(1, j), wherein:

[0243] 1 represents the starting position, which can be the 1st bit, the 1st byte or the 1st symbol.

[0244] The value of i can be 1, 2, 3, … s.

[0245] S5: determine the maximum value DelayTX_max2 of DelayTX2(1, j) and the minimum value DelayTX_min2 of DelayTX2(1, j).

[0246] S6: report DelayTX_max2 and DelayTX_min2 to the MAC layer module, or report (DelayTX_max2+sum21) and (DelayTX_min2+sum22) to the MAC layer module.

[0247] In one example, DelayTX_max2 or (DelayTX_max2+sum21) can be reported to the MAC layer module through the TX maximum delay register of the inner code FEC, and DelayTX_min2 or (DelayTX_min2+sum22) can be reported to the MAC layer module through the TX minimum delay register of the inner code FEC.

[0248] In another example, DelayTX_max2 or (DelayTX_max2+sum21) can be reported to the MAC layer module through the TX maximum delay register of the PMA / PMD, and DelayTX_min2 or (DelayTX_min2+sum22) can be reported to the MAC layer module through the TX minimum delay register of the PMA / PMD.

[0249] Wherein, sum21 can be the maximum value of the sum of the time delays of the data stream via other operations, and sum22 can be the minimum value of the sum of the time delays of the data stream via other operations. sum21 and sum22 can be the same, or sum21 can be greater than sum22. The other operations mentioned herein can be, for example, convolution interleaving operation in inner code FEC, inner code FEC encoding operation, etc.

[0250] For the communication device as the receiving end, the optical module thereof can perform the following operations:

[0251] S4': record the time delay of the i-th distribution sequence of the data stream sent by the communication device via the 120-bit block multiplexing operation, to obtain DelayRX2(1,j), wherein:

[0252] 1 represents the starting position, which can be the 1st bit, the 1st byte or the 1st symbol.

[0253] The value of i can be 1, 2, 3, … s.

[0254] S5': determine the maximum value DelayRX_max2 of DelayRX2(1,j) and the minimum value DelayRX_min2 of DelayRX2(1,j).

[0255] S6': report DelayRX_max2 and DelayRX_min2 to the MAC layer module, or report (DelayRX_max2+sum21') and (DelayRX_min2+sum22') to the MAC layer module.

[0256] In one example, DelayRX_max2 or (DelayRX_max2+sum21') can be reported to the MAC layer module through the RX maximum delay register of the inner code FEC, and DelayRX_min2 or (DelayRX_min2+sum22') can be reported to the MAC layer module through the RX minimum delay register of the inner code FEC.

[0257] In another example, DelayRX_max2 or (DelayRX_max2+sum21') can be reported to the MAC layer module through the RX maximum delay register of the PMA / PMD, and DelayRX_min2 or (DelayRX_min2+sum22') can be reported to the MAC layer module through the RX minimum delay register of the PMA / PMD.

[0258] Wherein, sum21' can be the maximum value of the sum of the time delays of the data stream via other operations, and sum22' can be the minimum value of the sum of the time delays of the data stream via other operations, sum21' can be equal to sum22', or sum21' can be greater than sum22'. The other operations mentioned herein can be, for example, the de-interleaving operation of the inverse convolution in the inner code FEC, the FEC inner code decoding operation, etc.

[0259] Embodiment 3:

[0260] For the communication device as the sending end, the optical module thereof can perform the following operations:

[0261] S7: record the time delay of the starting position of the kth data block in the data stream sent by it via the inner code FEC encoding, to obtain DelayTX3(1, k), wherein:

[0262] 1 represents the starting position, which can be the 1st bit, the 1st byte, or the 1st symbol.

[0263] The value of k can be 8, 16, 32, …8*s, in which case a data block includes 128 bits or 120 bits; or the value of k can be 32, 64, 96, …32*s, in which case a data block includes 126 bits or 110 bits.

[0264] S8: determine the maximum value DelayTX_max3 of DelayTX3(l, k) and the minimum value DelayTX_min3 of DelayTX3(l, k).

[0265] S9: report DelayTX_max3 and DelayTX_min3 to the MAC layer module, or report (DelayTX_max3 + sum31) and (DelayTX_min3 + sum32) to the MAC layer module.

[0266] In one example, DelayTX_max3 or (DelayTX_max3 + sum31) can be reported to the MAC layer module through the TX maximum delay register of inner code FEC, and DelayTX_min3 or (DelayTX_min3 + sum32) can be reported to the MAC layer module through the TX minimum delay register of inner code FEC.

[0267] In another example, DelayTX_max3 or (DelayTX_max3 + sum31) can be reported to the MAC layer module through the TX maximum delay register of PMA / PMD, and DelayTX_min3 or (DelayTX_min3 + sum32) can be reported to the MAC layer module through the TX minimum delay register of PMA / PMD.

[0268] Wherein, sum31 can be the maximum value of the sum of the time delays of the data stream via other operations, and sum32 can be the minimum value of the sum of the time delays of the data stream via other operations, sum31 can be equal to sum32, or sum31 can be greater than sum32. The other operations mentioned herein can be, for example, convolution interleaving operation in inner code FEC, or convolution interleaving operation and 120-bit block distribution operation.

[0269] For the communication device as a receiving end, the optical module thereof can perform the following operations:

[0270] S7': record the time delay of the starting position of the kth data block in the data stream sent by the communication device via inner code FEC encoding, to obtain DelayRX3(l, k), wherein:

[0271] 1 represents the starting position, which can be the 1st bit, the 1st byte or the 1st symbol.

[0272] The value of k can be 8, 16, 32, …8*s, in which case one data block includes 128 bits or 120 bits; or the value of k can be 32, 64, 96, …32*s, in which case one data block includes 126 bits or 110 bits.

[0273] S8': determining the maximum value DelayRX_max3 of DelayRX3(1, k) and the minimum value DelayRX_min3 of DelayRX(1, k).

[0274] S9': reporting DelayRX_max3 and DelayRX_min3 to the MAC layer module, or reporting (DelayRX_max3+sum31') and (DelayRX_min3+sum32') to the MAC layer module.

[0275] In one example, DelayRX_max3 or (DelayRX_max3+sum31') can be reported to the MAC layer module through the RX maximum delay register of inner code FEC, and DelayRX_min3 or (DelayRX_min3+sum32') can be reported to the MAC layer module through the RX minimum delay register of inner code FEC.

[0276] In another example, DelayRX_max3 or (DelayRX_max3+sum31') can be reported to the MAC layer module through the RX maximum delay register of PMA / PMD, and DelayRX_min3 or (DelayRX_min3+sum32') can be reported to the MAC layer module through the RX minimum delay register of PMA / PMD.

[0277] Wherein, sum31' can be the maximum value of the sum of the time delays of the data stream via other operations, sum32' can be the minimum value of the sum of the time delays of the data stream via other operations, sum31' can be equal to sum32', and sum31' can also be greater than sum32'. The other operations mentioned herein can be, for example, the de-interleaving operation of inverse convolution in inner code FEC, or the de-interleaving operation of inverse convolution and the 120-bit block multiplexing operation.

[0278] Based on the time delay reporting method provided in the above embodiments, the embodiments of the present application further provide a corresponding time delay reporting device, which can be used to execute the time delay reporting method provided in the above embodiments.

[0279] In one specific example, the time delay reporting device can be as shown in Figure 4 . Figure 4 A structure diagram of a time delay reporting device provided in the embodiments of the present application.

[0280] As shown in Figure 4 , the time delay reporting device 400 includes a sending unit 401.

[0281] The sending unit 401 is configured to report target time delays corresponding to data at a plurality of specific positions in a data stream, and intervals between the plurality of specific positions are of a fixed length; wherein: a period of the plurality of specific positions corresponds to a length of one or more convolution interleaving sequences, the specific positions correspond to delay lines with maximum or minimum introduced time delays in convolution interleaving; or, a period of the plurality of specific positions corresponds to a length of one or more distribution sequences, each of the distribution sequences corresponds to eight sub-sequences after distribution; or, a period of the plurality of specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponds to one forward error correction (FEC) code word respectively, N is a positive integer, and a length of each of the data blocks is: 120 bits, or 128 bits, or 110 bits, or 126 bits.

[0282] In a possible implementation, the delay line with the maximum or minimum introduced time delay is a first delay line of three delay lines in convolution interleaving.

[0283] In a possible implementation, the first delay line is configured to delay each data unit received thereby by 2*Q*D bits, a second delay line of the three delay lines is configured to delay each data unit received thereby by Q*D bits, and a third delay line of the three delay lines is configured not to perform a delay operation on each data unit received thereby, D is a number of bits included in each data unit, and Q is a positive integer; or, the third delay line is configured to delay each data unit received thereby by 2*Q*D bits, the second delay line is configured to delay each data unit received thereby by Q*D bits, and the first delay line is configured not to perform a delay operation on each data unit received thereby.

[0284] In a possible implementation, Q is 544, or 272, or 136, or 68.

[0285] In a possible implementation, the delay line with the maximum or minimum introduced time delay is a third delay line of three delay lines in convolution interleaving.

[0286] In a possible implementation, the first delay line is configured not to perform a delay operation on each data unit received thereby, a second delay line of the three delay lines is configured to delay each data unit received thereby by 6*D bits, and a third delay line of the three delay lines is configured to delay each data unit received thereby by 12*D bits, D is a number of bits included in each data unit; or, the third delay line is configured not to perform a delay operation on each data unit received thereby, the second delay line is configured to delay each data unit received thereby by 6*D bits, and the first delay line is configured to delay each data unit received thereby by 12*D bits.

[0287] In a possible implementation, each of the convolution interleaving sequences includes 3 data units, and each of the 3 data units includes 40 bits.

[0288] In a possible implementation, each of the distribution sequences includes 8 data blocks, each of the distribution sequences is used to perform 1:8 distribution processing, or a sequence corresponding to the specific position is a first stream in 8 streams corresponding to 1:8 distribution processing or 8:1 multiplexing processing.

[0289] In a possible implementation, the N is 8 or 32; or the FEC code word is an FEC inner code word after outer code FEC encoding processing and inner code FEC encoding; or, the FEC inner code word is a Hamming code word or a BCH code word; or, the data stream is a data stream received through an attachment unit interface (AUI); or, the data stream is a data stream obtained by performing inner code FEC decoding.

[0290] In a possible implementation, the specific position corresponds to a starting position of the one or more convolution interleaving sequences; or, the specific position corresponds to a starting position of the one or more distribution sequences; or, the specific position corresponds to a starting position of an integer multiple of the N data blocks; and the starting position is a first bit, a first symbol, or a first byte.

[0291] In a possible implementation, the apparatus 400 further includes a processing unit 402 configured to measure a first time delay corresponding to data at each of the plurality of specific positions, to obtain a plurality of first time delays; and the target time delay includes a maximum value and / or a minimum value in the plurality of first time delays.

[0292] In a possible implementation, the sending unit 401 is configured to report the target time delay corresponding to data at the plurality of specific positions in the data stream to a medium access control (MAC) layer.

[0293] For specific implementation of each unit of the apparatus 400, refer to the description of the time delay reporting method provided in the above embodiments. The apparatus 400 can implement the time delay reporting method described in the above embodiments, and the description is not repeated here. Each unit in the apparatus 400 can be a software unit implemented by a computer program or a hardware unit implemented by a circuit.

[0294] In another specific example, the foregoing time delay reporting apparatus can include a circuit configured to perform the time delay reporting method provided in the above embodiments.

[0295] The time delay reporting device mentioned in the embodiments of the present application can be an optical module or a PHY chip.

[0296] In one example, the structure of the PHY chip or the optical module can be as shown in Figure 5 Referring to Figure 5 , the figure is a structure schematic diagram of a PHY chip or an optical module provided by an embodiment of the present application. Figure 5 The PHY chip or the optical module 500 shown in the figure includes an interface circuit 501 and a processing circuit 502. The interface circuit 501 is configured to receive and / or send data, and the processing circuit 502 is configured to process data. The PHY chip or the optical module 500 can implement the time delay reporting method described in the above embodiments. The interface circuit 501 and the processing circuit 502 can be divided in an actual circuit structure, that is, the PHY chip or the optical module 500 includes two parts of circuits, which are the interface circuit 501 and the processing circuit 502. Alternatively, the interface circuit 501 and the processing circuit 502 can be divided in a functional logic, that is, the PHY chip or the optical module 500 includes an integral circuit, which can implement the process of receiving and / or sending data by the interface circuit 501, and can also implement the process of data processing by the processing circuit 502.

[0297] In one example, the interface circuit 501 is configured to report target time delays corresponding to data at a plurality of specific positions in a data stream, and the plurality of specific positions are spaced apart by a fixed length; wherein: a period of the plurality of specific positions corresponds to a length of one or more convolution interleaving sequences, and the specific positions correspond to delay lines with maximum or minimum introduced time delays in convolution interleaving; or, a period of the plurality of specific positions corresponds to a length of one or more distribution sequences, and each of the distribution sequences corresponds to eight sub-sequences after distribution; or, a period of the plurality of specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponds to a forward error correction (FEC) code word, N is a positive integer, and a length of each of the data blocks is: 120 bits, or 128 bits, or 110 bits, or 126 bits. The processing circuit 502 is configured to measure a first time delay corresponding to data at each of the plurality of specific positions, to obtain a plurality of first time delays; wherein the target time delays include a maximum value and / or a minimum value in the plurality of first time delays.

[0298] Referring to Figure 6 , the figure is a structure schematic diagram of a device provided by an embodiment of the present application. Figure 6The device 600 shown includes interface circuitry 601 and processing circuitry 602. The interface circuitry 601 is configured to receive and / or transmit data, and the processing circuitry 602 is configured to process data. The device 600 can implement the time delay reporting method described in the above embodiments. The interface circuitry 601 and the processing circuitry 602 can be logically divided, that is, the device 600 includes two parts of circuitry, namely the interface circuitry 601 and the processing circuitry 602. Alternatively, the interface circuitry 601 and the processing circuitry 602 can be logically divided, that is, the device 600 includes an overall circuit, which can implement the process of receiving and / or transmitting data by the interface circuitry 601, and can also implement the process of data processing by the processing circuitry 602.

[0299] As a specific example, the interface circuitry 601 is configured to report target time delays corresponding to data at a plurality of specific positions in a data stream, the plurality of specific positions being spaced apart by a fixed length; wherein: a period of the plurality of specific positions corresponds to a length of one or more convolution interleaving sequences, the specific positions corresponding to delay lines introducing maximum or minimum time delays in convolution interleaving; or, a period of the plurality of specific positions corresponds to a length of one or more distribution sequences, each of the distribution sequences corresponding to eight sub-sequences after distribution; or, a period of the plurality of specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponding to a forward error correction (FEC) code word, N being a positive integer, and a length of each of the data blocks being: 120 bits, or 128 bits, or 110 bits, or 126 bits. The processing circuitry 602 is configured to measure a first time delay corresponding to data at each of the plurality of specific positions to obtain a plurality of first time delays; wherein the target time delays include a maximum value and / or a minimum value of the plurality of first time delays.

[0300] Referring to Figure 7 The figure is a structural schematic diagram of a device provided by an embodiment of the application.

[0301] In one example, Figure 7 The device 700 shown can be used to execute the time delay reporting method corresponding to the above method embodiments. Figure 2 The time delay reporting method corresponding to the above method embodiments.

[0302] Referring to Figure 7 As shown, the device 700 includes a communication interface 720. The communication interface 720 is configured to execute the time delay reporting method corresponding to the above method embodiments. Figure 2 The time delay reporting method corresponding to the above method embodiments.

[0303] In one example, the device 700 can further include a processor 710. The number of processors 710 in the device 700 can be one or more,Figure 7 The processor 710 is taken as an example. The processor 710 and the communication interface 720 jointly perform the corresponding delay reporting method provided by the above method embodiments. Figure 2 For example, the processor 710 is configured to measure a first delay corresponding to each specific position of data in the data of the plurality of specific positions of data in the data stream, to obtain a plurality of first delays; wherein the target delay includes a maximum value and / or a minimum value in the plurality of first delays. The communication interface 720 is configured to report the target delay corresponding to the data of the plurality of specific positions of data in the data stream.

[0304] The processor 710 can be a central processing unit (CPU), an NP, or a combination of the CPU and the NP. The processor 710 can include a digital signal processor (DSP). The processor 710 can further include a hardware chip. The hardware chip can be an ASIC, a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0305] In one example, the device 700 further includes a memory 730. The memory 730 can include a volatile memory (English: volatile memory), such as a random-access memory (RAM); the memory 730 can also include a non-volatile memory (English: non-volatile memory), such as a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD); the memory 730 can also include a combination of the above types of memory. The memory 730 may, for example, store the aforementioned target delay.

[0306] Optionally, the memory 730 stores an operating system and programs, executable modules or data structures, or subsets thereof, or extended sets thereof, wherein the programs can include various operation instructions for implementing various operations. The operating system can include various system programs for implementing various basic services and processing hardware-based tasks. The processor 710 can read the programs in the memory 730 to implement the method provided by the embodiments of the application.

[0307] In the embodiments of the present application, the processor 710, the communication interface 720 and the memory 730 can be connected through a bus system or other manners, wherein, Figure 7 In the embodiments of the present application, the processor 710, the communication interface 720 and the memory 730 can be connected through a bus system or other manners, wherein,

[0308] The bus system 740 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus system 740 can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 7 In the embodiments of the present application, the processor 710, the communication interface 720 and the memory 730 can be connected through a bus system or other manners, wherein,

[0309] The time delay reporting device 400, the PHY chip or the optical module 500, the device 600 and the device 700 provided in the above can be network devices such as switches, routers, SPN devices or OTN devices, can be a part of components on the network device, for example, a single board or a line card or an interface on the network device, can be a functional module on the network device, can be a chip, can be a pluggable optical module on the network device, can be a server, a network card on the server or a network card of other devices, etc., and the embodiments of the present application are not limited specifically.

[0310] The terms "first", "second", "third", "fourth" and the like (if any) in the description and claims of the present application and the above-described figures are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in other than the order illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0311] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0312] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the division of the above-described device embodiments is merely a logical division, and there can be other division manners in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling or direct coupling or communication connection between units can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or in other forms.

[0313] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments.

[0314] In addition, each service unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present alone, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software service unit.

[0315] If the integrated unit is realized in the form of a software service unit and sold or used as a separate product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application or the essential part or all or part of the technical solutions that make contributions to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0316] Those skilled in the art should understand that, in one or more examples described above, the described services of the present application can be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the services can be stored in or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.

[0317] The above detailed description sets forth the purposes, technical solutions, and beneficial effects of the present application. It should be understood that the above is merely a specific implementation of the present application.

[0318] The above examples are merely used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for reporting a time delay, the method comprising: The method comprises: reporting a target time delay corresponding to data at a plurality of specific positions in a data stream, the plurality of specific positions being spaced apart by a fixed length; wherein: a period of the plurality of specific positions corresponds to a length of one or more convolution interleaving sequences, the specific positions corresponding to a delay line introducing a maximum or minimum time delay in convolution interleaving; or, a period of the plurality of specific positions corresponds to a length of one or more distribution sequences, each of the distribution sequences corresponding to eight sub-sequences after distribution; or, a period of the plurality of specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponding to a forward error correction (FEC) code word, N being a positive integer, a length of each of the data blocks being: 120 bits, or 128 bits, or 110 bits, or 126 bits.

2. The method of claim 1, wherein, The delay line introducing the maximum or minimum time delay is a first delay line among three delay lines in convolution interleaving.

3. The method of claim 2, wherein: the first delay line is configured to delay each data unit received thereby by 2*Q*D bits, a second delay line among the three delay lines is configured to delay each data unit received thereby by Q*D bits, and a third delay line among the three delay lines is configured not to perform a delay operation on each data unit received thereby, D being a number of bits included in each data unit, and Q being a positive integer; or, the third delay line is configured to delay each data unit received thereby by 2*Q*D bits, the second delay line is configured to delay each data unit received thereby by Q*D bits, and the first delay line is configured not to perform a delay operation on each data unit received thereby.

4. The method of claim 3, wherein, Q is 544 or 272 or 136 or 68.

5. The method of claim 1, wherein, The delay line introducing the maximum or minimum time delay is a third delay line among three delay lines in convolution interleaving.

6. The method of claim 5, wherein: the first delay line is configured not to perform a delay operation on each data unit received thereby, a second delay line among the three delay lines is configured to delay each data unit received thereby by 6*D bits, and a third delay line among the three delay lines is configured to delay each data unit received thereby by 12*D bits, D being a number of bits included in each data unit; or, the third delay line is configured not to perform a delay operation on each data unit received thereby, the second delay line is configured to delay each data unit received thereby by 6*D bits, and the first delay line is configured to delay each data unit received thereby by 12*D bits.

7. The method according to any one of claims 1 to 6, characterized in that, Each of the convolution interleaving sequences includes three data units, and each of the three data units includes 40 bits.

8. The method of claim 1, wherein, Each of the distribution sequences includes eight data blocks, each of the distribution sequences is configured to perform a 1:8 distribution process, or each of the distribution sequences is a sequence obtained by performing an 8:1 multiplexing process, and the specific positions correspond to a first stream among eight streams corresponding to the 1:8 distribution process or the 8:1 multiplexing process.

9. The method of claim 1, wherein: The N is 8 or 32; or The FEC code word is an FEC inner code code word after outer code FEC encoding processing and inner code FEC encoding; or The FEC inner code code word is a Hamming code code word or a BCH code code word; or The data stream is a data stream received through an attachment unit interface (AUI); or The data stream is a data stream obtained by performing inner code FEC decoding.

10. The method of any of claims 1-6, 8 or 9, wherein the specific positions correspond to starting positions of the one or more convolutional interleaving sequences; or The specific positions correspond to starting positions of the one or more distribution sequences; or The specific positions correspond to starting positions of integer multiples of the N data blocks; and The starting positions are first bits, first symbols or first bytes. The method further comprises:

11. The method according to any one of claims 1-6, 8 or 9, characterized in that, Measuring a first time delay corresponding to data at each of the specific positions in the data stream, to obtain a plurality of first time delays; The target time delay includes a maximum value and / or a minimum value of the plurality of first time delays. Reporting a target time delay corresponding to data at a plurality of specific positions in a data stream, comprising:

12. The method of any one of claims 1-6, 8, or 9, wherein, Reporting the target time delay corresponding to data at the plurality of specific positions in the data stream to a media access control (MAC) layer. The apparatus is configured to perform the method of any of claims 1-12.

13. A delay reporting apparatus, comprising: The apparatus comprises a circuit; 14. A delay reporting apparatus, comprising: The circuit is configured to perform the method of any of claims 1-12.

15. The apparatus of claim 14, wherein the apparatus is: An optical module, or a physical (PHY) layer chip. ​

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