45 results about "Interleaving" patented technology

The invention discloses a TCM-mode-based Si-SiC hybrid power multi-phase staggered H-bridge converter structure and a control method thereof, according to the scheme, a three-phase staggered parallel topology of a two-phase low-frequency Si-IGBT bridge arm and a one-phase high-frequency SiC-MOSFET bridge arm is adopted, and a TCM control strategy is combined, so that zero voltage switching (ZVS) of a Si device is successfully realized, the switching loss is remarkably reduced, and the switching efficiency is improved. The system efficiency is greatly improved; and meanwhile, through pilot frequency interleaving and ripple compensation technologies, total output current ripples are greatly reduced, and optimal balance between system performance and manufacturing cost is realized while the power capacity of the converter is remarkably expanded and the dynamic response speed and the output electric energy quality are improved.

The embodiment of the invention is suitable for the technical field of computers, and provides a chip system and a channel interleaving method thereof, the chip system comprises a main core grain and a plurality of storage units, at least one storage unit channel is arranged between the main core grain and each storage unit, and the main core grain comprises a main interleaving module comprising a memory channel interleaving unit; the memory channel interleaving unit is configured to perform first interleaving transformation on the address of the access request according to the address of the access request and a first interleaving parameter to obtain a target address, and the first interleaving parameter comprises the number of storage units corresponding to the access request; and the main routing module is configured to transmit an access request to the target storage unit through the corresponding storage unit channel according to the target address. According to the embodiment of the invention, the address of the access request can be subjected to first interleaving transformation by the independent memory channel interleaving unit instead of a main routing module, the method is suitable for different main core grains, the access request is sent to the target storage unit, and balanced access of the storage unit is realized.

The present application relates to the technical field of communications, and discloses an interleaved information indication method and apparatus, an interleaved information receiving method and apparatus, and a device. The interleaved information indication method in embodiments of the present application comprises: a first device sends first information to a second device, the first information being used for indicating an association parameter for inter-codeblock interleaving.

The present invention provides an interleaving method and a related device for mapping a virtual resource block to a physical resource block (VRB-to-PRB) during a sub-band full duplex (SBFD) period, and a method for mapping a virtual resource block to a physical resource block (VRB-to-PRB) during the SBFD period of the sub-band full duplex (SBFD) period of the sub-band full duplex (SBFD) period of the sub-band full duplex (SBFD) period of the sub-band full duplex (SBFD) period of the virtual resource block to the physical resource block (VRB-to-PRB). In one embodiment, the method includes performing a VRB-to-PRB interleaving during the SBFD to interleave resource blocks (RBs) and map a VRB beam to a PRB beam in a first DL frequency domain and a second DL frequency domain. By the method, the VRB-to-PRB interleaving is enhanced in the SBFD operation, thereby being able to benefit from less frequency selective fading.

Provided are a method, system, and computer program product in whichdata is encoded for a plurality of tracks of a tape of a tape drive, by using an error correction code (ECC) scheme that applies a single code with code word symbols that are at least 10 bits. The code word symbols are interleaved along and across parallel tracks of the tape in the tape drive.

Embodiments of this application disclose a data processing method and a data processing device, which can achieve good performance of a connected FEC-based solution in low-latency scenarios. In a connected FEC-based transmission solution, before convolutional interleaving is performed on a first data stream, interleaved alignment must first be performed to determine the boundaries of each bit set in the first data stream and the boundaries of each bit subset within each bit set. Furthermore, in the convolutional interleaving process, bit subsets are transmitted to each storage unit as granularity. In other words, each bit subset contains d bits, and each storage unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

The invention relates to the technical field of electronics, and discloses a VOT compensation-based single-phase interleaved CRM PFC digital control system and method, and the system comprises a DSP controller, a first power loop, a second power loop, a first off-chip comparator, a second off-chip comparator, and a driver. An EPWM driving module, an ADC sampling module, an on-chip DC digital comparator module and a TZ trigger interrupt module are integrated in the DSP controller, a 2P2Z controller, a voltage feedforward operation unit, a current detection verification unit and a temperature protection unit are further arranged in the DSP controller, the TZ trigger interrupt module is provided with a TZ2 pin and a TZ3 pin, and the EPWM driving module is provided with a first comparison register CMPA, a period register TBPRD and a second comparison register CMPB. The first power loop and the second power loop form a single-phase and two-phase staggered Boost topology, and the two Boost circuits are staggered and connected in parallel at a 180-degree initial phase and are jointly connected to the same PFC bus. According to the invention, the circuit design is simplified, the dynamic stability of inductive current interleaving is optimized, and the THD index of the power supply is improved.

The invention discloses a communication system of an improved parallel cascade LDPC code structure based on a single encoder, and belongs to the technical field of aviation platform laser communication. Aiming at the bottlenecks that the traditional PCGC depends on double encoders, the hardware overhead is large, the decoding delay is high and the complementarity requirement on component codes is harsh, the system adopts a single encoder architecture design: firstly, a basic verification sequence is generated through a single LDPC encoder, and differential verification constraints are constructed through interleaving and repeating operations; meanwhile, a zero syndrome and non-zero syndrome dual-check sequence design is introduced, so that the minimum distance of a code word is increased; a decoding end fuses a normalized minimum sum algorithm and a hierarchical message updating and dynamic early stop mechanism, combines channel sensing soft information construction and a self-adaptive interleaving and redundancy allocation strategy, and adapts to composite channel characteristics of an aviation platform.

A method for improving the forward error correction in serial coding in a data transmission in a vehicle allowing the physical behavior on a transmission channel to always be deterministically controlled despite a reduction in the resource requirements. Tit errors are minimal and a transmission error can be corrected efficiently. In addition, encoders used are designed with a minimum number of gates and an interleaving is implicit in the proposed method, which is based on the fact that burst errors can be corrected particularly advantageously. This interleaving makes it possible to dispense with conventional buffer memory required for explicit interleaving. In addition, user data together with correcting metadata can be encoded advantageously. It can be ensured that not only the user data is line-coded or line-encoded, but also the correction data. Also provided is a system for implementing the method.

The application discloses a magnetic tape storage adaptive interleaving method and system based on dynamic error mode detection, relates to the technical field of magnetic tape interleaving, and comprises the following steps: continuously collecting error information in a magnetic tape reading and writing process and forming a structured report; judging the received structured report according to a preset rule, dynamically calculating new interleaving parameters, and outputting a decision package containing a new interleaving depth factor and a new available track list; checking whether the parameters in the received decision package are within a preset range, and if yes, sending an instruction to a magnetic tape drive through a bottom driver interface, setting new interleaving configuration for the magnetic tape, and obtaining a success status code returned by the magnetic tape drive; and the interleaving method significantly improves the reliability and error correction efficiency of the magnetic tape storage system in a complex error environment, reduces redundancy, and improves the effective utilization rate of storage space.

The invention discloses an interaction method and device between a host application and a plug-in, equipment and a medium, which are applied to the host application and comprise the following steps: when a plug-in calling request of a user is received, loading a target plug-in corresponding to the plug-in calling request, reading an interface type on which the target plug-in depends, and sending the interface type to the host application; detecting whether a target interface corresponding to the interface type is defined in the host application or not, obtaining a detection result, obtaining an instance object corresponding to the target interface according to the detection result, and injecting the instance object into the plug-in running environment, so that the host application and the target plug-in interact through the target interface and the instance object in the plug-in running environment. The coupling degree of the codes between the host application and the target plug-in is reduced, the problems of modification limitation, difficult expansion and the like caused by close interleaving of the codes are avoided, and the interaction flexibility between the host application and the target plug-in is improved.

Embodiments of this application disclose a data processing method and a data processing apparatus, so that good performance of a concatenated FEC-based solution can be achieved in a scenario with a low latency. For a concatenated FEC-based transmission solution, interleaving alignment needs to be first performed before convolutional interleaving is performed on a first data stream, to determine a boundary of each bit set in the first data stream and a boundary of each bit subset in the bit set. Further, bit subsets are sent as a granularity to each storage unit in a convolutional interleaving operation. In other words, each bit subset includes d bits, and each storage unit is configured to store d bits. The bits in each bit subset are from v symbols, and the v symbols are respectively from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

The invention discloses an interleaving method combining dynamic bit loading and ROBO interleaving. According to the method, sending parameters are configured at a sending end based on copy times, subcarrier granularity and a modulation loading table which are fed back by a receiving end; then frame control and frame load data are processed respectively, improved ROBO interleaving combined with Bitloading is adopted for frame load, and framing is carried out on the frame load and a preamble signal through the steps of IFFT, cyclic prefix adding and the like. And after completing signal recovery and subcarrier SNR evaluation, a receiving end dynamically determines and feeds back key parameters according to different system requirements of low feedback signaling or high transmission rate. And the sending end reconfigures and generates the data frame according to the feedback. Through deep fusion of Bitloading and ROBO interleaving and flexible parameter adaptation, transmission reliability, rate and feedback overhead are effectively considered in a complex channel environment, and efficient data transmission with a low frame error rate is realized.

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

A data processing method includes, for a concatenated FEC-based transmission solution, interleaving alignment that is first performed before convolutional interleaving is performed on a first data stream, to determine a boundary of each bit set in the first data stream and a boundary of each bit subset in the bit set. Further, bit subsets are sent as a granularity to each storage unit in a convolutional interleaving operation. Each bit subset includes d bits, and each storage unit is configured to store d bits. The bits in each bit subset are from v symbols, and the v symbols are respectively from v first codewords. One symbol is selected from each of the v first codewords to form a bit subset.

The application provides a control method and device of an interleaved parallel system, a controller and the interleaved parallel system. The control method of the interleaved parallel system comprises the following steps: obtaining the demand range of the switching frequency, the switching carrier interleaving times and the control frequency of the interleaved parallel system; determining the control frequency division number of the interleaved parallel system based on the demand range of the switching frequency, the switching carrier interleaving times and the control frequency; determining the target control frequency of the interleaved parallel system based on the switching frequency and the control frequency division number, and controlling the interleaved parallel system based on the target control frequency. The application can control different interleaved parallel systems by only obtaining the switching frequency and the switching carrier interleaving times of the interleaved parallel system, without developing new software program architecture. One set of software program architecture can be compatible with interleaved parallel systems with different switching frequencies and switching carrier interleaving times.

The application discloses a data interleaving method and device, and relates to the field of optical fiber communication systems.The method comprises the following steps: dividing an input bit data stream into a plurality of first data blocks by taking 4 bits as a unit, exchanging 2 bits of data in the middle of each first data block; dividing the exchanged bit data stream into second data blocks by taking 512 bits as a unit, and performing intra-block interleaving; and performing inter-block interleaving on the bit data stream after the intra-block interleaving through two random access memories.The application guarantees the original probability distribution characteristics of the PCS technology, and improves the ability of correcting burst errors in the joint application of the FEC technology and the PCS technology.

An address mapping method, apparatus and device based on DDR interleaving, and a storage medium relate to the field of computer storage, and comprise: performing sequential mapping operation on interleaving bits of a basic address block through a lookup table to obtain a target mapping address; calculating the relative offset of different basic address blocks in the same DDR according to the distribution number of sub-address blocks interleaved from the basic address blocks in the DDR channel y before interleaving to the DDR channel x after interleaving and the serial numbers of the basic address blocks; determining self-adaptive offset among different DDR channels based on the number of sub-address blocks, mapped to the interleaved DDR channel x, of all the DDR channels before the DDR channel y before interleaving; and a target address corresponding to the interleaved address is generated based on the topdrbit, the target mapping address, the relative offset, the adaptive offset and the target address bit corresponding to the interleaving granularity, so that the interleaved addresses to each DDR are still arranged in sequence, and the read-write performance of the DDR is improved.

The application provides a method and a communication device for interleaving, the method comprising: obtaining, by a sending device, C first bit sequences, the C first bit sequences being bit sequences obtained through channel coding; and performing, by the sending device, M times of bit interleaving on the C first bit sequences, one time of bit interleaving in the M times of bit interleaving being related to a plurality of first bit sequences in the C first bit sequences, and / or at least two times of bit interleaving in the M times of bit interleaving being related to one first bit sequence in the C first bit sequences, wherein C and M are positive integers. In the method, the number of the first bit sequences and the number of times of bit interleaving are not in a one-to-one correspondence, for example, a plurality of first bit sequences can be concatenated into a bit sequence with a length less than or equal to a maximum bit sequence length supported by a bit interleaver, and the concatenated bit sequence is interleaved by using one bit interleaver, thereby improving resource utilization of the bit interleaver.

The present invention relates to a method for improving forward error correction in serial coding in data transmission in a vehicle and, compared to the prior art, the invention produces, inter alia, the advantage that physical behavior on the transmission channel can always be deterministically controlled despite reduced resource requirements. Thus, according to the proposed method, bit errors are few, and transmit errors can be corrected efficiently (i.e., with little technical effort). Furthermore, the encoder used is designed to have a minimum number of gates, and interleaving is implied in the proposed method based on the fact that so-called burst errors can be particularly advantageously corrected. This implicit interleaving makes it possible to dispense with the conventional buffer memory required for explicit interleaving. In addition, the present invention ensures that user data together with correction metadata can be advantageously encoded with respect to transmission. According to the invention, not only user data can be ensured, but also correction data can be ensured to be line-coded or line-coded. The invention also relates to a similarly designed system arrangement for carrying out the method, and to a computer program product having control commands for carrying out the method.

The invention provides a rapid implementation method of a high-performance low-bit-rate Turbo code IP core, which comprises the following steps of: splitting overall data in a segmented and parallel manner, providing a hardware architecture foundation for parallel operation, further splitting sub-blocks by sliding window processing, reducing single block storage requirements, completing core probability calculation by measurement calculation, and taking output extrinsic information as input of parallel interleaving, so as to achieve the purpose of parallel interleaving. And parallel interleaving is carried out to realize transmission of external information between the two component decoders until iteration is terminated. According to the method, the time delay is reduced, the throughput is improved, the occupation of storage resources is reduced, hardware is easy to implement, the decoding correctness is ensured, and the error rate requirement of an LTE communication system is met.

The application provides an unknown vulnerability scanning verification method and system based on an active trapping technology, and relates to the field of security technology, wherein the method comprises the following steps: obtaining trapping parameters and instantiating a plurality of trapping containers on idle computing nodes, screening out one with the largest number of connections with external access objects as a main trapping container to maintain an interactive session, recording the time sequence of each memory page table item dirty bit being set and the physical page number address sequence, generating vulnerability detection parameters through interleaving and recombination and splitting into illegal instruction data and abnormal condition data, and storing them into the reserved bit segment of the instruction cache and the reserved bit segment of the exception vector table register, respectively, monitoring the instruction decoding result and the abnormal condition matching state during the execution of the simulation image asset, positioning the pollution propagation path of the unknown vulnerability in the instruction execution pipeline and marking the existence and pollution depth thereof. The application improves the detection accuracy and scanning verification efficiency of unknown vulnerabilities.

Wireless communication systems and methods related to sidelink communication between user equipments (UEs) are disclosed. A first UE determines a power level of a physical sidelink format indicator channel (PSFCH) having multiple interleaving resource blocks (RBs) and / or common interleaving. If the reference power level is provided by a network device, such as a base station, the UE may determine a power level based on the reference power level. The UE may also determine a power level based on a maximum support power level for the UE. In some embodiments, common interleaving uses a fixed percentage of maximum UE power. In other embodiments, the available transmit power is evenly divided between the PSFCH RB and the common interleaving. When the scheduled PSFCH exceeds a power limit, a priority PSFCH drop rule may be implemented.

At least one processor may obtain a plurality of test pattern data sets for a plurality of cores of an integrated circuit to be applied via a shared testing input bus. The at least one processor may next generate a test data sequence including an interleaving of respective task procedures of the plurality of test pattern data sets, where the generating of the test data sequence includes generating sleep instructions for respective cores of the plurality of cores in accordance with the interleaving. The at least one processor may then apply the test data sequence via the shared testing input bus.

An apparatus and related method are disclosed. The apparatus includes: a port; a memory circuitry; and a processing circuitry coupled to the port and the memory circuitry. The processing circuitry receives a plurality of commands through the port, said plurality of commands coming from at least two hosts using an inserter, and said plurality of commands include a corresponding memory address and a corresponding port identifier (ID). The processing circuitry divides each of the received commands into a plurality of segments, each segment having a predetermined transfer size. The processing circuitry also transfers each segment of each command to a corresponding data structure instance corresponding to the port ID of the corresponding received command, and performs the data transfer of each of the plurality of segments by accessing the memory circuitry at each corresponding memory address associated with each segment.

The present application relates to the technical field of wireless communications, and provides an interleaving method and apparatus and a deinterleaving method and apparatus, aiming to support the interleaving of sequences having different numbers of CRC bits. The interleaving method comprises: a first communication device acquires a first bit sequence, the first bit sequence comprising A information bits and L check bits; and the first communication device interleaves the first bit sequence on the basis of a first interleaving sequence or a second interleaving sequence, wherein in the first interleaving sequence, the number of positions corresponding to information bits is A, and the number of positions corresponding to check bits is L; in the second interleaving sequence, the number of positions corresponding to information bits is Kmax, and the number of positions corresponding to check bits is L; and in a target interleaving sequence, the number of positions corresponding to information bits is Kmax, and the number of positions corresponding to check bits is Lmax. The described solution provides support for an interleaving sequence whose check bit length L is less than or equal to Lmax, and can be applied to interleaving operations in different scenarios.

This invention relates to a method for improving forward error correction of serial coding in data transmission within a vehicle, and compared to the prior art, it offers the advantage of always being able to deterministically control the physical behavior on the transmission channel while reducing resource requirements. Accordingly, according to the proposed method, bit errors are minimized, and transmission errors can be corrected efficiently, i.e., with minimal technical effort. Furthermore, the encoder used is designed with a minimum number of gates, and interleaving is implicitly provided in the proposed method, which is based on the fact that so-called burst errors can be corrected particularly favorably. This implicit interleaving makes it possible to eliminate the buffer memory that was conventionally required for explicit interleaving. In addition, the invention ensures that user data can be encoded favorably with respect to transmission along with correction metadata. According to the invention, it can be guaranteed that not only user data but also correction data can be line-coded or line-encoded. The invention also relates to a system device similarly designed to perform this method, and a computer program product having control commands for performing this method.

Provided in the embodiments of the present disclosure are an ODUCn mapping method, an electronic device, a storage medium and a program product. The method comprises: acquiring the bandwidth and the degree of parallelism of a target service, determining the multiple yi of the bandwidth with respect to a unit bandwidth, and determining the multiple m×yi of the degree of parallelism of the target service with respect to a predetermined data size; acquiring service data to be processed of the target service within the current clock cycle; determining yi mapping channels for mapping the target service; dividing said service data into m×yi data blocks of equal size, and allocating the m×yi data blocks to the yi mapping channels; and mapping the data blocks allocated to the mapping channels to containers corresponding to the mapping channels. The solution of the embodiment allows a service data transmission process to have good uniformity, effectively reducing the degree of data burstiness, a waste of logical resources caused by time slot interleaving, and the complexity of implementation.

A sub-block interleaving for polarity coding systems, processes, and signaling is disclosed. A wireless transmit / receive unit (WTRU) may generate a plurality of polarity coded bits using polarity coding. The WTRU may divide the plurality of polarity coded bits into sub-blocks of the same size in a sequential manner. The WTRU may apply sub-block type interleaving to the sub-block by using an interleaver mode. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block interleaving may include interleaving on the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may cascade bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a ring buffer. The WTRU may select a plurality of bits from the interleaved bits for transmission.