81 results about "Interleaving" patented technology

The invention discloses a TCM-mode-based Si-SiC hybrid power multi-phase staggered H-bridge converter structure and a control method thereof, according to the scheme, a three-phase staggered parallel topology of a two-phase low-frequency Si-IGBT bridge arm and a one-phase high-frequency SiC-MOSFET bridge arm is adopted, and a TCM control strategy is combined, so that zero voltage switching (ZVS) of a Si device is successfully realized, the switching loss is remarkably reduced, and the switching efficiency is improved. The system efficiency is greatly improved; and meanwhile, through pilot frequency interleaving and ripple compensation technologies, total output current ripples are greatly reduced, and optimal balance between system performance and manufacturing cost is realized while the power capacity of the converter is remarkably expanded and the dynamic response speed and the output electric energy quality are improved.

Variable width interleaved coding for graphics processing is described. An example of an apparatus includes one or more processors including a graphic processor; and memory for storage of data including data for graphics processing, wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to receive a plurality of bitstreams from workgroups; perform parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups; perform variable interleaving of the bitstreams for each workgroup based at least in part on data requirements for decoding received from the decoder pipeline; and compact outputs for each of the workgroups into a contiguous stream of interleaved data.

The invention relates to the technical field of computer networks, and discloses a distributed model training-oriented congestion control method and device, and a medium. The method comprises the following steps: when a cooperative switch receives a local gradient data packet, updating the total communication traffic required to be transmitted by each training task in a task total communication traffic table according to a corresponding field; when the cooperative switch receives the global gradient data packet, the residual communication traffic of each training task in the task total communication traffic table is updated according to the corresponding field, and the residual communication traffic is broadcasted to each working node, so that the working node updates the residual communication traffic of each training task in the residual communication traffic table; when network congestion is detected, calculating a real-time proportion, and dynamically adjusting a sending rate of a working node corresponding to each training task through an increasing function; a working node senses the existence of other training tasks, the residual communication traffic of the other training tasks in the communication stage of the current iteration round is obtained, and the training task with less residual communication traffic obtains a larger bandwidth, so that the communication stage staggering is realized, and the link utilization rate is improved.

The embodiment of the invention provides a time delay reporting method, and the method comprises the steps: reporting target time delays corresponding to data at a plurality of specific positions in a data stream, and enabling the specific positions to be spaced by a fixed length; wherein the period of the plurality of specific positions corresponds to the length of one or more convolution interleaving sequences, and the specific positions correspond to a delay line with the maximum or minimum time delay introduced in convolution interleaving; or, the period of the plurality of specific positions corresponds to the length of one or more distribution sequences, and each distribution sequence corresponds to eight distributed subsequences; or the period of the plurality of specific positions corresponds to an integral multiple of N data blocks, each data block in the N data blocks corresponds to a forward error correction (FEC) code word, N is a positive integer, and the length of each data block is 120 bits, or 128 bits, or 110 bits, or 126 bits. By using the scheme, the time delay can be accurately reported.

Various embodiments include a memory controller and methods for implementing functions of the memory controller for hardware and software hybrid configuration of memory channel interleaving management. Embodiments may include a memory controller having a signaling mechanism configured to provide a configuration signal for indicating to the memory controller a layer of a memory channel interleaving hierarchy for software memory channel interleaving management, a processor configured to read the configuration signal and select the layer of the memory channel interleaving hierarchy for software memory channel interleaving management based on the configuration signal, and an integrated circuit configured to implement memory channel interleaving according to a layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management. In some embodiments, the layers for software or hardware memory channel interleaving management may include any of an intra-memory channel group, an inter-memory channel group, or an inter-die memory channel group layer.

The embodiment of the invention is suitable for the technical field of computers, and provides a chip system and a channel interleaving method thereof, the chip system comprises a main core grain and a plurality of storage units, at least one storage unit channel is arranged between the main core grain and each storage unit, and the main core grain comprises a main interleaving module comprising a memory channel interleaving unit; the memory channel interleaving unit is configured to perform first interleaving transformation on the address of the access request according to the address of the access request and a first interleaving parameter to obtain a target address, and the first interleaving parameter comprises the number of storage units corresponding to the access request; and the main routing module is configured to transmit an access request to the target storage unit through the corresponding storage unit channel according to the target address. According to the embodiment of the invention, the address of the access request can be subjected to first interleaving transformation by the independent memory channel interleaving unit instead of a main routing module, the method is suitable for different main core grains, the access request is sent to the target storage unit, and balanced access of the storage unit is realized.

The present application relates to the technical field of communications, and discloses an interleaved information indication method and apparatus, an interleaved information receiving method and apparatus, and a device. The interleaved information indication method in embodiments of the present application comprises: a first device sends first information to a second device, the first information being used for indicating an association parameter for inter-codeblock interleaving.

The present invention provides an interleaving method and a related device for mapping a virtual resource block to a physical resource block (VRB-to-PRB) during a sub-band full duplex (SBFD) period, and a method for mapping a virtual resource block to a physical resource block (VRB-to-PRB) during the SBFD period of the sub-band full duplex (SBFD) period of the sub-band full duplex (SBFD) period of the sub-band full duplex (SBFD) period of the sub-band full duplex (SBFD) period of the virtual resource block to the physical resource block (VRB-to-PRB). In one embodiment, the method includes performing a VRB-to-PRB interleaving during the SBFD to interleave resource blocks (RBs) and map a VRB beam to a PRB beam in a first DL frequency domain and a second DL frequency domain. By the method, the VRB-to-PRB interleaving is enhanced in the SBFD operation, thereby being able to benefit from less frequency selective fading.

Provided are a method, system, and computer program product in whichdata is encoded for a plurality of tracks of a tape of a tape drive, by using an error correction code (ECC) scheme that applies a single code with code word symbols that are at least 10 bits. The code word symbols are interleaved along and across parallel tracks of the tape in the tape drive.

The present invention provides a channel interleaving method, apparatus and chip, including: calculating a first end row index corresponding to the rank indication data in a predetermined interleaving table, a first filling quantity of the corresponding rank indication data in the first end row, a second end row index corresponding to the retransmission feedback data, and a second filling quantity of the corresponding retransmission feedback data in the second end row according to the lengths of the rank indication data and the retransmission feedback data; obtaining a mapping relationship between the current data to be output and the row index and column index of the interleaving table according to the output rule of the predetermined interleaving table; calculating the data type and offset value corresponding to the current data according to the row index mapped by the current data, the column index mapped by the current data, the first end row index, the first filling quantity, the second end row index, the second filling quantity, and the data quantity of each row; and obtaining the corresponding data according to the current data type and offset value to complete channel interleaving. The present invention can save the buffer space required by the interleaver.

Embodiments of this application disclose a data processing method and a data processing device, which can achieve good performance of a connected FEC-based solution in low-latency scenarios. In a connected FEC-based transmission solution, before convolutional interleaving is performed on a first data stream, interleaved alignment must first be performed to determine the boundaries of each bit set in the first data stream and the boundaries of each bit subset within each bit set. Furthermore, in the convolutional interleaving process, bit subsets are transmitted to each storage unit as granularity. In other words, each bit subset contains d bits, and each storage unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

Embodiments of the present application disclose a data processing method, device, and system. The application ensures that the overall data processing operations are simple, and achieves low complexity and low power consumption while increasing spectrum utilization and improving system transmission performance. Specifically, PCS processing is performed on a first bit set among a plurality of bits to obtain a second bit set. Also, a first interleaving is performed on the second bit set and a third bit set, which consists of the plurality of bits excluding the first bit set, so as to obtain a first fourth bit set and a second fourth bit set. Then, FEC encoding is performed using a fifth bit set as granularity. For example, a first fifth bit set comprises at least one first fourth bit set, a second fifth bit set comprises at least one second fourth bit set, and the two fifth bit sets each undergo FEC encoding to obtain two sixth bit sets. The two sixth bit sets are each subjected to a second interleaving to obtain two seventh bit sets. A third interleaving is performed on the two seventh bit sets to obtain an eighth bit set.

The invention relates to the technical field of electronics, and discloses a VOT compensation-based single-phase interleaved CRM PFC digital control system and method, and the system comprises a DSP controller, a first power loop, a second power loop, a first off-chip comparator, a second off-chip comparator, and a driver. An EPWM driving module, an ADC sampling module, an on-chip DC digital comparator module and a TZ trigger interrupt module are integrated in the DSP controller, a 2P2Z controller, a voltage feedforward operation unit, a current detection verification unit and a temperature protection unit are further arranged in the DSP controller, the TZ trigger interrupt module is provided with a TZ2 pin and a TZ3 pin, and the EPWM driving module is provided with a first comparison register CMPA, a period register TBPRD and a second comparison register CMPB. The first power loop and the second power loop form a single-phase and two-phase staggered Boost topology, and the two Boost circuits are staggered and connected in parallel at a 180-degree initial phase and are jointly connected to the same PFC bus. According to the invention, the circuit design is simplified, the dynamic stability of inductive current interleaving is optimized, and the THD index of the power supply is improved.

The invention discloses a communication system of an improved parallel cascade LDPC code structure based on a single encoder, and belongs to the technical field of aviation platform laser communication. Aiming at the bottlenecks that the traditional PCGC depends on double encoders, the hardware overhead is large, the decoding delay is high and the complementarity requirement on component codes is harsh, the system adopts a single encoder architecture design: firstly, a basic verification sequence is generated through a single LDPC encoder, and differential verification constraints are constructed through interleaving and repeating operations; meanwhile, a zero syndrome and non-zero syndrome dual-check sequence design is introduced, so that the minimum distance of a code word is increased; a decoding end fuses a normalized minimum sum algorithm and a hierarchical message updating and dynamic early stop mechanism, combines channel sensing soft information construction and a self-adaptive interleaving and redundancy allocation strategy, and adapts to composite channel characteristics of an aviation platform.

A method for improving the forward error correction in serial coding in a data transmission in a vehicle allowing the physical behavior on a transmission channel to always be deterministically controlled despite a reduction in the resource requirements. Tit errors are minimal and a transmission error can be corrected efficiently. In addition, encoders used are designed with a minimum number of gates and an interleaving is implicit in the proposed method, which is based on the fact that burst errors can be corrected particularly advantageously. This interleaving makes it possible to dispense with conventional buffer memory required for explicit interleaving. In addition, user data together with correcting metadata can be encoded advantageously. It can be ensured that not only the user data is line-coded or line-encoded, but also the correction data. Also provided is a system for implementing the method.

The application discloses a magnetic tape storage adaptive interleaving method and system based on dynamic error mode detection, relates to the technical field of magnetic tape interleaving, and comprises the following steps: continuously collecting error information in a magnetic tape reading and writing process and forming a structured report; judging the received structured report according to a preset rule, dynamically calculating new interleaving parameters, and outputting a decision package containing a new interleaving depth factor and a new available track list; checking whether the parameters in the received decision package are within a preset range, and if yes, sending an instruction to a magnetic tape drive through a bottom driver interface, setting new interleaving configuration for the magnetic tape, and obtaining a success status code returned by the magnetic tape drive; and the interleaving method significantly improves the reliability and error correction efficiency of the magnetic tape storage system in a complex error environment, reduces redundancy, and improves the effective utilization rate of storage space.

The invention discloses an interaction method and device between a host application and a plug-in, equipment and a medium, which are applied to the host application and comprise the following steps: when a plug-in calling request of a user is received, loading a target plug-in corresponding to the plug-in calling request, reading an interface type on which the target plug-in depends, and sending the interface type to the host application; detecting whether a target interface corresponding to the interface type is defined in the host application or not, obtaining a detection result, obtaining an instance object corresponding to the target interface according to the detection result, and injecting the instance object into the plug-in running environment, so that the host application and the target plug-in interact through the target interface and the instance object in the plug-in running environment. The coupling degree of the codes between the host application and the target plug-in is reduced, the problems of modification limitation, difficult expansion and the like caused by close interleaving of the codes are avoided, and the interaction flexibility between the host application and the target plug-in is improved.

Disclosed is a connection device between a DMA and a DRAM, which includes a slave interface connected to the DMA of an NPU, a master interface connected to the DRAM having a plurality of slave ports, and a switch that connects the slave interface to the master interface, and the connection device receives a data read request from the DMA of the NPU and transfers the received data read request to the DRAM, receives data or a response corresponding to the received data read request from the plurality of slave ports, and rearranges the data or the response based on an order of the received data read request so as to be transferred to the DMA of the NPU.

Embodiments of this application disclose a data processing method and a data processing apparatus, so that good performance of a concatenated FEC-based solution can be achieved in a scenario with a low latency. For a concatenated FEC-based transmission solution, interleaving alignment needs to be first performed before convolutional interleaving is performed on a first data stream, to determine a boundary of each bit set in the first data stream and a boundary of each bit subset in the bit set. Further, bit subsets are sent as a granularity to each storage unit in a convolutional interleaving operation. In other words, each bit subset includes d bits, and each storage unit is configured to store d bits. The bits in each bit subset are from v symbols, and the v symbols are respectively from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

The embodiment of the invention discloses a data processing method, device and system. Specifically, firstly, p first data streams subjected to RS coding are acquired; then, first data processing including FEC coding and first interleaving is carried out on the p first data streams to obtain m second data streams, and m is an integer larger than or equal to p; further, second data processing including second interleaving, DP-16QAM symbol mapping and framing is performed on the m second data streams to obtain q first dual-polarization symbol streams, q being an integer greater than 1. Wherein the first dual-polarization symbol stream comprises a symbol stream in a first polarization direction and a symbol stream in a second polarization direction. Through the above mode, the scheme of cascade FEC coding and multi-wave transmission is adopted, and the method is suitable for a data center internal transmission scene with a transmission rate higher than 800Gbps, and has the characteristics of low power consumption and low time delay.

The invention discloses an interleaving method combining dynamic bit loading and ROBO interleaving. According to the method, sending parameters are configured at a sending end based on copy times, subcarrier granularity and a modulation loading table which are fed back by a receiving end; then frame control and frame load data are processed respectively, improved ROBO interleaving combined with Bitloading is adopted for frame load, and framing is carried out on the frame load and a preamble signal through the steps of IFFT, cyclic prefix adding and the like. And after completing signal recovery and subcarrier SNR evaluation, a receiving end dynamically determines and feeds back key parameters according to different system requirements of low feedback signaling or high transmission rate. And the sending end reconfigures and generates the data frame according to the feedback. Through deep fusion of Bitloading and ROBO interleaving and flexible parameter adaptation, transmission reliability, rate and feedback overhead are effectively considered in a complex channel environment, and efficient data transmission with a low frame error rate is realized.

The embodiment of the invention discloses a data processing method and a data processing device. Good cascade FEC scheme performance can be obtained in a scene with low time delay. For a transmission scheme adopting cascaded FEC, interleaving alignment needs to be carried out before convolutional interleaving is carried out on a first data stream, so that boundaries of bit sets in the first data stream and boundaries of bit subsets in the bit sets are determined. Furthermore, the bit subsets are sent to each storage unit of the convolution interleaving operation as granularity, namely each bit subset comprises d bits, and each storage unit is used for storing d bits. Wherein the bits in each bit subset are from v symbols, and the v symbols are from v first code words, respectively. In other words, each first code word in the v first code words takes one symbol to form a bit subset.

The convolutional interleaver included in the time interleaver and performing convolutional interleaving has: a first switch that switches the connection destination of the input of the convolutional interleaver to one end of a certain branch among multiple branches; FIFO memories provided in some of the multiple branches except for one branch, with different numbers among these some branches; a second switch that switches the connection destination of the output of the convolutional interleaver to the other end of a certain branch among multiple branches; the first and second switches switch the above connection destination when a plurality of data units equal in number to the number of codewords per frame have passed, and the switching of the connection destination is performed by sequentially repeating the multiple branches to connect the destination branches.

The invention discloses a tape storage adaptive interleaving method and system based on dynamic error pattern detection, and relates to the technical field of tape interleaving, and the method comprises the steps: continuously collecting error information in a tape read-write process, and forming a structured report; judging the received structured report according to a preset rule, dynamically calculating a new interleaving parameter, and outputting a decision packet containing a new interleaving depth factor and a new available magnetic track list; checking whether parameters in the received decision packet are within a preset range, if yes, sending an instruction to a tape driver through a bottom driver interface, setting new interleaving configuration for the tape, and obtaining a success state code returned by the tape driver; according to the interleaving method, the reliability and the error correction efficiency of the tape storage system in a complex error environment are remarkably improved, meanwhile, the redundancy is reduced, and the effective utilization rate of the storage space is improved.

The present application relates to the technical field of wireless communications, and provides an interleaving method and apparatus and a deinterleaving method and apparatus, aiming to support the interleaving of sequences having different numbers of CRC bits. The interleaving method comprises: a first communication device acquires a first bit sequence, the first bit sequence comprising A information bits and L check bits; and the first communication device interleaves the first bit sequence on the basis of a first interleaving sequence or a second interleaving sequence, wherein in the first interleaving sequence, the number of positions corresponding to information bits is A, and the number of positions corresponding to check bits is L; in the second interleaving sequence, the number of positions corresponding to information bits is Kmax, and the number of positions corresponding to check bits is L; and in a target interleaving sequence, the number of positions corresponding to information bits is Kmax, and the number of positions corresponding to check bits is Lmax. The described solution provides support for an interleaving sequence whose check bit length L is less than or equal to Lmax, and can be applied to interleaving operations in different scenarios.

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

A data processing method includes, for a concatenated FEC-based transmission solution, interleaving alignment that is first performed before convolutional interleaving is performed on a first data stream, to determine a boundary of each bit set in the first data stream and a boundary of each bit subset in the bit set. Further, bit subsets are sent as a granularity to each storage unit in a convolutional interleaving operation. Each bit subset includes d bits, and each storage unit is configured to store d bits. The bits in each bit subset are from v symbols, and the v symbols are respectively from v first codewords. One symbol is selected from each of the v first codewords to form a bit subset.

A device and related method, the device including a port, memory circuitry, and processing circuitry which is coupled to the port and to the memory circuitry. The processing circuitry receives multiple commands through the port, wherein the multiple commands are from at least two hosts using an interposer and wherein each command of the multiple commands includes a respective memory address and a respective port identification (ID). The processing circuitry segments each of the received commands into multiple segments, each segment being of a predetermined transfer size. The processing circuitry also transmits each segment of each command to a respective data structure instantiation corresponding to the port ID of the respective received command and performs data transfer for each segment of the multiple segments by accessing the memory circuitry at each respective memory address associated with each segment.

A system, method, and tool for interleaving coded bits are disclosed. A wireless transmit / receive unit (WTRU) may generate a plurality of polarity coded bits using polarity coding. The WTRU may group the plurality of polarity coded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block interleaving may include interleaving on the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits from the interleaved bits for transmission.