45 results about "Address generator" patented technology

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to operational units for use as operands. A promotion unit optionally increases date element data size by an integral power of 2 either zero filing or sign filling the additional bits. A decimation unit optionally decimates data elements by an integral factor of 2. For ease of implementation the promotion factor must be greater than or equal to the decimation factor.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

This invention relates to the field of blockchain technology and discloses a Merkle tree hardware acceleration system for blockchain data verification. The system includes a control module for coordinating and controlling various modules; an address generator for generating addresses of sibling and parent nodes in the Merkle tree based on the indices of the input leaf nodes; a storage unit for storing the leaf, internal, and root node data of the Merkle tree; a computation module for performing data concatenation, hashing, and comparison on the Merkle tree nodes based on the addresses provided by the address generator, and generating intermediate and verification results; and a buffer for temporarily storing node data read from the storage unit and intermediate results output by the computation module. This invention designs a hardware acceleration architecture tailored to the structural characteristics of Merkle trees, improving the computational efficiency of blockchain data verification, achieving low-power operation, and is suitable for the performance requirements of various blockchain application scenarios.

The invention discloses a dynamic reconfigurable chip configuration management structure oriented to data cycle processing. Automatic cycle configuration of a plurality of configuration indexes is supported. The configuration index can be operated according to a certain sequence rule in each cycle process; an end signal of the address generator integrated in the structure is used as a trigger signal of the next configuration, so that the automation of the configuration is realized; automatic link configuration among a plurality of configuration indexes is supported, and any specified configuration index can be automatically started after the current configuration index is executed. The method is suitable for the dynamic reconfigurable chip, especially for the dynamic reconfigurable chip in the field of data encryption and decryption and graphic image processing, and by means of the design, the function configuration time can be shortened, the complexity of function configuration management can be reduced, and the overall performance of the dynamic reconfigurable chip can be improved.

The invention relates to a built-in self-test system and method for an MTP memory, belongs to the technical field of chip testing, and solves the problems that the existing built-in self-test function is single and cannot be applied to different memory areas at the same time. The address generator is used for generating an address signal; the mode generator is used for obtaining a test operation signal according to the area selection signal, the mode selection signal and the test sequence selection signal, starting the mode state machine and entering a corresponding test state; the signal generator is used for starting the signal state machine and entering a corresponding signal state according to the test state signal and the preset time of the time sequence counter; the MTP memory is used for starting testing according to the address signals, the test operation signal and the signal state, acquiring test data of each address signal and returning the test data to the comparator; and the comparator is used for comparing the test data of each address signal with the received address signal and the test operation signal, and feeding back a comparison result to the mode generator. And various and flexible built-in self-testing is realized.

A method for refreshing a memory element, comprising: - generating a refresh address with a refresh period, - performing each refresh at a weak cell with a first address when the refresh address is a second address, instead of a first strong cell with the second address, and - performing each refresh at a first strong cell or a second strong cell with a third address when the refresh address is the third address, - wherein address information is stored for only one of the first, second, and third addresses, and / or wherein the third address is selected from a pool of addresses with a range defined by at least two least significant bits of one of the first and second addresses.

A system includes a first coarse-grained reconfigurable (CGR) processor including first and second CGR arrays. A second CGR processor includes third and fourth CGR arrays. Each CGR array includes an address generator and coalescing unit (AGCU) designated as an array master AGCU (AMAGCU). The first CGR array AGCU is also designated as a processor master AGCU (PMAGCU) and as a system master (SMAGCU). The third CGR array AGCU is also designated as a PMAGCU. Each AMAGCU performs first execution synchronization actions, each PMAGCU also performs second execution synchronization actions, and the SMAGCU also performs third execution synchronization actions. The execution synchronization actions include a token exchange protocol for tokens such as “array ready”, “processor ready”, “system master ready”, “program start”, “array done, “processor done”, and “program terminate”. The tokens are communicated over a token bus via token interfaces that include a bus interface and a token receive FIFO.

A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and / or may be used with a streaming address generator.

The invention relates to a stream engine with selectable multi-dimensional loop addressing in each dimension. A stream engine (125, 2700) for use in a digital data processor specifies a fixed read-only data stream defined by a plurality of nested loops. An address generator (1901) generates addresses of data elements of the nested loops. A stream head register (2718, 2728) stores a data element to be provided next to a functional unit for use as an operand. A stream template register (2800) independently specifies a linear address or a loop address pattern for each of the nested loops.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Upon a stream break instruction specifying one of the nested loops, the stream engine ends a current iteration of the loop. If the specified loop was not the outermost loop, the streaming engine begins an iteration of a next outer loop. If the specified loop was the outermost nested loop, the streaming engine ends the stream. The streaming engine places a vector of data elements in order in lanes within a stream head register. A stream break instruction is operable upon a vector break.

The present application discloses a stream engine that uses early and late address and loop count registers to track architectural state. A stream engine (125, 200) for use in a digital data processor (100) specifies a fixed, read-only data stream defined by multiple nested loops. An address generator (1901) generates addresses for data elements. A stream head register (2718, 2728) stores the data element to be provided next to a functional unit for use as an operand. The stream engine (125, 2700) stores, for each of the nested loops, an early address of the data element to be retrieved next and a late address of the data element in the stream head register (2718, 2728). The stream engine (125, 2700) stores, for each of the nested loops, an early loop count (3701-3704) of the data element to be retrieved next and a late loop count (3705-3708) of the data element in the stream head register (2718, 2728).

The application discloses an annealing method-based dynamic reconfigurable convolutional neural network accelerator and a parameter optimization method thereof, and the accelerator comprises a data buffer, a controller, an address generator, a convolution calculation engine and a dimension rearrangement module; the data buffer is used for buffering input and weight data of the convolutional neural network read from outside the chip; the controller controls input of input data and weight data of different addresses to the convolution calculation engine; the convolution calculation engine carries out convolution calculation on different convolution layers according to a parallel calculation mode and a corresponding parallel degree value pair obtained by the parameter optimization method based on the annealing method; if the parallel calculation mode of the next convolution layer changes, the result data of the current convolution layer is rearranged and stored to the data buffer, otherwise, the result data is directly stored to the data buffer. The application can improve resource utilization, calculation efficiency and throughput of the accelerator and reduce the delay.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.

A memory test circuit in a circuit is configured to perform a test on one or more memories in the circuit, each of the one or more memories having a plurality of logical ports. The memory test circuit includes: a test algorithm control unit configured to implement a test algorithm; a reference address generator configured to generate a reference address based on the test algorithm; one or more concurrent address generators configured to generate one or more concurrent addresses based on the reference address; and an address selection circuit for each of the one or more memories configured to select one of the one or more concurrent addresses or the reference address for each of the plurality of logical ports based on an address selection signal. One logical port is configured to receive an algorithm command and the reference address, while the other logical ports are configured to receive a concurrent command and the concurrent address.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.

The application provides a reading system and method. A register unit stores a fault address of a faulty storage unit. A comparison unit compares the fault address of the faulty storage unit stored in the register unit with a read operation address generated by a controller, generates a comparison result, and when the comparison result indicates that the read operation address is consistent with the fault address, sends the comparison result to a redundant address generator, so that the redundant address generator generates a redundant address and sends the redundant address to the controller, so that the controller reads a corresponding storage unit according to the redundant address. In this way, by comparing the read operation address with the fault address stored in the register, it is determined whether the storage unit corresponding to the read operation address can be read, and when the storage unit corresponding to the read operation address cannot be read, the read operation address is replaced by the redundant address, so that the controller can obtain data in time and improve the reading efficiency.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Upon a stream break instruction specifying one of the nested loops, the stream engine ends a current iteration of the loop. If the specified loop was not the outermost loop, the streaming engine begins an iteration of a next outer loop. If the specified loop was the outermost nested loop, the streaming engine ends the stream. The streaming engine places a vector of data elements in order in lanes within a stream head register. A stream break instruction is operable upon a vector break.

The invention relates to the technical field of channel coding, particularly discloses a data replacement method based on a Banyan network in LDPC T1 coding and an encoder, and aims to solve the problems that in the prior art, a data replacement method based on an address generator is large in resource consumption, complex in wiring and difficult to support high parallelism and high throughput. The method comprises the following steps: reading a pre-stored Banoan network coefficient according to a code rate and a non-zero element position of a check matrix, and setting a Banoan network to finish offset jump of 512-bit parallel information to be replaced. The encoder correspondingly comprises a replacement module, a summing circuit and an accumulation module for realizing the method. According to the method, the non-blocking rearrangement characteristic of the Banoan network under the T1 code standard is utilized, 255 replacement modes of three code rates of the LDPC T1 code are supported through a unified hardware structure, the maximum 512-path parallel is achieved, meanwhile, the resource consumption of a lookup table and a register is remarkably reduced, and the working frequency and the coding throughput are improved through the multi-stage assembly line design.

The invention discloses a post quantum cryptography data processing optimization system based on a double register block architecture. The system comprises two independently arranged register blocks, an address generator, a multiplexer, a butterfly unit and a control unit, wherein the two independently arranged register groups comprise a register group I and a register group II, and the register group I and the register group II are used for respectively storing input data and output data of each round of data processing; the address generator is used for extracting to-be-processed data from the register group I according to the step length and transmitting the to-be-processed data to the butterfly unit; the butterfly unit is used for carrying out data optimization processing on the data transmitted by the address generator by selecting a corresponding data processing mode based on the multiplexer; the control unit is used for sending a mode selection signal to the multiplexer according to a preset execution program; and the multiplexer is used for controlling the butterfly unit to execute a corresponding data processing mode according to the mode selection signal sent by the control unit.

A computer-implemented method of generating a network address of a network, wherein the method is performed by an address generator and comprises: generating a signature based on a subnet prefix; generating an interface identifier, where the interface identifier is based on a hash value, where the hash value is based on a hash of at least the signature and a conflict count value; and generating the network address based on the subnet prefix and the interface identifier.

The invention discloses an address scanning method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring address generation scales respectively corresponding to a plurality of address areas of a current round, and respectively inputting prefixes of the plurality of address areas into an address generator based on the address generation scales respectively corresponding to the plurality of address areas of the current round to obtain address candidate sets respectively corresponding to the prefixes of the plurality of address areas of the current round; inputting the address candidate sets respectively corresponding to the prefixes of the plurality of address areas in the current round into a scanner to obtain survival rates respectively corresponding to the plurality of address areas in the current round, and determining address generation scales respectively corresponding to the plurality of address areas in the next round based on the survival rates respectively corresponding to the plurality of address areas in the current round; and generating an address and a scanning address based on the address generation scale corresponding to the multiple address areas in the next round, and stopping generating the address and the scanning address until a scanning stop condition is met to obtain a target scanning result. According to the technical scheme, the address scanning benefit is improved.

A computer-implemented method of generating a network address of a network, where the method is performed by an address generator and comprises: generating an interface identifier, where the interface identifier is based on a hash value, where the hash value is based on a hash of at least a modifier value, a subnet prefix, a conflict count value, and a public key; generating a network address based on the subnet prefix and the interface identifier; and generating a signature based on the network address, wherein the private key for generating the signature corresponds to the public key.

A differential matching prefetcher for coping with irregular memory access includes: an access index table, an access target table, a differential matching module, an index queue, an indirect memory access candidate scoreboard, an address generator, an indirect memory access relationship table, a prefetch status handling register, a repetition filter, a continuous address filter, and a range prefetch table. The differential matching prefetcher is configured to monitor events of access requests and data responses between a computing core and a first level of cache, as well as between the first level of cache and a second level of cache. The differential matching prefetcher may be applied in various general-purpose computing architectures adopting a hierarchical storage design to realize mode capture and data prefetch for irregular indirect memory access, reduce long-delay storage access overhead caused by the irregular memory access, and increase instructions per cycle (IPC) of the computing architectures.

A memory interface circuit includes a request decoder configured to receive a command signal and an address signal. The request decoder is configured to decode the command signal and the address signal to generate a data count signal and a start address signal. A burst counter is coupled to the request decoder, and the burst counter is configured to update the data count signal after each access of a memory. An address generator is coupled to the request decoder. The address generator is configured to receive the start address signal and generate a subsequent memory address signal based on the start address signal after each access of the memory.

Apparatuses, systems, and methods for managing storage and retrieval of metadata at a memory. A metadata column address generator, during a metadata access operation, is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of column planes of a memory array. A column decoder is configured to facilitate a double cycle access operation to write data to or retrieve data from the plurality of column planes based on the column address and to write metadata to or retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the column planes corresponding to the column plane address.

The present disclosure relates to the technical field of semiconductor, and relates to a refresh address generation circuit and method, a memory, and an electronic device. The refresh address generation circuit comprises a refresh control circuit and an address generator. The refresh control circuit is configured to sequentially receive a plurality of first refresh instructions and perform first refresh operations respectively, output a first clock signal when the number of the first refresh operations is less than a preset number value, and output a second clock signal when the number of the first refresh operations is equal to the preset number value n, wherein n is a positive integer greater than or equal to 1. The address generator is coupled to the refresh control circuit, and prestores a first address and receives the first clock signal or the second clock signal. During each first refresh operation, the address generator outputs a first address to be refreshed in response to the first clock signal, and the first address to be refreshed comprises the first address. In response to the second clock signal, the address generator changes the first address. The refresh address generation circuit can provide refresh addresses for refreshing the same memory block.

The invention discloses an address generation circuit, a data access device, an address generation method and a medium. The address generation circuit comprises a register used for registering data access configuration information; the address generator is used for determining sub-configuration information respectively corresponding to a plurality of holes distributed to the data to be accessed in the memory based on the data access configuration information acquired from the register; based on the data access configuration information, determining first reference physical addresses of a plurality of sub-data in the to-be-accessed data in a memory; and based on the sub-configuration information corresponding to the plurality of holes, mapping first reference physical addresses corresponding to the plurality of pieces of sub-data to the plurality of holes to obtain target physical addresses corresponding to the plurality of pieces of sub-data. According to the embodiment of the invention, successful writing of the to-be-accessed data can be realized through a fragmented storage scheme.

Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

The embodiment of the present application discloses a refresh address generation circuit, comprising: a refresh control circuit and an address generator. Wherein, the refresh control circuit sequentially receives a plurality of first refresh instructions and correspondingly performs a plurality of first refresh operations, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operations is equal to m, m is an integer greater than or equal to 1. The address generator is coupled to the refresh control circuit, used for pre-storing a first address, receiving the first clock signal or the second clock signal, outputting a to-be-refreshed address during each first refresh operation in response to the first clock signal, and changing the first address in response to the second clock signal. The to-be-refreshed address comprises the first address or a second address, and the least significant bit of the second address is opposite to the least significant bit of the first address. The present application can ensure that the refresh operation is carried out without omission, and the integrity of the address is maintained.