69 results about "Address generator" patented technology

A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.

A differential matching prefetcher for coping with irregular memory access includes: an access index table, an access target table, a differential matching module, an index queue, an indirect memory access candidate scoreboard, an address generator, an indirect memory access relationship table, a prefetch status handling register, a repetition filter, a continuous address filter, and a range prefetch table. The differential matching prefetcher is configured to monitor events of access requests and data responses between a computing core and a first level of cache, as well as between the first level of cache and a second level of cache. The differential matching prefetcher may be applied in various general-purpose computing architectures adopting a hierarchical storage design to realize mode capture and data prefetch for irregular indirect memory access, reduce long-delay storage access overhead caused by the irregular memory access, and increase instructions per cycle (IPC) of the computing architectures.

A refresh address generation circuit includes: a refresh control circuit configured to sequentially receive first refresh commands and perform first refresh operations respectively, output a first clock signal when the number of the first refresh operations is less than a preset value or output a second clock signal when the number of the first refresh operations is equal to the preset value n, where n is a positive integer greater than or equal to 1; an address generator coupled to refresh control circuit, pre-storing a first address, receiving the first clock signal or the second clock signal, outputting a first to-be-refreshed address in response to the first clock signal during each first refresh operation, the first to-be-refreshed address includes the first address, and changing the first address in response to the second clock signal.

The embodiment of the invention discloses a dynamic-length large model compiling method and device. The method comprises the steps that a trained large model is split into a set of a plurality of operators in a preset mode; each operator comprises a plurality of micro operators; dynamic length is used as input for operators in the large model, compiling of dynamic operators is achieved, and the compiled operators are spliced according to a network structure to achieve compiling of the model; the dynamic length is the length corresponding to each operator; the runtime support comprises globally adjusting the configuration of a model operator according to the received dynamic length of the reasoning during the model reasoning, and then executing the reasoning; the operator configuration is obtained by configuring an address generator and an instruction configuration register in the AI chip; the method has the beneficial effects that the remainder micro-operator generated by each operator is configured according to the dynamic length during operation, so that flexible and efficient dynamic length large model compiling can be realized by only needing a small amount of hardware support.

According to the NTT calculation system, method and device applied to the lattice-based anti-quantum cryptography algorithm, parallel calculation is carried out on each polynomial coefficient obtained from a register through storage bit mapping addresses of each polynomial coefficient sent by an address generator by using butterfly operation units which are integer multiples of 2 at the same time, and a calculation result is obtained. The invention provides a high-performance NTT computing architecture combining parallel computing of butterfly computing units with the number of integer multiples of 2 and an address generator, and the high-performance NTT computing architecture can further accelerate multiplication among polynomials, so that the operation of a lattice-based anti-quantum cryptography algorithm is accelerated, and the NTT operation rate is improved; and the scene of performing higher-speed encryption and decryption on the data is met.

A memory device, an operating method thereof and an electronic device are provided. The memory device includes a memory array, an address generator, a data register, and a processing unit. The address generator is configured to receive an instruction and a base address of the instruction from a host, and sequentially generate a target address for performing an operation of the instruction by sequentially adding an offset to the base address. The data register is configured to store data values corresponding to one or more of the target addresses. The processing unit is configured to perform one or more of the operations of the instruction based on the data value.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to operational units for use as operands. A promotion unit optionally increases date element data size by an integral power of 2 either zero filing or sign filling the additional bits. A decimation unit optionally decimates data elements by an integral factor of 2. For ease of implementation the promotion factor must be greater than or equal to the decimation factor.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.

This invention relates to the field of blockchain technology and discloses a Merkle tree hardware acceleration system for blockchain data verification. The system includes a control module for coordinating and controlling various modules; an address generator for generating addresses of sibling and parent nodes in the Merkle tree based on the indices of the input leaf nodes; a storage unit for storing the leaf, internal, and root node data of the Merkle tree; a computation module for performing data concatenation, hashing, and comparison on the Merkle tree nodes based on the addresses provided by the address generator, and generating intermediate and verification results; and a buffer for temporarily storing node data read from the storage unit and intermediate results output by the computation module. This invention designs a hardware acceleration architecture tailored to the structural characteristics of Merkle trees, improving the computational efficiency of blockchain data verification, achieving low-power operation, and is suitable for the performance requirements of various blockchain application scenarios.

A semiconductor memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer handler configured to generate a refresh address when performing a refresh operation on the plurality rows of memory cells. The row hammer handler (RHH) includes a weight distributor configured to: receive a plurality of row addresses, assign a weight to each of the plurality of row addresses thus received, and to generate weight data corresponding to each of the plurality of row addresses. The RHH also includes an aggress address generator configured to determine an aggress address of a row of memory cells based on the weight data, and a refresh address generator configured to receive the aggress address and to generate the refresh address, which includes address information of a memory cell row adjacent the aggress address.

A storage device includes an address generator that generates a first physical address and a second physical address different from the first physical address. A first nonvolatile memory includes the first physical address, and a second nonvolatile memory includes the second physical address. An attack detection circuit detects whether the first nonvolatile memory and the second nonvolatile memory are under attack. The attack detection circuit receives first data from the first nonvolatile memory and second data from the second nonvolatile memory, compares the first data and the second data, and determines whether the first nonvolatile memory and the second nonvolatile memory are under attack based on the comparison result of the first and second data.

The invention discloses a dynamic reconfigurable chip configuration management structure oriented to data cycle processing. Automatic cycle configuration of a plurality of configuration indexes is supported. The configuration index can be operated according to a certain sequence rule in each cycle process; an end signal of the address generator integrated in the structure is used as a trigger signal of the next configuration, so that the automation of the configuration is realized; automatic link configuration among a plurality of configuration indexes is supported, and any specified configuration index can be automatically started after the current configuration index is executed. The method is suitable for the dynamic reconfigurable chip, especially for the dynamic reconfigurable chip in the field of data encryption and decryption and graphic image processing, and by means of the design, the function configuration time can be shortened, the complexity of function configuration management can be reduced, and the overall performance of the dynamic reconfigurable chip can be improved.

The invention relates to a built-in self-test system and method for an MTP memory, belongs to the technical field of chip testing, and solves the problems that the existing built-in self-test function is single and cannot be applied to different memory areas at the same time. The address generator is used for generating an address signal; the mode generator is used for obtaining a test operation signal according to the area selection signal, the mode selection signal and the test sequence selection signal, starting the mode state machine and entering a corresponding test state; the signal generator is used for starting the signal state machine and entering a corresponding signal state according to the test state signal and the preset time of the time sequence counter; the MTP memory is used for starting testing according to the address signals, the test operation signal and the signal state, acquiring test data of each address signal and returning the test data to the comparator; and the comparator is used for comparing the test data of each address signal with the received address signal and the test operation signal, and feeding back a comparison result to the mode generator. And various and flexible built-in self-testing is realized.

A method for refreshing a memory element, comprising: - generating a refresh address with a refresh period, - performing each refresh at a weak cell with a first address when the refresh address is a second address, instead of a first strong cell with the second address, and - performing each refresh at a first strong cell or a second strong cell with a third address when the refresh address is the third address, - wherein address information is stored for only one of the first, second, and third addresses, and / or wherein the third address is selected from a pool of addresses with a range defined by at least two least significant bits of one of the first and second addresses.

A system includes a first coarse-grained reconfigurable (CGR) processor including first and second CGR arrays. A second CGR processor includes third and fourth CGR arrays. Each CGR array includes an address generator and coalescing unit (AGCU) designated as an array master AGCU (AMAGCU). The first CGR array AGCU is also designated as a processor master AGCU (PMAGCU) and as a system master (SMAGCU). The third CGR array AGCU is also designated as a PMAGCU. Each AMAGCU performs first execution synchronization actions, each PMAGCU also performs second execution synchronization actions, and the SMAGCU also performs third execution synchronization actions. The execution synchronization actions include a token exchange protocol for tokens such as “array ready”, “processor ready”, “system master ready”, “program start”, “array done, “processor done”, and “program terminate”. The tokens are communicated over a token bus via token interfaces that include a bus interface and a token receive FIFO.

A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and / or may be used with a streaming address generator.

The invention relates to a stream engine with selectable multi-dimensional loop addressing in each dimension. A stream engine (125, 2700) for use in a digital data processor specifies a fixed read-only data stream defined by a plurality of nested loops. An address generator (1901) generates addresses of data elements of the nested loops. A stream head register (2718, 2728) stores a data element to be provided next to a functional unit for use as an operand. A stream template register (2800) independently specifies a linear address or a loop address pattern for each of the nested loops.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Upon a stream break instruction specifying one of the nested loops, the stream engine ends a current iteration of the loop. If the specified loop was not the outermost loop, the streaming engine begins an iteration of a next outer loop. If the specified loop was the outermost nested loop, the streaming engine ends the stream. The streaming engine places a vector of data elements in order in lanes within a stream head register. A stream break instruction is operable upon a vector break.

The present application discloses a stream engine that uses early and late address and loop count registers to track architectural state. A stream engine (125, 200) for use in a digital data processor (100) specifies a fixed, read-only data stream defined by multiple nested loops. An address generator (1901) generates addresses for data elements. A stream head register (2718, 2728) stores the data element to be provided next to a functional unit for use as an operand. The stream engine (125, 2700) stores, for each of the nested loops, an early address of the data element to be retrieved next and a late address of the data element in the stream head register (2718, 2728). The stream engine (125, 2700) stores, for each of the nested loops, an early loop count (3701-3704) of the data element to be retrieved next and a late loop count (3705-3708) of the data element in the stream head register (2718, 2728).

The present disclosure discloses a templatized memory pattern generator and a method. The templatized memory pattern generator includes a test processor, a simple memory pattern generator, a channel timing & formatter, and a pin electronic. The simple memory pattern generator includes an X address generator, a Y address generator, a D data generator, a SMPG and channel mapping. An input terminal of the channel timing & formatter is connected to the SMPG and channel mapping; an output terminal of the channel timing & formatter is connected to the pin electronic; and parallel data calculated by the simple memory pattern generator based on an SMPG resource mapping table provided by an upper computer is mapped to pins of a device under test one by one. The present disclosure can effectively reduce a quantity of test vectors in an image file. Meanwhile, after modulation, the scheme can improve the reusability of a test program and reduce the development period of the test scheme.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

The application discloses an annealing method-based dynamic reconfigurable convolutional neural network accelerator and a parameter optimization method thereof, and the accelerator comprises a data buffer, a controller, an address generator, a convolution calculation engine and a dimension rearrangement module; the data buffer is used for buffering input and weight data of the convolutional neural network read from outside the chip; the controller controls input of input data and weight data of different addresses to the convolution calculation engine; the convolution calculation engine carries out convolution calculation on different convolution layers according to a parallel calculation mode and a corresponding parallel degree value pair obtained by the parameter optimization method based on the annealing method; if the parallel calculation mode of the next convolution layer changes, the result data of the current convolution layer is rearranged and stored to the data buffer, otherwise, the result data is directly stored to the data buffer. The application can improve resource utilization, calculation efficiency and throughput of the accelerator and reduce the delay.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

A memory device includes a memory array, an address generator, a data register, and a processing unit. The address generator is configured to receive an instruction and a base address of the instruction from a host, and sequentially generate target addresses for performing operations of the instruction by sequentially adding offsets to the base address. The data register is configured to store data values corresponding to one or more of the target addresses. The processing unit is configured to perform one or more of the operations of the instruction based on the data values.

A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.

A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.

A memory test circuit in a circuit is configured to perform a test on one or more memories in the circuit, each of the one or more memories having a plurality of logical ports. The memory test circuit includes: a test algorithm control unit configured to implement a test algorithm; a reference address generator configured to generate a reference address based on the test algorithm; one or more concurrent address generators configured to generate one or more concurrent addresses based on the reference address; and an address selection circuit for each of the one or more memories configured to select one of the one or more concurrent addresses or the reference address for each of the plurality of logical ports based on an address selection signal. One logical port is configured to receive an algorithm command and the reference address, while the other logical ports are configured to receive a concurrent command and the concurrent address.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.

The application provides a reading system and method. A register unit stores a fault address of a faulty storage unit. A comparison unit compares the fault address of the faulty storage unit stored in the register unit with a read operation address generated by a controller, generates a comparison result, and when the comparison result indicates that the read operation address is consistent with the fault address, sends the comparison result to a redundant address generator, so that the redundant address generator generates a redundant address and sends the redundant address to the controller, so that the controller reads a corresponding storage unit according to the redundant address. In this way, by comparing the read operation address with the fault address stored in the register, it is determined whether the storage unit corresponding to the read operation address can be read, and when the storage unit corresponding to the read operation address cannot be read, the read operation address is replaced by the redundant address, so that the controller can obtain data in time and improve the reading efficiency.