16 results about "Address generator" patented technology

This invention relates to the field of blockchain technology and discloses a Merkle tree hardware acceleration system for blockchain data verification. The system includes a control module for coordinating and controlling various modules; an address generator for generating addresses of sibling and parent nodes in the Merkle tree based on the indices of the input leaf nodes; a storage unit for storing the leaf, internal, and root node data of the Merkle tree; a computation module for performing data concatenation, hashing, and comparison on the Merkle tree nodes based on the addresses provided by the address generator, and generating intermediate and verification results; and a buffer for temporarily storing node data read from the storage unit and intermediate results output by the computation module. This invention designs a hardware acceleration architecture tailored to the structural characteristics of Merkle trees, improving the computational efficiency of blockchain data verification, achieving low-power operation, and is suitable for the performance requirements of various blockchain application scenarios.

A method for refreshing a memory element, comprising: - generating a refresh address with a refresh period, - performing each refresh at a weak cell with a first address when the refresh address is a second address, instead of a first strong cell with the second address, and - performing each refresh at a first strong cell or a second strong cell with a third address when the refresh address is the third address, - wherein address information is stored for only one of the first, second, and third addresses, and / or wherein the third address is selected from a pool of addresses with a range defined by at least two least significant bits of one of the first and second addresses.

The invention relates to a stream engine with selectable multi-dimensional loop addressing in each dimension. A stream engine (125, 2700) for use in a digital data processor specifies a fixed read-only data stream defined by a plurality of nested loops. An address generator (1901) generates addresses of data elements of the nested loops. A stream head register (2718, 2728) stores a data element to be provided next to a functional unit for use as an operand. A stream template register (2800) independently specifies a linear address or a loop address pattern for each of the nested loops.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Upon a stream break instruction specifying one of the nested loops, the stream engine ends a current iteration of the loop. If the specified loop was not the outermost loop, the streaming engine begins an iteration of a next outer loop. If the specified loop was the outermost nested loop, the streaming engine ends the stream. The streaming engine places a vector of data elements in order in lanes within a stream head register. A stream break instruction is operable upon a vector break.

The invention relates to the technical field of channel coding, particularly discloses a data replacement method based on a Banyan network in LDPC T1 coding and an encoder, and aims to solve the problems that in the prior art, a data replacement method based on an address generator is large in resource consumption, complex in wiring and difficult to support high parallelism and high throughput. The method comprises the following steps: reading a pre-stored Banoan network coefficient according to a code rate and a non-zero element position of a check matrix, and setting a Banoan network to finish offset jump of 512-bit parallel information to be replaced. The encoder correspondingly comprises a replacement module, a summing circuit and an accumulation module for realizing the method. According to the method, the non-blocking rearrangement characteristic of the Banoan network under the T1 code standard is utilized, 255 replacement modes of three code rates of the LDPC T1 code are supported through a unified hardware structure, the maximum 512-path parallel is achieved, meanwhile, the resource consumption of a lookup table and a register is remarkably reduced, and the working frequency and the coding throughput are improved through the multi-stage assembly line design.

The present disclosure relates to the technical field of semiconductor, and relates to a refresh address generation circuit and method, a memory, and an electronic device. The refresh address generation circuit comprises a refresh control circuit and an address generator. The refresh control circuit is configured to sequentially receive a plurality of first refresh instructions and perform first refresh operations respectively, output a first clock signal when the number of the first refresh operations is less than a preset number value, and output a second clock signal when the number of the first refresh operations is equal to the preset number value n, wherein n is a positive integer greater than or equal to 1. The address generator is coupled to the refresh control circuit, and prestores a first address and receives the first clock signal or the second clock signal. During each first refresh operation, the address generator outputs a first address to be refreshed in response to the first clock signal, and the first address to be refreshed comprises the first address. In response to the second clock signal, the address generator changes the first address. The refresh address generation circuit can provide refresh addresses for refreshing the same memory block.

The invention discloses an address generation circuit, a data access device, an address generation method and a medium. The address generation circuit comprises a register used for registering data access configuration information; the address generator is used for determining sub-configuration information respectively corresponding to a plurality of holes distributed to the data to be accessed in the memory based on the data access configuration information acquired from the register; based on the data access configuration information, determining first reference physical addresses of a plurality of sub-data in the to-be-accessed data in a memory; and based on the sub-configuration information corresponding to the plurality of holes, mapping first reference physical addresses corresponding to the plurality of pieces of sub-data to the plurality of holes to obtain target physical addresses corresponding to the plurality of pieces of sub-data. According to the embodiment of the invention, successful writing of the to-be-accessed data can be realized through a fragmented storage scheme.

Techniques described herein provide memory redundancy. For example, the memory block for each pixel can be partitioned into multiple memory bins, and the number of memory bins can be larger than the number of time bins. Once a faulty memory cell is identified, an address associated with the memory bin that has the faulty memory cell can be skipped by an address generator. As such, the faulty memory cell is not used to store time-of-fight (ToF) information.

This invention discloses a method for processing matrix multiplication weight data in model inference, adapted to large-scale matrix multiplication in BFP format for large models in the Transformer architecture. Addressing the pain points of existing architectures regarding BFP exponent and mantissa splitting, bandwidth, and resource consumption, this method employs (64,64) weight blocks, dual address generator 1:4 scheduling, waterline flow control, and double buffering techniques to achieve full-bandwidth read / write between DDR, BRAM, and computational units. Through multi-core parallelism and multi-round multiplication and accumulation, performance is improved by more than 3 times compared to FP16, reducing memory usage and design complexity while ensuring inference accuracy, providing an efficient hardware acceleration solution for LLM inference in resource-constrained environments.

The application relates to the technical field of image processing, and discloses a pixel sampling device, a pixel sampling method and an image compression system. The device comprises a first address generator, a prediction adjustment unit, a private cache unit and a downsampling unit. The first address generator is used for initiating a read request to a target image in an external memory according to a preset initial address and a termination address. The read request is used for reading all target data blocks of the target image. The private cache unit is used for caching high-frequency data blocks and corresponding pixel frequency information in a historical image and a prediction period value. The prediction adjustment unit is used for predicting whether a current target data block is the same as the high-frequency data blocks in the private cache unit according to a current prediction period value, and determining the target data block or the high-frequency data blocks as a to-be-converted data block according to a prediction result. The prediction period value is determined based on a prediction result of predicting a previous target data block. The downsampling unit is used for performing color space conversion and chroma information downsampling on the to-be-converted data block to obtain a result data block. Based on the device, a hardware sampling process of image compression can be realized, the occupation of system resources is reduced, and the image compression efficiency can be improved.

The invention provides a memory testing device and method, a processing chip and a computer readable storage medium, and the testing device comprises an address generator which generates address information of a to-be-tested unit in a memory; a data generator that generates data for testing by using a data generation mode selected from two or more data generation modes; the system controller is used for controlling the testing device to write data into the memory according to the address information and read the data from the memory according to the address information; and a data verifier that compares the read data with expected return data to generate a test result. Therefore, on one hand, the test device supports more than two data generation modes, and the completeness and robustness of a test scheme are improved by enhancing the flexibility of the data generation modes and the diversity of test data; and on the other hand, the test of read and write operations is carried out on the memory, and the association test of the memory and a transmission link is realized.

Sequences to synchronize devices and related methods are disclosed herein including an access address generator to cryptographically generate a first bit sequence, an access address selector to read a first portion of the first bit sequence and read a second portion of the first bit sequence, the second portion different than the first portion, an access address analyzer to identify a first access address from a first section of the first portion based on a first criteria, the first criteria a function of a first autocorrelation function and identify a second access address from a second section of the second portion based on a second criteria, the second criteria a function of a second autocorrelation function.

This invention discloses a low-instruction-overhead, reconfigurable normalization operator implementation method based on SIMD vector processing, relating to deep learning algorithm model technology and electronic information technology. The invention first divides the normalization operator into reduction and scalar operations, compiles the operations into a fixed sequence of M microcodes, preloads them into a microcode sequence memory, and configures a SIMD vector processing unit consisting of an instruction decoding unit, a hardware autonomous execution engine, and a memory access address generator. It continuously performs sequence length token and channel group scanning, performing P×N iterations on P groups of channels and N tokens, physically reusing the microcode sequence. The microcode pointer is automatically reset to zero, and intermediate result fusion is adaptively completed by scalar microcode operator encoding. Compared with existing GPU solutions, this method has better reconfigurability, lower execution cycle, and lower instruction overhead.

Sequences to synchronize devices and related methods are disclosed herein including an access address generator to cryptographically generate a first bit sequence, an access address selector to read a first portion of the first bit sequence and read a second portion of the first bit sequence, the second portion different than the first portion, an access address analyzer to identify a first access address from a first section of the first portion based on a first criteria, the first criteria a function of a first autocorrelation function and identify a second access address from a second section of the second portion based on a second criteria, the second criteria a function of a second autocorrelation function.

This invention relates to an anonymous and oversightable cross-chain privacy protection method based on zero-knowledge proofs, belonging to the field of network security technology. First, cross-chain smart contracts and virtual address generator contracts are deployed on the main chain and side chains, connected via a cross-chain relay network. Then, the transaction initiator uses the cross-chain contract on the relay chain to call the cross-chain contracts of both transaction chains to generate an anonymous transaction. Finally, a zero-knowledge proof algorithm calculates the proof information, packages it together with the transaction, and sends it to the recipient and the relay chain, completing the transaction. This invention protects user privacy information, enables oversightable transaction traceability, and facilitates secure and efficient cross-chain transactions, improving the security of blockchain cross-chain communication in a zero-trust environment.