668 results about "Address generator" patented technology

Provided is a communication device which securely registers a slave unit. A secret address generation and setup section generates a secret address generator, and a secret address of the slave unit used temporarily instead of a unique address of the slave unit based on the secret address generator and identification information of the slave unit. A second communication section transmits to the slave unit a registration start notice containing the secret address generator by broadcast. A registration process section generates a registration authentication key; generates a unique key of the slave unit by transmitting/receiving, to/from the slave unit, unique key generation information encrypted using the registration authentication key; receives, from the slave unit, the unique address of the slave unit encrypted using the registration authentication key; and stores the identification information in association with the unique address and the unique key of the slave unit in the registration information storing section.

A data processing apparatus maps input symbols to be communicated onto a predetermined number of carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM carrier signals. The interleaver memory reads-out the data symbols on to the OFDM carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. In order to provide a 4 k mode for an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial (DVB-T) or DVB-Handheld (DVB-H) standards, a generator polynomial for the linear feedback shift register of Ri'[10]=Ri-1'[0]⊕Ri-1'[2] is provided with a permutation order which has been established by simulation analysis to optimise communication performance via typical radio channels.

A data packet classifier to classify a plurality of N-bit input tuples, said classifier comprising a hash address, a memory and a comparison unit. The hash address generator generate a plurality of M-bit hash addresses from said plurality of N-bit input tuples, wherein M is significantly smaller than N. The memory has a plurality of memory entries and is addressable by said plurality of M-bit hash addresses, each such address corresponding to a plurality of memory entries, each of said plurality of memory entries capable of storing one of said plurality of N-bit tuples and an associated process flow information. The comparison unit determines if an incoming N-bit tuple can be matched with a stored N-bit tuple. The associated process flow information is output if a match is found and wherein a new entry is created in the memory for the incoming N-bit tuple if a match is not found.

A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes each selected for translating a different set of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each of the virtual address received, the selection unit positions a field in that virtual address based on the page size selected for translating the set of virtual addresses to which that virtual address belongs. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator identifies an entry in a page table based on those bits.

A data processing device transmits the data bits on the predetermined quantity carrying wave signal of the OFDM sign. The data processing device comprises a parity interweaver for operating the pairs of LDPC coding data. The data bits are obtained by the parity matrix LDPC detecting with the LDPC code. The parity matrix has a ladder-type structure interweaving the LDPC code data to the different parity bit position. The mapping unit maps the parity interweaving bit to the data signs corresponding to the modulating signs of the solution. The sign interweaver reads the quantity signs to the sign interweaving store, carrying out the data sig of the sign interweaving store reading the order with different reading; the order address set is confirmed. The address set is generated by the address generator.

A master/slave data communication system in which a master device communicates with the slave devices by uniquely addressing each of the slave devices. In order to enhance the security of the data communication system, each slave device includes an address generator for generating unique addresses. Periodically, the master device requests that one or more slave device change its address. In response to the request, the addressed slave device increments its address generating algorithm to provide a new slave address. The master device also includes an algorithm that is synchronized with the slave address generating algorithm, whereby when the slave changes its address, it need not transmit the new slave address to the master device over the bus.

A data terminal which is coupled to an local area network and a public switched telephone network includes a sub-address generator that generates a sub-address based on an electronic mail address and a predetermined functional operation method. A data table generator generates an address conversion table correlating a plurality of sub-addresses to corresponding input electronic mail addresses. Each of the plurality of sub-addresses being uniquely coupled with a corresponding electronic mail address that is uniquely assigned to a single client terminal. The data terminal also includes memory to store the address conversion table and a terminal controller. The terminal controller checks an incoming call from a facsimile machine containing facsimile image information and a sub-address representing a destination client terminal, and upon receiving such incoming facsimile image information and sub-address, the controller determines an electronic mail address corresponding to the sub-address using the address conversion table. The controller then relays the facsimile image information to the destination client terminal at the determined appropriate electronic mail address.

A built-in self test (BIST) circuit comprising a linear feedback shift register is disclosed. The BIST circuit comprises a controller for controlling a self-testing operation of a memory chip embedded in an integrated circuit, an address generator for generating pseudo-random address patterns under control of the controller, a data generator for producing test data associated with data backgrounds of the address bits under the control of the controller, and a comparator for comparing the test data with memory data output from the memory chip to detect a defect, if any, of the memory chip. The pseudo-random random pattern comprises a single-random pseudo-random address pattern.

A memory device may include: a target address generator suitable for storing one or more addresses for each time a refresh command is skipped, and for generating one or more target addresses for each of the stored addresses during a burst refresh operation; and a refresh controller suitable for refreshing a word line selected among a plurality of word lines of a memory bank based on the generated one or more target addresses during a target refresh operation.

A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.

In one embodiment of the present invention, a programmable vision accelerator enables applications to collapse multi-dimensional loops into one dimensional loops. In general, configurable components included in the programmable vision accelerator work together to facilitate such loop collapsing. The configurable elements include multi-dimensional address generators, vector units, and load/store units. Each multi-dimensional address generator generates a different address pattern. Each address pattern represents an overall addressing sequence associated with an object accessed within the collapsed loop. The vector units and the load store units provide execution functionality typically associated with multi-dimensional loops based on the address pattern. Advantageously, collapsing multi-dimensional loops in a flexible manner dramatically reduces the overhead associated with implementing a wide range of computer vision algorithms. Consequently, the overall performance of many computer vision applications may be optimized.

A combined interleaving and deinterleaving circuit (IDL1) has a first data memory (RAM) for temporary storage of the data to be interleaved and deinterleaved. A first address generator produces a sequence of sequential addresses, and a second address generator (AG) produces a sequence of addresses which represents the interleaving rule (α(i)). A logic means (XOR, MUX) causes the data memory (RAM) to be addressed by the second address generator (AG) in the interleaving mode for a read process and in the deinterleaving mode for a write process.

The present invention relates to methods and a system for enhancing DHCP to promote a more secure IP address allocation model. The invention advantageously accomplishes this through the utilization of an address generator which is compatible with the existing DHCP protocol, and which incorporates an algorithm for use in producing a selected IP address as one of a sub-set of allocable addresses that are non-sequentially distributed within an address pool. As such, the invention offers robust security and allows for the rapid detection of unauthorized activity such as network intrusion, worms, virus propagation, network scanners, and SPAM.

The exemplary embodiments provide a multi-context configurable memory controller comprising: an input-output data port array comprising a plurality of input queues and a plurality of output queues; at least one configuration and control register to store, for each context of a plurality of contexts, a plurality of configuration bits; a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts, the plurality of data operations comprising memory address generation, memory write operations, and memory read operations, the configurable circuit element comprising a plurality of configurable address generators; and an element controller, the element controller comprising a port arbitration circuit to arbitrate among a plurality of contexts having a ready-to-run status, and the element controller to allow concurrent execution of multiple data operations for multiple contexts having the ready-to-run status.

A gateway realizes a connection between a network where HAVi devices are hooked up and another network in accordance with a Play-and-Plug spec. (e.g. the internet protocol (IP)) other than the HAVi spec. An HAVi plug-in detector detects a plug-in of a device to the HAVi network. A virtual device functions as a gateway for accessing from a device plugged-in the IP network to the device plugged-in the HAVi network. A virtual device controller provides the virtual device with an IP identifier for accessing to the virtual device from the IP network, and turns the virtual device to a standby status waiting for connection. A pseudo address generator generates a pseudo address for the virtual device to communicate with the device in the HAVi network, and provides the virtual device with the pseudo address. An address-correspondence-controller controls the correspondence between an HAVi address and the IP identifier both provided to the virtual device.

A buffer structure for storing symbols received via a number of (e.g., physical or transport) channels. Each channel is associated with a particular time interval (e.g., a radio frame period or a transmission time interval (TTI)) over which the received symbols are processed (e.g., interleaved). The buffer structure includes a buffer and an address generator. The buffer is partitioned into a number of sections. One section is assigned to each channel being processed. Each section can be operated as a circular buffer. The address generator provides addresses for writing symbols to the assigned sections. If the buffer structure is used for the transport channels, the sections can be assigned to the transport channels based on the associated TTIs (e.g., in descending order of TTIs). For each coded composite transport channel (CCTrCH), the transport channels in the CCTrCH can be assigned to sections defined starting from a respective initial location (e.g., the top or bottom of the buffer) and continuing along a respective direction of the buffer (e.g., downward or upward).

A multi-word line refresh-type semiconductor device may have a plurality of memory banks and performs a refresh operation simultaneously with respect to a plurality of word lines for each of the banks in a self-refresh mode. The semiconductor device includes an address controller for receiving a normal address and a refresh address and selectively outputting the received refresh address in a refresh mode, a fuse circuit for receiving the refresh address, determining whether the received refresh address corresponds to a word line to be repaired and outputting a redundancy word line enable signal and a first control signal according to a result of the determination, a first signal generator for, in response to a bit value for block selection of the refresh address and the first control signal, outputting a second control signal which defines a multi-word line refresh period, a refresh address generator for generating the refresh address in response to the second control signal, and a row controller for receiving the refresh address, second control signal and redundancy word line enable signal and controlling the refresh operation with respect to a memory core.