547 results about "Cell region" patented technology

The invention provides an OCR (Optical Character Recognition) method and system for high-precision table data structuring. The method comprises the following steps: converting an original image into a grayscale image and preprocessing the grayscale image; extracting a table edge structure line and filling a fracture part; detecting longitudinal and transverse straight lines in the preprocessed image, calculating intersection points, and determining a table row-column structure; dividing a cell region and positioning to generate a cell coordinate matrix; pixels in the cells are divided into a frame influence area and an effective data area, and the frame influence area executes neighborhood mean filtering and weighted fusion operation; performing end-to-end detection on characters and symbols in the effective data area, and outputting an OCR recognition result with coordinates; and dynamically generating a table structure template based on the cell coordinate matrix and an OCR recognition result, speculating a strategy matching field type through a rule, processing and merging cell missing data based on adjacent cell information, and outputting structured data. The reliability and accuracy of the OCR technology are improved, and the requirement of automatic information processing for high-precision data extraction is met.

The invention discloses a multimodal-based cell experiment image processing method and system and a storage medium, and the method comprises the steps: obtaining a single-channel gray image or a multi-channel fluorescence image containing cytoplasm and cell nucleus characteristics, carrying out the Gaussian filtering of a cytoplasm channel, and carrying out the median filtering of a cell nucleus channel; performing threshold segmentation on the preprocessed cytoplasm channel image by using a maximum between-class variance method to generate an initial cytoplasm mask; performing adaptive threshold segmentation on the preprocessed cell nucleus channel image to generate an initial cell nucleus mask; performing logic OR operation on the initial cytoplasm mask and the initial cell nucleus mask to generate an initial cell region; and finally, calculating each morphological parameter of each cell region and removing the cell regions of which the morphological parameters exceed a preset range to generate a segmentation result of the complete cell region, the morphological parameters and spatial distribution information. The problems that in the prior art, cytoplasm and cell nucleus noise processing segmentation precision is low, overlapped nucleus regions are difficult to separate, and morphological parameter analysis reliability is poor are solved.

According to the present disclosure, a semiconductor device includes a semiconductor substrate of a first conductivity type, in which a cell region, a ballast resistor region, and a termination region surrounding the ballast resistor region are defined, a first insulating film arranged on a front surface of the semiconductor substrate, having a first opening in the cell region, and having at least one second opening in the ballast resistor region, a second insulating film filled in the at least one second opening, a first impurity layer of a second conductivity type arranged on the front surface of the semiconductor substrate below the first opening, and a second impurity layer of the second conductivity type arranged on the front surface of the semiconductor substrate below the at least one second opening, a conductive film arranged from the front surface of the first opening of the semiconductor substrate to the termination region.

The invention relates to the technical field of cell image processing, in particular to a cell growth state detection method and system based on image processing. The method comprises the following steps: acquiring a suspected cell region degree of each pixel point in a grayscale image of a cell image; clustering the pixel points to obtain expanded boundary pixel points of class clusters, and then obtaining the confidence coefficient of the pixel points of each class cluster; multiplying the suspected cell region degree by the confidence coefficient, and normalizing to obtain the importance degree; analyzing the gray scale conditions of the pixel points in eight neighborhoods of one pixel point to obtain the gray scale change degree of the pixel point; acquiring adjacent pixel points of one pixel point, and analyzing to obtain the continuity degree of the pixel point; the enhancement coefficient of each pixel point is optimized according to the importance degree, the gray level change degree and the continuity degree of each pixel point, and then image enhancement is carried out; and carrying out cell growth state detection by utilizing the enhanced cell image. According to the invention, the accuracy of cell growth state detection can be improved.

Disclosed are a method, a device, and an information processing program for determining, by using refractive index distribution data pertaining to an object to be observed, the region of a cell that has undergone programmed cell death in the object to be observed.

There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive layers, which are alternately stacked in a third direction; a channel plug formed in a cell region, the channel plug penetrating the gate stack structure in the third direction; and at least one support structure formed in a contact region, the channel plug penetrating the gate stack structure in the third direction. The support structure includes a plurality of support structure layers that are sequentially stacked in the third direction, and the plurality of support structure layers are sequentially disposed such that each of the plurality of support structure layers extends in different directions along a plane defined by a first direction and a second direction, the first direction, the second direction, and the third direction being orthogonal to each other.

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with an SCR (Selective Catalytic Reduction) and a manufacturing method thereof, and relates to the technical field of power semiconductor devices, the device is integrated with a PNPN four-layer structure consisting of a P + region, an N-type epitaxial layer, a P-type body region and an N + source region between a grid electrode and a source electrode, and the P + region is in metal ohmic contact with the source electrode. Through collaborative design of the distance and the doping concentration of the P + region and the N + source region, the forward and reverse trigger voltage thresholds of the PNPN structure can be accurately matched with the asymmetric driving window of the electric control main drive. The structure is arranged on the outer edge of a cellular area or a terminal area, and is electrically isolated from an active area, a field plate is arranged to suppress false triggering, ohmic contact is optimized to accelerate turn-off, and it is ensured that holding current is higher than parasitic latch triggering current, so that rapid and reliable discharge and self-protection of bidirectional surge between a gate and a source are achieved on the premise that the performance of a main device is not affected, and the reliability of the device is improved. And the gate oxide reliability is obviously improved.

The application relates to a wireless table structure recognition method and device, equipment, a storage medium and a program product, and relates to the technical field of image recognition. At least one content contour is extracted from a target table image; noise removal processing is performed on each content contour to obtain at least one content region; clustering processing is performed based on the center points of each content region to determine a plurality of cell blocks; horizontal projection is performed on the plurality of cell blocks, and row coordinate information is determined according to the horizontal projection result; vertical projection is performed on the plurality of cell blocks, and column coordinate information is determined according to the vertical projection result; and the table structure is determined according to the row coordinate information and the column coordinate information. The method can reduce noise interference and improve the accuracy of wireless table structure recognition. The plurality of content regions in a cell are subjected to clustering processing, the table cell region can be accurately obtained, deep learning algorithms are not required, resource consumption is low, and the wireless table structure can be simply and effectively recognized.

The present invention relates to the field of image analysis technology, specifically to a method and system for monitoring the preparation process of umbilical cord mesenchymal stem cells, comprising the following steps: based on the umbilical cord mesenchymal stem cell image, image size standardization, noise removal, cell region cropping, grayscale value comparison to remove grayscale value regions below a set threshold, and filtering to eliminate background noise, remove noise points, and extract cell edge information to generate a denoised cell image. In the present invention, by introducing a residual network and convolution operation, cell morphological changes are accurately captured, providing more accurate proliferation state analysis, cell boundary extraction and cycle classification improvements, effectively avoiding the misjudgment of cell state in traditional methods, and deep learning training optimizes image segmentation, making cell cycle division more accurate, ensuring the efficiency and accuracy of the entire monitoring process, and ensuring the standardization and efficiency of the stem cell preparation process.

A semiconductor device includes a trench emitter electrode located at a boundary between one end of an active cell region and an inactive cell region, a trench gate electrode located at a boundary between the other end of the active cell region and the inactive cell region, an end trench gate electrode connected to one end of the trench gate electrode, and an end trench emitter electrode connected to one end of the trench emitter electrode. A hole barrier region of a first conductivity type is provided under a body region of a second conductivity type between the end trench gate electrode and the end trench emitter electrode in a plan view. A body region in the active cell region and a body region in the inactive cell region are connected to each other by a body region between the end trench gate electrode and the end trench emitter electrode.

To provide a semiconductor device with improved HBT withstand capability. [Solution] The semiconductor device comprises a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface which is the opposite surface of the first main surface. In a plan view, the second main surface has a cell region and an outer peripheral region located between the cell region and the outer peripheral edge of the second main surface. Within the silicon carbide substrate, the silicon carbide substrate has a termination structure and a channel stopper formed on the second main surface located in the outer peripheral region. In a plan view, the channel stopper is located outside the termination structure. The conductivity type of the silicon carbide substrate and the conductivity type of the channel stopper is a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in a plan view and at least partially overlaps the channel stopper in a plan view.

To provide an estimation method for estimating the amount of marker proteins in the stratum corneum. [Solution] Identify one or more cell regions, stratified exfoliation regions, and single-cell regions in the stratum corneum image. A marker protein quantity estimation method that estimates the amount of marker proteins in the stratum corneum from stratum corneum images based on the correlation between the obtained stratum corneum parameters as explanatory variables and one of the following as the dependent variable: Enolase-1 quantity, FABP5 quantity, or Polyamine quantity.

The invention relates to a deposition mask and an electronic device. The deposition mask includes: a mask substrate including a plurality of cell regions and a cell peripheral region surrounding the plurality of cell regions; a mask diaphragm disposed in the plurality of cell regions of the mask substrate and including a mask shield defining a pixel opening; a mask frame disposed in the cell peripheral region of the mask substrate and including a first upper inorganic layer on the mask substrate and a second upper inorganic layer on the first upper inorganic layer; and a mask conductive layer including a first portion on the mask frame and a second portion on the mask shield, where the first portion and the second portion are spaced apart from each other and the pixel opening is between the first portion and the second portion.

A semiconductor memory device is provided. The semiconductor memory device comprises a substrate including a cell region having an active region defined by a cell element isolation layer, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region. The device includes a word line structure in the substrate and extending in a first direction, a bit line structure on the substrate extending from the cell region to the boundary region in a second direction that crosses the first direction, including first and second cell conductive layers sequentially stacked on the substrate, and a bit line contact between the substrate and the bit line structure and connecting the substrate with the bit line structure. The second cell conductive layer in the boundary region is thicker than the second cell conductive layer in the cell region.

The embodiment of the invention relates to a semiconductor device. According to one embodiment, a semiconductor device includes: a semiconductor layer having a cell region and a terminal region surrounding the cell region; a first insulating film disposed on the semiconductor layer; and a semi-insulating film disposed on the first insulating film. The semiconductor layer includes: a first semiconductor portion of a first conductivity type provided in the cell region and the terminal region; and a second semiconductor part of a second conductivity type provided on the first semiconductor part in the terminal region, the second semiconductor part having a plurality of concentration peak regions in which the concentration of impurities of the second conductivity type is the highest in the second semiconductor part. An end portion of the first insulating film on the end region side is located between any two adjacent concentration peak regions among the plurality of concentration peak regions.

The utility model provides a semiconductor device. The semiconductor device comprises at least one cell. The cell is divided into two cell regions along a first direction. Each cellular region comprises a drift region, a source doped region, a contact hole and source metal. The source doped region comprises a well region, a source region and a plurality of contact regions arranged in the second direction. The source region comprises at least one embedded region extending into two adjacent contact regions. The contact hole exposes at least one part of the source doped region so that the source metal can be filled into the contact hole to be connected with the source doped region. In the cell, the state of configuring the contact hole to expose the source doped region is that the contact hole of at least one cell region exposes a part of the embedded region. According to the semiconductor device, the on-resistance is increased by prolonging the path of current flowing through the source region, and the short-circuit current capability is improved. By adjusting the gate structures of part of the cells of the semiconductor device, the short-circuit current capability and the conduction current capability of the device are further balanced.

An integrated circuit includes a first cell region including a first set of transistors of a clock circuit, and a second cell region adjacent to the first cell region along a first boundary. The second cell region includes a feed-through via extending from a front-side to a back-side of a substrate, and being configured to electrically couple elements on the front-side and the back-side together. The feed-through via includes a first conductor on the back-side of the substrate, a second conductor being on a first level and being above the first conductor, a first contact being on a second level, and being above the first conductor, and a first via being on a third level, and being above the first conductor.

To provide a device capable of reducing gate resistance. [Solution] The semiconductor device includes first to fourth electrodes, a semiconductor layer, a first contact, and a first conductive layer. The second electrode is located above the first electrode. The semiconductor layer is provided between the first electrode and the second electrode. The semiconductor layer includes first to third semiconductor regions. Multiple third electrodes are provided side by side in a cell region. The third electrode faces the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode includes a first extending portion and a wide portion. The fourth electrode faces the second semiconductor region via a second insulating portion. The first contact is located above the fourth electrode and is connected to the wide portion of the fourth electrode. The first conductive layer is located above the fourth electrode and is connected to the fourth electrode by the first contact.

The application discloses a SiC power device with local lifetime control and a manufacturing method thereof, which can be applied to the technical field of semiconductor devices. The device comprises an N-doped SiC substrate layer, an N-doped epitaxial layer grown on the substrate layer, a cell region and a termination region prepared on the epitaxial layer, and a first lifetime control region prepared between the cell region and the termination region. The first lifetime control region wraps a transition region well structure between the cell region and the termination region. In this way, by adding a local lifetime control region in the transition region, the number of minority carrier injection from the transition region to the termination region is reduced, local recombination and local reverse recovery speed are increased, and the response speed of the termination region is optimized.

Provided is a memory device including: a memory cell array including a plurality of cell regions; and a control logic configured to control a calculation operation on an appropriate read level based on a valley value of a search threshold voltage distribution in response to an error occurring in a read operation on the cell region. Based on a counting operation on data read by using the plurality of read levels, the control logic is configured to calculate first to Nth count values corresponding to first to Nth read levels, respectively, an intersection of at least two linear functions modeled by substituting the first to Nth read levels as an input and substituting the first to Nth count values as an output is calculated, and an appropriate read level is calculated based on at least one of a read level corresponding to a coordinate value of the intersection and a valley height.

The invention discloses an Apopsin3 mutant and a method for regulating an environment in a plant cell to be acidic, and belongs to the technical field of pH regulation in the plant cell. The regulation and control method comprises the following steps: mutating 83rd and 120th amino acids of the light-operated hydrogen ion pump protein Apopsin3, converting into hydrogen ion channels, expressing the hydrogen ion channels on a cell membrane in a targeting manner, and stimulating with green light of 40-500 [mu] W / mm < 2 > and 520-560 nm so as to regulate the pH in the cell to be acidic. By adopting the cell specific promoter and performing site-specific mutagenesis modification on the specific hydrogen ion pump, accurate pH regulation and control on specific cells or organelles can be realized. An Apopsin3 (FARH) gene is fused with a cell membrane targeting sequence, and under the stimulation of specific light, only the pH of cytoplasm is obviously changed, and the pH of other cell regions is not influenced.

The application belongs to the technical field of power devices, and provides a super-junction MOS device with strong terminal robustness, a preparation method thereof and a chip. The surface of a terminal withstand voltage region is higher than the surface of a cell region, so that a first P-type base region in a terminal transition region and a first P-type ring region in the terminal withstand voltage region form a first included angle, and the first P-type base region is in contact with a plurality of second P-type columns. The surface of the terminal withstand voltage region is higher than the surface of the cell region, and the first P-type base region and the first P-type ring region form a first included angle, so that the terminal transition region forms a slope along the terminal withstand voltage region to the cell region, thereby increasing the contact area of the terminal transition region and the source metal layer, improving the reverse extraction speed of the terminal holes, converting the one-dimensional hole channel of the terminal transition region structure into a two-dimensional channel, improving the extraction speed of the holes, and weakening the aggregation phenomenon of the electrons, thereby reducing the peak electric field and improving the terminal robustness of the device.

A method of manufacturing a display device includes providing a mother substrate including a first cell region, a second cell region, and a peripheral region. First alignment keys arranged in a first direction in the peripheral region on the mother substrate is formed such that the first alignment keys are adjacent to a first side portion of each of first and second light emitting structures, while forming the first and second light emitting structures in the first and second cell regions on the mother substrate, respectively. A photoresist is formed in a second direction on the first and second light emitting structures by using a coater such that the photoresist does not to overlap the first alignment keys. The mother substrate is rotated at a preset angle. A light is irradiated to the photoresist by moving an exposer in a direction in which the first alignment keys are arranged.

A semiconductor device (100) comprises a silicon carbide substrate (10), a field oxide film (20), an insulating film (50), and a wiring layer (60). The silicon carbide substrate comprises a first main surface (10a) and a second main surface (10b), which is opposite the first main surface. The second main surface comprises a cell region (10ba) and an outer peripheral region (10bb) located, in plan view, between the cell region and an outer peripheral edge of the second main surface. The silicon carbide substrate includes a termination structure (18) and a channel stopper (19) formed in the second main surface located in the outer peripheral region. The channel stopper is located outside the termination structure in plan view.One conductivity type of the silicon carbide substrate and one conductivity type of the channel stopper each constitute a first conductivity type. The termination structure exhibits a second conductivity type opposite to the first. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in plan view and at least partially overlaps the channel stopper in plan view.

Embodiments of the present application relate to a cell region of a semiconductor device and a method of manufacturing the same. The cell region (of the semiconductor device) includes: first and second active regions located on opposite sides of a first reference line and adjacent to the first reference line and doped with different dopants accordingly; and dummy gate segments, each of which overlaps with the active regions; corresponding AR portions of the active regions are defined between adjacent dummy gate segments; each of the first and second active regions includes adjacent first and second AR portions; the first and second AR portions define first and second AR segments; each of the first and second AR segments has first and second profiles located at proximal and distal ends of the first reference line accordingly; and the proximal profile of each of the first and second AR segments is planar; and the distal profile of the first or second AR segment is stepped, such that the first or second AR segment is a concave polygonal shape.

A memory device includes a cell region in which a plurality of memory cells are arranged and a peripheral circuit region in which a row decoder is connected to the plurality of memory cells through a plurality of wordlines, a plurality of page buffers connected to the plurality of memory cells through a plurality of bitlines, and a control logic controlling the row decoder and the plurality of page buffers are arranged. The row decoder inputs a plurality of read voltages having different levels to a selected wordline among the plurality of wordlines in sequence. Each of the plurality of page buffers includes a sensing node connected to one of the plurality of bitlines. Voltages of the sensing nodes included in the page buffers of a portion of the plurality of page buffers decrease differently while each of the plurality of read voltages is input to the selected wordline.

An epitaxial wafer for a GaN HEMT having enhanced electrical insulation and a method of manufacturing the same are provided according to an embodiment of the present invention, the epitaxial wafer comprising: a growth substrate; a nucleation region, wherein the nucleation region is grown on the growth substrate; and a high resistance region having high resistance characteristics, the high resistance region including a high resistance cell region defined by a first region grown as a group III nitride semiconductor doped with carbon and a second region grown as a group III nitride semiconductor on the first region, the high-resistance region is arranged on the nucleation region; and an active region including a channel region grown on the high resistance region and a barrier region grown on the channel region.

The present invention provides a semiconductor device capable of reducing gate resistance and a method for manufacturing the same. [Solution] According to the embodiment, the semiconductor device includes first to fourth electrodes, a semiconductor layer, and wiring. The second electrode is located above the first electrode. The semiconductor layer is provided between the first and second electrodes and includes first to third semiconductor regions. A plurality of third electrodes are provided side by side in the cell region where the second electrodes are provided. The third electrodes face the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode faces the second semiconductor region via a second insulating portion. The first insulating layer is provided on top of the semiconductor layer. The wiring is provided in the cell region within the first insulating layer, extends above and along the fourth electrode, is thinner than the fourth electrode, and is electrically connected to the fourth electrode.

Semiconductor device, exhibiting: - a semiconductor substrate (51) of a first conductivity type in which a cell region (1), an interface region (2) surrounding the cell region (1), and a termination region (3) surrounding the interface region (2) are defined; and - an insulating film (10) arranged on a surface of the semiconductor substrate (51), where: - the insulating film (10) contains a first opening part area (10a1, 10a2) in at least one of the cell area (1) and the closure area (3) and a second opening part area (10b) in the interface area (2), wherein the second opening part area has an opening ratio that is less than an opening ratio of the first opening part area (10a1, 10a2), - the semiconductor device further features: - a first defect layer (7, 8) of a second conductivity type, which is arranged on the surface of the semiconductor substrate (51) below the first opening part region (10a1, 10a2); and - a second defect layer (9) of the second conductivity type, which has a defect concentration that is lower than a defect concentration of the first defect layer (7, 8), and is arranged on the surface of the semiconductor substrate (51) below the second opening part region (10b), and - the second defect layer (9) is arranged continuously across sub-areas under each of a plurality of second opening sub-areas (10b).