314 results about "Cell region" patented technology

Disclosed are a method, a device, and an information processing program for determining, by using refractive index distribution data pertaining to an object to be observed, the region of a cell that has undergone programmed cell death in the object to be observed.

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with an SCR (Selective Catalytic Reduction) and a manufacturing method thereof, and relates to the technical field of power semiconductor devices, the device is integrated with a PNPN four-layer structure consisting of a P + region, an N-type epitaxial layer, a P-type body region and an N + source region between a grid electrode and a source electrode, and the P + region is in metal ohmic contact with the source electrode. Through collaborative design of the distance and the doping concentration of the P + region and the N + source region, the forward and reverse trigger voltage thresholds of the PNPN structure can be accurately matched with the asymmetric driving window of the electric control main drive. The structure is arranged on the outer edge of a cellular area or a terminal area, and is electrically isolated from an active area, a field plate is arranged to suppress false triggering, ohmic contact is optimized to accelerate turn-off, and it is ensured that holding current is higher than parasitic latch triggering current, so that rapid and reliable discharge and self-protection of bidirectional surge between a gate and a source are achieved on the premise that the performance of a main device is not affected, and the reliability of the device is improved. And the gate oxide reliability is obviously improved.

To provide a semiconductor device with improved HBT withstand capability. [Solution] The semiconductor device comprises a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface which is the opposite surface of the first main surface. In a plan view, the second main surface has a cell region and an outer peripheral region located between the cell region and the outer peripheral edge of the second main surface. Within the silicon carbide substrate, the silicon carbide substrate has a termination structure and a channel stopper formed on the second main surface located in the outer peripheral region. In a plan view, the channel stopper is located outside the termination structure. The conductivity type of the silicon carbide substrate and the conductivity type of the channel stopper is a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in a plan view and at least partially overlaps the channel stopper in a plan view.

To provide an estimation method for estimating the amount of marker proteins in the stratum corneum. [Solution] Identify one or more cell regions, stratified exfoliation regions, and single-cell regions in the stratum corneum image. A marker protein quantity estimation method that estimates the amount of marker proteins in the stratum corneum from stratum corneum images based on the correlation between the obtained stratum corneum parameters as explanatory variables and one of the following as the dependent variable: Enolase-1 quantity, FABP5 quantity, or Polyamine quantity.

A semiconductor memory device is provided. The semiconductor memory device comprises a substrate including a cell region having an active region defined by a cell element isolation layer, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region. The device includes a word line structure in the substrate and extending in a first direction, a bit line structure on the substrate extending from the cell region to the boundary region in a second direction that crosses the first direction, including first and second cell conductive layers sequentially stacked on the substrate, and a bit line contact between the substrate and the bit line structure and connecting the substrate with the bit line structure. The second cell conductive layer in the boundary region is thicker than the second cell conductive layer in the cell region.

The embodiment of the invention relates to a semiconductor device. According to one embodiment, a semiconductor device includes: a semiconductor layer having a cell region and a terminal region surrounding the cell region; a first insulating film disposed on the semiconductor layer; and a semi-insulating film disposed on the first insulating film. The semiconductor layer includes: a first semiconductor portion of a first conductivity type provided in the cell region and the terminal region; and a second semiconductor part of a second conductivity type provided on the first semiconductor part in the terminal region, the second semiconductor part having a plurality of concentration peak regions in which the concentration of impurities of the second conductivity type is the highest in the second semiconductor part. An end portion of the first insulating film on the end region side is located between any two adjacent concentration peak regions among the plurality of concentration peak regions.

An integrated circuit includes a first cell region including a first set of transistors of a clock circuit, and a second cell region adjacent to the first cell region along a first boundary. The second cell region includes a feed-through via extending from a front-side to a back-side of a substrate, and being configured to electrically couple elements on the front-side and the back-side together. The feed-through via includes a first conductor on the back-side of the substrate, a second conductor being on a first level and being above the first conductor, a first contact being on a second level, and being above the first conductor, and a first via being on a third level, and being above the first conductor.

To provide a device capable of reducing gate resistance. [Solution] The semiconductor device includes first to fourth electrodes, a semiconductor layer, a first contact, and a first conductive layer. The second electrode is located above the first electrode. The semiconductor layer is provided between the first electrode and the second electrode. The semiconductor layer includes first to third semiconductor regions. Multiple third electrodes are provided side by side in a cell region. The third electrode faces the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode includes a first extending portion and a wide portion. The fourth electrode faces the second semiconductor region via a second insulating portion. The first contact is located above the fourth electrode and is connected to the wide portion of the fourth electrode. The first conductive layer is located above the fourth electrode and is connected to the fourth electrode by the first contact.

The application discloses a SiC power device with local lifetime control and a manufacturing method thereof, which can be applied to the technical field of semiconductor devices. The device comprises an N-doped SiC substrate layer, an N-doped epitaxial layer grown on the substrate layer, a cell region and a termination region prepared on the epitaxial layer, and a first lifetime control region prepared between the cell region and the termination region. The first lifetime control region wraps a transition region well structure between the cell region and the termination region. In this way, by adding a local lifetime control region in the transition region, the number of minority carrier injection from the transition region to the termination region is reduced, local recombination and local reverse recovery speed are increased, and the response speed of the termination region is optimized.

Provided is a memory device including: a memory cell array including a plurality of cell regions; and a control logic configured to control a calculation operation on an appropriate read level based on a valley value of a search threshold voltage distribution in response to an error occurring in a read operation on the cell region. Based on a counting operation on data read by using the plurality of read levels, the control logic is configured to calculate first to Nth count values corresponding to first to Nth read levels, respectively, an intersection of at least two linear functions modeled by substituting the first to Nth read levels as an input and substituting the first to Nth count values as an output is calculated, and an appropriate read level is calculated based on at least one of a read level corresponding to a coordinate value of the intersection and a valley height.

The application belongs to the technical field of power devices, and provides a super-junction MOS device with strong terminal robustness, a preparation method thereof and a chip. The surface of a terminal withstand voltage region is higher than the surface of a cell region, so that a first P-type base region in a terminal transition region and a first P-type ring region in the terminal withstand voltage region form a first included angle, and the first P-type base region is in contact with a plurality of second P-type columns. The surface of the terminal withstand voltage region is higher than the surface of the cell region, and the first P-type base region and the first P-type ring region form a first included angle, so that the terminal transition region forms a slope along the terminal withstand voltage region to the cell region, thereby increasing the contact area of the terminal transition region and the source metal layer, improving the reverse extraction speed of the terminal holes, converting the one-dimensional hole channel of the terminal transition region structure into a two-dimensional channel, improving the extraction speed of the holes, and weakening the aggregation phenomenon of the electrons, thereby reducing the peak electric field and improving the terminal robustness of the device.

A method of manufacturing a display device includes providing a mother substrate including a first cell region, a second cell region, and a peripheral region. First alignment keys arranged in a first direction in the peripheral region on the mother substrate is formed such that the first alignment keys are adjacent to a first side portion of each of first and second light emitting structures, while forming the first and second light emitting structures in the first and second cell regions on the mother substrate, respectively. A photoresist is formed in a second direction on the first and second light emitting structures by using a coater such that the photoresist does not to overlap the first alignment keys. The mother substrate is rotated at a preset angle. A light is irradiated to the photoresist by moving an exposer in a direction in which the first alignment keys are arranged.

A semiconductor device (100) comprises a silicon carbide substrate (10), a field oxide film (20), an insulating film (50), and a wiring layer (60). The silicon carbide substrate comprises a first main surface (10a) and a second main surface (10b), which is opposite the first main surface. The second main surface comprises a cell region (10ba) and an outer peripheral region (10bb) located, in plan view, between the cell region and an outer peripheral edge of the second main surface. The silicon carbide substrate includes a termination structure (18) and a channel stopper (19) formed in the second main surface located in the outer peripheral region. The channel stopper is located outside the termination structure in plan view.One conductivity type of the silicon carbide substrate and one conductivity type of the channel stopper each constitute a first conductivity type. The termination structure exhibits a second conductivity type opposite to the first. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in plan view and at least partially overlaps the channel stopper in plan view.

Embodiments of the present application relate to a cell region of a semiconductor device and a method of manufacturing the same. The cell region (of the semiconductor device) includes: first and second active regions located on opposite sides of a first reference line and adjacent to the first reference line and doped with different dopants accordingly; and dummy gate segments, each of which overlaps with the active regions; corresponding AR portions of the active regions are defined between adjacent dummy gate segments; each of the first and second active regions includes adjacent first and second AR portions; the first and second AR portions define first and second AR segments; each of the first and second AR segments has first and second profiles located at proximal and distal ends of the first reference line accordingly; and the proximal profile of each of the first and second AR segments is planar; and the distal profile of the first or second AR segment is stepped, such that the first or second AR segment is a concave polygonal shape.

A memory device includes a cell region in which a plurality of memory cells are arranged and a peripheral circuit region in which a row decoder is connected to the plurality of memory cells through a plurality of wordlines, a plurality of page buffers connected to the plurality of memory cells through a plurality of bitlines, and a control logic controlling the row decoder and the plurality of page buffers are arranged. The row decoder inputs a plurality of read voltages having different levels to a selected wordline among the plurality of wordlines in sequence. Each of the plurality of page buffers includes a sensing node connected to one of the plurality of bitlines. Voltages of the sensing nodes included in the page buffers of a portion of the plurality of page buffers decrease differently while each of the plurality of read voltages is input to the selected wordline.

The present invention provides a semiconductor device capable of reducing gate resistance and a method for manufacturing the same. [Solution] According to the embodiment, the semiconductor device includes first to fourth electrodes, a semiconductor layer, and wiring. The second electrode is located above the first electrode. The semiconductor layer is provided between the first and second electrodes and includes first to third semiconductor regions. A plurality of third electrodes are provided side by side in the cell region where the second electrodes are provided. The third electrodes face the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode faces the second semiconductor region via a second insulating portion. The first insulating layer is provided on top of the semiconductor layer. The wiring is provided in the cell region within the first insulating layer, extends above and along the fourth electrode, is thinner than the fourth electrode, and is electrically connected to the fourth electrode.

Semiconductor device, exhibiting: - a semiconductor substrate (51) of a first conductivity type in which a cell region (1), an interface region (2) surrounding the cell region (1), and a termination region (3) surrounding the interface region (2) are defined; and - an insulating film (10) arranged on a surface of the semiconductor substrate (51), where: - the insulating film (10) contains a first opening part area (10a1, 10a2) in at least one of the cell area (1) and the closure area (3) and a second opening part area (10b) in the interface area (2), wherein the second opening part area has an opening ratio that is less than an opening ratio of the first opening part area (10a1, 10a2), - the semiconductor device further features: - a first defect layer (7, 8) of a second conductivity type, which is arranged on the surface of the semiconductor substrate (51) below the first opening part region (10a1, 10a2); and - a second defect layer (9) of the second conductivity type, which has a defect concentration that is lower than a defect concentration of the first defect layer (7, 8), and is arranged on the surface of the semiconductor substrate (51) below the second opening part region (10b), and - the second defect layer (9) is arranged continuously across sub-areas under each of a plurality of second opening sub-areas (10b).

In some embodiments, the semiconductor device includes a substrate comprising a cell region, a dummy region spaced apart from the cell region in a first direction, and a border region between the cell region and the dummy region, an active pattern on the cell region, a device isolation layer on the substrate, source / drain patterns on the active pattern and channel patterns between the source / drain patterns, cell gate electrodes crossing the channel patterns in a second direction, active contacts disposed on the cell region and between the cell gate electrodes and coupled to the source / drain patterns, dummy gate electrodes on the dummy region and on the device isolation layer, dummy contacts on the dummy region and on a side surface of each of the dummy gate electrodes, an interlayer insulating layer on the side surface of each of the dummy gate electrodes, and a dam structure on the border region.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure. The substrate has a cell region and a peripheral region. The first isolation structure is disposed in the cell region of the substrate. The first isolation structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is spaced apart from the substrate by the first dielectric layer. The second dielectric layer is doped with an impurity.

The invention relates to the technical field of semiconductor devices, in particular to a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: providing a substrate with an epitaxial layer; sequentially forming a JFET layer and a first type doping layer on the epitaxial layer, wherein a cellular region and a bus region are defined on the surface of the first type doping layer; a second type doped column is formed by extending from the surface of the first type doped layer, the second type doped column penetrates through the first type doped layer and the JFET layer, and the bottom of the second type doped column is located in the epitaxial layer; a groove is formed in the second type doping column through etching, a second type doping area is reserved between the inner wall of the groove and the outer wall of the second type doping column, and the groove comprises a cellular groove formed in the cellular area and a bus groove formed in the bus area. The method has the advantages that the technological process is simple, and the uniform second-type doped region can be formed without accurately controlling the injection angle like a traditional method.

The present invention provides a semiconductor device that improves current spread by reducing saturated drain current, lowering the degree of current concentration at the active source contact, and improving voltage overshooting or non-uniformity of source current at different cell region locations. [Solution] The semiconductor device includes a substrate including a cell region and a peripheral region PERI located outside the cell region, a first conductivity type semiconductor layer located on the upper surface of the substrate, a second conductivity type doping wall region located within the first conductivity type semiconductor layer, a gate electrode located on the first conductivity type semiconductor layer, a gate insulating layer located between the first conductivity type semiconductor layer and the gate electrode, a source electrode 170 located on the second conductivity type doping wall region, and a drain electrode located below the lower surface of the substrate. The source electrode includes a first source electrode 171 located on the gate electrode and a second source electrode 172 located on the first source electrode and having a greater electrical resistance than the first source electrode.

A semiconductor device having a through via and a method for manufacturing the semiconductor device are provided. The semiconductor device includes a semiconductor chip including: a cell region including a memory cell; a peripheral circuit region stacked on the cell region in a first direction and including a peripheral circuit element electrically connected to the memory cell; a through via penetrating the cell region and the peripheral circuit region in the first direction; a backside pad disposed below the cell region and electrically connected to the through via; and a frontside pad disposed above the peripheral circuit region and electrically connected to the through via. The cell region includes a cell insulating layer surrounding the memory cell and a cell substrate disposed below the cell insulating layer. The peripheral circuit region includes a peripheral circuit insulating layer surrounding the peripheral circuit element and a peripheral circuit substrate disposed below the peripheral circuit insulating layer. The through via penetrates the cell substrate, the cell insulating layer, the peripheral circuit substrate, and the peripheral circuit insulating layer along the first direction.

The cell region (10) and the connection region (200) have: a semiconductor substrate (30) including a drift layer (31), a base layer (32) formed in a surface layer portion of the drift layer (31), a collector layer (41) formed in the IGBT region (11) and the connection region (200), and a cathode layer (42) formed in the FWD region (12), a surface on the base layer (32) side serving as one surface (30a), and surfaces on the collector layer (41) and the cathode layer (42) side serving as the other surface (30b); and a contact region (37) formed in the surface layer portion of the base layer (32) in the additional FWD region (12a) and the connection region (200); and the formation area of the contact region (37) per unit area in the connection region (200) is smaller than the formation area of the contact region (37) per unit area in the additional FWD region (12a) on one surface (30a) of the semiconductor substrate (30).

The invention provides a semiconductor device and a preparation method thereof, and the semiconductor device comprises a substrate which comprises a substrate and an epitaxial layer, the epitaxial layer is located at one side of the substrate, and the substrate is of a first doping type; the doped regions are located in the epitaxial layer at intervals, the surfaces of the sides, away from the substrate, of the doped regions are located in the surface of the side, away from the substrate, of the epitaxial layer, and the doped regions are of the second doping type; the ohmic contact structures are located on the side, away from the substrate, of the epitaxial layer of the cellular region of the semiconductor device at intervals, the ohmic contact structures make contact with the doped region, the ohmic contact structures contain carbon, and the problem that in the prior art, the ohmic contact resistance of the semiconductor device is high is solved.

This invention discloses a silicon carbide junction barrier Schottky diode, belonging to the field of semiconductor technology. It includes a silicon carbide substrate, an N+ buffer zone, an N+ drift region, a cell region, a termination region, an isolation layer, a cathode metal, an anode metal, and a passivation layer. The N+ buffer zone is located above the silicon carbide substrate and has a first epitaxial layer. The N+ drift region is located above the N+ buffer zone and has a second and a third epitaxial layer, with the second epitaxial layer covering the first and third epitaxial layers respectively. The cell region includes a P+ junction. The termination region is located above the N+ drift region and has a P+ field-limiting ring. A P+ transition region is located between the cell region and the termination region. The isolation layer covers the termination region. The passivation layer covers the isolation layer. The cathode metal covers the bottom of the silicon carbide substrate, and the anode metal is located above the N+ drift region. This diode has a low forward voltage drop and a high reverse breakdown voltage.

The application provides a junction termination structure and a preparation method thereof and a semiconductor device. The junction termination structure comprises a cell region and a termination region located at the periphery of the cell region. The junction termination structure comprises a substrate with a first conductivity type, an epitaxial layer with the first conductivity type located above the substrate, and a plurality of annular grooves located in the epitaxial layer. The plurality of annular grooves are located in the termination region and surround the cell region, comprising first-type annular grooves and second-type annular grooves, and each annular groove is provided with a polysilicon structure and a first insulating layer covering the bottom wall and the side wall of the annular groove; the first-type annular groove is further provided with a second insulating layer and a conductive structure, two polysilicon structures are arranged in the first-type annular groove, the two polysilicon structures are located on the opposite sides of the conductive structure, and the second insulating layer is located between the polysilicon structure and the conductive structure. At least one annular groove close to the cell region is the first-type annular groove, and the conductive structure in the at least one first-type annular groove is configured to be connected to zero potential when the junction termination structure is reversely broken down.

The invention relates to a semiconductor package. A semiconductor package and a method of manufacturing the same are disclosed. A semiconductor chip may be disposed on a package substrate having a vent hole formed therethrough, and a molding layer including a lower molding portion connected to an upper molding portion may be formed. The package substrate may include a substrate body having a plurality of cell regions, spherical bosses disposed in the cell regions, and first and second dam patterns spanning the cell regions and extending into edge regions located outside the cell regions.

A cell region includes: a transistor-components layer including a first feedthrough via arrangement (FTA); a first metallization layer over the transistor-components layer and including first-front-side segments, the first front-side segments including first and second front-side power grid (FPG) segments, and one or more front-side routing (FRTE) segments including a first FRTE segment; and a first buried metallization layer under the transistor-components layer and including first back-side segments, the first back-side segments including first and second back-side power grid (BPG) segments, and one or more back-side routing (BRTE) segments including a first BRTE segment. The first FTA couples the first FRTE segment to the first BRTE segment. Relative to the first direction and a second direction perpendicular to the first direction, the first BPG segment having a first notch partially occupied by at least a first portion of the first BRTE segment.

A nonvolatile memory device includes a first cell region, a second cell region, and a peripheral circuit region. The first cell region includes a first normal bit line and a first redundant bit line. The second cell region is disposed above the first cell region in a vertical direction and includes a second normal bit line and a second redundant bit line. The peripheral circuit region is disposed below the first cell region in the vertical direction and includes a page buffer circuit and a page buffer decoder. The page buffer circuit includes a page buffer connected to the first normal bit line, the second normal bit line, the first redundant bit line, and the second redundant bit line. The page buffer decoder is configured to integrate a defective bit line occurring among the first normal bit line and the second normal bit line and replace the defective bit line with the first redundant bit line and the second redundant bit line.

The invention provides an automatic migration rate quantification method for a mesenchymal stem cell scratch experiment. In order to solve the problems of fuzzy cell scratch boundary, low contrast, irregular form and difficulty in automatic migration rate quantification, the method comprises the following steps: firstly, constructing a mesenchymal stem cell (MSCs) scratch microscopic image data set, and carrying out gray scale and contrast enhancement on an original RGB image; and then, automatic segmentation of the scratch and the cell region is realized by utilizing a high-low frequency feature decoupling network, and quantitative analysis of the end-to-end mobility is realized by combining time sequence mask alignment, initial scratch region identification and scratch area measurement at each time point. The method supports batch processing of images at multiple time points, provides a high-precision, automatic and visual mobility analysis means, and can be widely applied to mesenchymal stem cell migration behavior research and regenerative medicine experiments.