1374 results about "Cell region" patented technology

A semiconductor device includes a substrate having a cell region and a connection region. A plurality of gate electrodes is stacked in a vertical direction in the cell region of the substrate. Conductive pads that are electrically connected to a peripheral circuit extend horizontally from the gate electrodes to the connection region. The conductive pads form a cascade structure in the connection region. Contact plugs that have different vertical lengths are electrically connected to respective ones of the conductive pads. The conductive pads have contact portions that are thicker in the vertical direction than the gate electrodes.

A transmitter transmits time synchronized data via a pager/WiMax/802.x access to a receiver system, wherein the receiver system is programmed to receive data for specific geographic locations. The geographic locations may be specified by the user or by the receiver system, and includes state, zip codes, towns, counties, towns, or cardinal regions. The receiver is able to find its location when outside its cell region and is able to synchronize to the data transmitted in the new cell region. Further, the receiver system is able to remotely monitor weather data and other information at a different location via wireless Internet or voice over IP. A transceiver may also be used to receive weather or alert data. In response to receiving data, the transceiver transmits the data to low powered devices in a house using a different frequency band than the frequency band it received the data.

A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

A semiconductor device includes a first-conductivity-type semiconductor layer which includes a cell region portion and a junction terminating region portion. The junction terminating region portion is a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field.

An method and apparatus for transmitting ranging information from at least one base station to subscriber stations and generating a ranging signal by the subscriber station using received ranging information in a Broadband Wireless Access (BWA) communication system including a plurality of neighbor cells and a plurality of the subscriber stations located in each cell region. A first code generator generates a first code using different first code information received from the base stations in the neighbor cells allocated the first code information. A second code generator generates a second code using second code information received by each of the subscriber stations existing in cell regions of the neighbor cells. A ranging signal generator generates a new ranging signal by combining the first code with the second code.

A semiconductor memory device and method of manufacturing the same are disclosed. The semiconductor memory device includes a semiconductor substrate having a cell region and a peripheral circuit region, first transistors provided on the semiconductor substrate, a first semiconductor layer provided on the first transistors, and bonded by a bonding technique, and second transistors provided on the first semiconductor layer, wherein the first and second transistors are provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer, respectively, and a metal layer is formed on gates of the first and second transistors respectively provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer. As a result, the transistors in the peripheral circuit region requiring high performance can be formed on an upper layer and a lower layer.

A vertical-type semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a wordline structure on the cell region of the semiconductor substrate, the wordline structure including a plurality of wordlines stacked on top of each other, a semiconductor structure through the wordline structure, a gate dielectric between the wordline structure and the semiconductor structure, and a dummy wordline structure on the peripheral circuit region, the dummy wordline structure having a vertical structure and including same components as the wordline structure.

A nonvolatile memory device includes a substrate including a cell region, contact regions and dummy contact regions. The contact regions and the dummy contact regions alternately are disposed. A plurality of word lines stacked at the cell region of the substrate and contact groups stacked at the contact regions and the dummy contact regions of the substrate. The contact groups include a plurality of pad layers being coupled to the word lines, and each of the contact groups has stepped structure disposed at a corresponding contact region.

A semiconductor memory device includes a first substrate on which a cell region is defined. In the cell region, memory cells are stacked. A second substrate is located above the first substrate, and a peripheral region is defined on the second substrate. One or more conductive lines are located in the peripheral region. The one or more lines extend through the second substrate and couple to the cell region.

An encapsulation for an organic light emitting diode (OLED) (201) device is disclosed. The encapsulation includes a sealing dam (280) surrounding the cell region of the OLED device to support a cap. The sealing dam provides a sealing region between the edge of the cap and dam in which an adhesive is applied to seal the OLED device. The use of the sealing dam advantageously enables devices to be formed with narrower sealing widths.

A semiconductor device including a pixel region in which one or more pixels are formed and a DRAM cell region in which one or more DRAM cells for storing output signals from the pixels are formed, characterized in that the layers constituting the pixel region and the DRAM cell region are formed in the same semiconductor process.

A method of fabricating a non-volatile memory device includes providing a substrate with a cell region where a plurality of memory cells that are stacked vertically are to be formed and a peripheral circuit region where a peripheral circuit device is to be formed. Forming a gate structure where an inter-layer dielectric layer and a gate electrode layer are alternately stacked over the substrate of the cell region and the peripheral circuit region. Forming a first trench that isolates the gate electrode layers in one direction by selectively etching the gate structure of the cell region and forming a trench by selectively etching the gate structure corresponding to a contact formation region of the peripheral circuit region.

In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a portion of the semiconductor substrate in the cell region and in the peripheral circuit region including an isolation region defining an active region, a portion of the active region protruding above an upper surface of the isolation region to define at least two active channels, a gate dielectric layer formed over the active region of the semiconductor substrate including the at least two protruding active channels, a gate electrode formed over the gate dielectric layer and the isolation region of the semiconductor substrate, and a source/drain region formed in the active region of the semiconductor substrate on either side of the gate electrode.

A method for determination of tunnel oxide weakness is provided. A tunnel oxide layer is formed on a semiconductor wafer. At least one poly gate is formed on the tunnel oxide layer in a flash memory region of the semiconductor wafer. At least one poly island, which is substantially larger than the poly gate, is formed on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer. The poly island and the tunnel oxide layer therebeneath form a voltage contrast tunnel oxide cell. A voltage contrast measurement is performed on the voltage contrast tunnel oxide cell. The voltage contrast measurement is then compared with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells. The tunnel oxide weakness of the tunnel oxide layer is then determined from the voltage contrast measurement comparisons.

According to the present invention, a semiconductor integrated circuit having: a cell region in which a plurality of MOS transistors forming at least one cell are placed; and first and second power lines placed along one direction in a peripheral portion of the cell region, wherein in the cell region, gate grids for defining a first pitch in the one direction and pin grids for defining a second pitch in the one direction are set, gate electrodes of the MOS transistors are placed in accordance with the gate grids, and an interconnection layer is placed in accordance with the pin grids.

Methods and apparatus are described and illustrated for producing GPS corrections, comprising: collecting measurements from a plurality of network reference stations; determining network corrections from the measurements; determining residual errors at one or more vernier-cell reference stations; and preparing vernier-cell corrections to compensate the residual errors within a vernier-cell region. Network correction streams are described and illustrated which contain network corrections derived from a plurality of network reference stations and residual error corrections derived from one or more vernier-cell reference stations. Methods and apparatus are described for employing such network correction streams in a virtual reference station to produce corrections and/or virtual measurements for use in a GPS receiver.

An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p⁺ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p⁺ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

A system and method for increasing the performance of a satellite communication system by using a multivariate analysis approach to optimize the pointing of the boresight of a satellite-mounted antenna. Optimizing the pointing of the boresight of the antenna minimizes sidelobe generation, and thus Co-Channel Interference (CCI) in geographic areas served by the system. By minimizing CCI, the overall system performance of the communication system is optimized. To optimize the pointing of the boresight of the antenna, the overall performance of the satellite communication system is determined, and the boresight of the antenna is iteratively repointed in the direction of increasing system performance until the optimized boresight pointing is determined. Alternatively, the frequency re-use plan of the satellite communication system may be analyzed to determine a high density cell region and the boresight may be pointed to the high density cell region.