45 results about "Floating body cell" patented technology

A semiconductor storage device according to one embodiment of the present invention, comprising: FBCs (Floating Body Cells) which store data by accumulating a majority carrier in a floating channel body; and sense amplifiers which perform control reading out data stored in said FBC, wherein each of said sense amplifier includes: a pair of sense nodes provided corresponding to a bit line pair to which said FBC is connected; a pair of load which flow currents through said pair of sense nodes; latch circuits which latch potentials of said pair of sense nodes when a potential difference between said pair of sense nodes reaches a predetermined value; and an output control circuit which outputs latched outputs of said latch circuits at a predetermined timing and feeds back the latched outputs to said bit line pair side to again write it into said FBC.

A semiconductor integrated apparatus, comprising: an SOI (Silicon On Insulator) substrate which has a support substrate and an embedded insulation film; an NMOSFET, a PMOSFET and an FBC (Floating Body Cell) formed on the SOI substrate separately from each other; a p type of first well diffusion region formed along the embedded insulation film in the support substrate below the NMOSFET; an n type of second well diffusion region formed along the embedded insulation film in the support substrate below the PMOSFET; and a conduction type of third well diffusion region formed along the embedded insulation film in the support substrate below the FBC.

A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive portion positioned below the body in the cylindrical pillar, a gate oxide layer surrounding the sidewall of the cylindrical pillar and a gate structure surrounding the gate oxide layer. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body can store carriers such as holes. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the surface of the semiconductor substrate to electrically connect the bottom conductive regions in the cylindrical pillars.

An integrated circuit having both floating body cells and logic devices fabricated in a bulk silicon substrate is described. The floating body cells have electrically floating bodies formed by oxidizing a lower portion of the cell bodies to electrically isolate them from the substrate.

An improved dynamic memory cell using a semiconductor fin or body is described. Asymmetrical doping is used in the channel region, with more dopant under the back gate to improve retention without significantly increasing read voltage.

The invention discloses a floating structure connected by a tension connector with adjustable length. Floating body cells are connected by the tension connector with adjustable length, and elastic buffer material is installed among the floating body cells; a pull force is borne by the tension connector; a pressure is borne by the elastic buffer material and the floating body cells; and a shear force is borne by an inclined tension connector which forms an angle with a connection surface. Both a rigid joint and a hinge joint of the combined floating structure have certain elasticity and can bear a large wave load. Because the length of the tension connector can be adjusted and the requirement on the manufacturing precision of the floating body cells is low, bigger floating body cells can be used so that a bigger floating structure can be combined. Because of being not welded together with the floating body cells, the tension connector can be changed so that the service life of the floating structure is not limited by the fatigue life of the connector.

A semiconductor device comprises: a channel region of a transistor formed in a predetermined region of silicon layer formed on insulation film; a gate electrode formed on the channel region via gate insulation film; and source/drain regions formed in the silicon layer thicker than said channel region located out of the channel region, wherein the transistor is a memory element constituting the channel region as a floating body cell.

Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.

The invention belongs to the technical field of dynamic random access memories, in particular to a method for refreshing a bulk-silicon floating body cell transistor memory, which comprises the step of: offsetting a voltage pulse on an implant layer of a bulk-silicon floating body cell (FBC) to ensure that a PN junction between the implant layer and a floating body cell region is weakly conductedso that the memory is changed from a strong 1 state into a weak 1 state or from a weak 0 state into a strong 0 state. The method has the characteristic of high refreshing reliability due to no utilization of a Charge Bumping effect. Meanwhile, for the FBC memory unit or memory, the read process does not exist in the refreshing process, thus a storage array of the FBC memory is integrally refreshed.

The invention provides a fin-like back gate storage structure and an automatic refreshing method of floating body cells. A back gate is arranged on the upper surface of a substrate, a back gate?oxide layer is arranged on the upper surface of the back gate, and a floating gate structure is arranged on the back gate?oxide layer. Data writing can be finished with small voltage. As the automatic floating body cell refreshing technology is adopted, the maintaining time is greatly increased, power consumption is significantly reduced, and integration is high as the size of the storage cell is excessively small. A static random access memory whose single tube storage structure replaces the original six-tube memory cell can greatly reduce the area of CMOS processer chip and is applied to a technology node of no less than 28/20/14nm, the cost is reduced obviously, and the power consumption is significantly reduced.

Disclosed herein is a semiconductor memory device including floating body cells. The semiconductor memory device includes memory cell active regions formed on a Silicon-On Isolator (SOI) semiconductor substrate, a plurality of floating body cell transistors formed in the memory cell active regions, and inactive transistors for providing cell isolation that are formed between the plurality of floating body cell transistors. Here, the inactive transistors for providing cell isolation are controlled so that they always are in an OFF state while the semiconductor memory device is operating.