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Semiconductor memory apparatus and refresh control method of the same

A memory and semiconductor technology, applied in static memory, digital memory information, information storage, etc., can solve the problems of data volatility, difficult to use semiconductor memory device storage units, etc.

Inactive Publication Date: 2010-10-20
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] So far, FBC technology has been difficult to apply to memory cells of semiconductor memory devices because circuits for supplying voltage to the source, drain, and gate of each cell transistor have not been developed
Also, similar to DRAM, the data of semiconductor memory devices employing FBC technology is also volatile

Method used

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  • Semiconductor memory apparatus and refresh control method of the same
  • Semiconductor memory apparatus and refresh control method of the same
  • Semiconductor memory apparatus and refresh control method of the same

Examples

Experimental program
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Embodiment Construction

[0030] figure 2 is a block diagram showing the configuration of a memory core area of ​​a semiconductor memory device according to one embodiment.

[0031] Such as figure 2 As shown, the semiconductor memory device may include a refresh controller 10, a row refresh counter 11, a row address decoder 12, a source address decoder 13, a row operation controller 14, a column refresh counter 15, a column address decoder 16, a column operation control device 17, data bus switch 18 and memory cell block 19.

[0032] The refresh controller 10 may generate a refresh enable signal rfen, a refresh read signal rfrd, a refresh write signal rfwt, and a refresh sense amplification enable signal rfsaen in response to the refresh signal rfsh. The row refresh counter 11 may generate a multi-bit row count signal rcnt and a multi-bit source count signal scnt by performing a count operation in response to the refresh enable signal rfen. The row address decoder 12 may generate the multi-bit row...

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PUM

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Abstract

A semiconductor memory apparatus and a refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC) transistors. Each FBC transistor has a gate connected to a word line, a drain connected to a bit line, and a source connected to a source line. FBC transistor pairs are formed by sharing the source lines in the plurality of the floating body cell transistors. When a refresh signal is enabled, the semiconductor memory apparatus is configured to read data stored in the memory cell block by enabling a refresh read signal and then configured to rewrite the read data in the memory cell block by enabling a refresh write signal.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more specifically, to a storage unit of the semiconductor memory device and a control circuit thereof. Background technique [0002] A conventional dynamic random access memory (DRAM) includes many memory cells, each of which includes a transistor and a capacitor to store data. However, a general structure having these memory cells is not suitable for reducing the area of ​​a memory core region, so that there is a technical limit in increasing the degree of integration of a semiconductor memory device. Therefore, a floating body cell (FBC, Floating body cell) technology for implementing a transistor and a capacitor of a memory cell as one transistor has been developed. [0003] The FBC technique will be described in more detail below with reference to the accompanying drawings. [0004] figure 1 is a cross-sectional view of a transistor implementing FBC, and illustrates an N-type tr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/401G11C11/4063G11C11/406
CPCG11C2211/4016G11C11/406G11C2211/4065G11C11/4085G11C11/4087G11C11/4091G11C11/4094G11C11/4096
Inventor 吴荣训
Owner SK HYNIX INC
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