Semiconductor memory apparatus and refresh control method of the same

Abstract

A semiconductor memory apparatus and a refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC) transistors. Each FBC transistor has a gate connected to a word line, a drain connected to a bit line, and a source connected to a source line. FBC transistor pairs are formed by sharing the source lines in the plurality of the floating body cell transistors. When a refresh signal is enabled, the semiconductor memory apparatus is configured to read data stored in the memory cell block by enabling a refresh read signal and then configured to rewrite the read data in the memory cell block by enabling a refresh write signal.

Description

technical field

[0001] The present invention relates to a semiconductor memory device, and more specifically, to a storage unit of the semiconductor memory device and a control circuit thereof. Background technique

[0002] A conventional dynamic random access memory (DRAM) includes many memory cells, each of which includes a transistor and a capacitor to store data. However, a general structure having these memory cells is not suitable for reducing the area of ​​a memory core region, so that there is a technical limit in increasing the degree of integration of a semiconductor memory device. Therefore, a floating body cell (FBC, Floating body cell) technology for implementing a transistor and a capacitor of a memory cell as one transistor has been developed.

[0003] The FBC technique will be described in more detail below with reference to the accompanying drawings.

[0004] figure 1 is a cross-sectional view of a transistor implementing FBC, and illustrates an N-type tr...

Images