14 results about "Source lines" patented technology

The application discloses a source line abnormality detection circuit and method based on charge sharing. The circuit comprises a source drive array, a display panel, a comparator and a reference module. The application adds a reference capacitor with a capacitance not greater than the parasitic capacitance of the source line, and converts the size of the parasitic capacitance of the source line which is difficult to directly measure into a detection voltage which can be compared with a reference voltage by using the voltage division principle after charge sharing, so that the faults such as disconnection or short circuit with adjacent lines of the source line can be accurately judged. The application realizes online and non-invasive abnormality monitoring of the source line, and can effectively improve the reliability and maintainability of the display chip and the display panel.

The application provides a memory, an operating method of the memory and an electronic device. The memory comprises: a first storage array; the first storage array comprises a plurality of first storage units arranged in an array; the first storage unit comprises n first transistors and m first storage elements; a second storage array; the second storage array is stacked with the first storage array along a vertical direction and comprises a plurality of second storage units arranged in an array; the second storage unit comprises n second transistors and m second storage elements; a plurality of first word lines; first transistors located in the same row are connected to the same first word line; a plurality of second word lines; second transistors located in the same row are connected to the same second word line; a plurality of source lines; the plurality of source lines extend along a row direction and are arranged at intervals along a column direction, wherein the first storage units located in the same column and the second storage units corresponding to the first storage units located in the same column and arranged correspondingly are connected to the same source line.

The present disclosure relates to the technical field of circuits. Provided are a power carrier circuit and a lighting device. A carrier modulates a carrier signal into an alternating current of a first power source line, so as to obtain an alternating-current carrier control signal; a rectifier converts into a direct current the alternating-current carrier control signal transmitted by the first power source line; a first coupler is used for filtering out a direct-current signal and a low-frequency signal in the alternating-current carrier control signal, and retaining a high-frequency signal in the alternating-current carrier control signal, where the target carrier signal and the first direct-current signal are modulated in a second power source line; a second coupler is used for performing coupling on the direct-current power source carrier signal to obtain the target carrier signal, and transmitting the target carrier signal to a lighting module.

This invention provides a memory device capable of high-speed operation. One embodiment of the memory device includes a bit line, a source line, a first unit transistor between the bit line and the source line, a second unit transistor between the first unit transistor and the bit line, a third unit transistor between the first unit transistor and the source line, a first word line connected to the gate of the first unit transistor, a second word line connected to the gate of the second unit transistor, and a third word line connected to the gate of the third unit transistor. A first voltage is applied to the source line during a first period. At a first moment within the first period, a second voltage greater than or equal to the threshold voltage of the first, second, and third unit transistors is applied to at least one of the second and third word lines. At a second moment later than the first moment within the first period, a third voltage greater than or equal to the threshold voltage of the first, second, and third unit transistors is applied to the first word line.

The invention provides a memory, an operation method thereof and a storage system, and belongs to the technical field of storage. In the scheme provided by the invention, the first discharge circuit in the memory can discharge the bit line through the first discharge transistor based on the received first voltage. The second discharge circuit is capable of discharging the source line through the second discharge transistor based on the received second voltage. Wherein the second voltage is higher than the first voltage, and the discharge current output by the second discharge transistor is larger than the discharge current output by the first discharge transistor. Due to the fact that the discharge current is large when the second discharge circuit discharges the source line, even if the load of the source line is large, it can be ensured that the voltage difference between the source line and the bit line is small in the discharge process, and then the performance of a top select gate (TSG) connected with the bit line is prevented from being affected.

The present application discloses a source driver, a display device and a source driving method. The source driver provides a plurality of source driving signals to the display panel through a plurality of source lines, and the display panel also receives a common voltage signal through a common electrode line. The source driver includes: a voltage detection circuit, which detects the voltage state of the low-voltage driving signal to output a state characterization signal; a logic circuit, which generates a control signal according to the state characterization signal and the backlight enable signal; an output selection circuit, which connects a plurality of source lines and a common electrode line, and selects to output the source driving signal and the common voltage signal to the display panel or output the ground voltage to the display panel according to the control signal. The output selection circuit outputs the source driving signal and the common voltage signal to the display panel according to the control signal only when the state characterization signal is valid and the backlight enable signal is valid. In order to control the timing of the low-voltage driving signal, the source driving signal and the common voltage signal during the startup process, the white flickering of the screen is improved.

The embodiment of the invention provides a storage device which can restrain manufacturing cost. According to one embodiment, a memory device includes a substrate (W1), a first circuit layer, and a second circuit layer. The substrate has a first region and a second region. The second circuit layer includes: a laminated body including first insulator layers and first conductor layers alternately laminated in the second direction in the first region; a plurality of first pillars that pass through the stacked body in the second direction in the first region and are electrically connected to the source line above the stacked body; and at least one first contact having a portion provided at the same height as the laminated body in the second region. The source line includes a second conductor layer (51) having a portion provided so as to cover an upper portion of each of the plurality of first pillars in the first region, and a portion provided so as to cover an upper portion of at least one first contact in the second region. The surface of the second conductor layer is provided in a non-planar shape above at least one of the plurality of first pillars and the at least one first contact.

The present invention provides a data-driven surface wave prediction method, device, computer-readable storage medium, and system. The method constructs a cross-arranged shot-and-detection seismic observation system, wherein a source line composed of a number of vertically arranged shot points intersects a detection line composed of a number of horizontally arranged detection points in a cross-shaped manner; seismic data from the cross-arranged shot-and-detection seismic observation system is acquired and converted from the time domain to the frequency domain; the number of shot points on the source line and the number of detection points on the detection line that participate in surface wave prediction are determined, and these are grouped into a number of shot-and-detection pairs; for each group of shot-and-detection pairs, a surface wave prediction result is calculated for each frequency component in the frequency domain seismic data; and the surface wave prediction results for all frequency components of all shot-and-detection pairs are converted from the frequency domain to the time domain to obtain the surface wave prediction results of the shot-and-detection seismic observation system. The present invention does not rely on a near-surface model, does not require human interaction, and can be widely applied to ground seismic data processing.

The invention discloses a source line anomaly detection circuit and anomaly detection method based on charge sharing. The circuit comprises a source electrode driving array, a display panel, a comparator and a reference module. According to the invention, the reference capacitor whose capacitance value is not greater than the parasitic capacitance of the source line is added, and the voltage division principle after charge sharing is utilized, so that the parasitic capacitance of the source line, which is difficult to directly measure, is converted into the detection voltage which can be compared with the reference voltage; therefore, faults such as disconnection of the source line or short circuit between the source line and an adjacent line can be accurately judged. According to the invention, on-line and non-intrusive abnormity monitoring of the source line is realized, and the reliability and maintainability of the display chip and the display panel can be effectively improved.

The application discloses a device for realizing fast two-dimensional DCT transformation and a method thereof. The device comprises a bit line driving unit, a word line driving unit, a source line driving unit, a photoelectric storage and calculation integrated device array unit, an integration unit, a current-voltage conversion and analog-digital conversion unit and a shift accumulation unit. The driving units are used for inputting a transformation matrix and a data vector. The photoelectric storage and calculation integrated device array unit is used for completing multiplication operation of the transformation matrix and the data vector. The integration unit is used for integrating positive value components and negative value components into one data. The current-voltage conversion and analog-digital conversion unit is used for converting a photoelectric current signal into a voltage signal and converting a voltage analog signal into a digital signal. The shift accumulation unit is used for shifting and accumulating intermediate results. The device can realize fast two-dimensional DCT transformation, and when the hardware is used to realize calculation acceleration, the area, power consumption and calculation delay of the hardware architecture are greatly reduced.

The current-limiting protection circuit is connected with a bit line and a source line which are connected with the RRAM, the RRAM comprises a plurality of resistive units which are connected between the source line and the bit line and comprise a transistor and a resistive device, the transistor is connected with the resistive device, the control end of the transistor is connected with a word line, and the control end of the resistive device is connected with the bit line. The current-limiting protection circuit comprises a feedback protection circuit and a termination signal generation circuit, the feedback protection circuit is connected with a bit line and a source line and comprises a first feedback unit, a second feedback unit and a third feedback unit, the first feedback unit is connected with the bit line, the second feedback unit is connected with the source line, and the third feedback unit is connected with the termination signal generation circuit. The third feedback unit is connected with the first feedback unit and the second feedback unit, and when the voltage of the source line rises, the current of the resistance change unit is rapidly reduced through multiple feedback paths, and the voltage drop of a transistor in the resistance change unit is limited; the termination signal generation circuit is connected with the source line and the feedback protection circuit to generate a termination signal and terminate the activation voltage output.

A memory device includes a first memory block containing first word lines and a first source layer segment, and a second memory block containing second word lines and a second source layer segment which is electrically isolated from the first source layer segment. The first word lines in the first memory block are electrically connected to the respective second word lines in the second memory block.

The application discloses an Oersted magnetic field assisted SOT-MRAM unit and a write voltage regulation method thereof, and the structure comprises a first PMOS tube, a second PMOS tube and a SOT device. The gate of the first PMOS tube is connected with a first word line WL, the source is connected with a reading channel of the SOT device, and the drain is connected to a bit line BL. The gate of the second PMOS tube is connected with a second word line WWL, the drain is connected to the bit line BL, and the source is connected to a writing channel of the SOT device. The other end of the writing channel of the SOT device is connected to a source line SL. A current line and a magnetic sensor are arranged directly below the SOT device, and the current line is located between the SOT device and the magnetic sensor. An Oersted magnetic field is generated by applying a current in the current line. In the writing process, the different device flip probabilities are concentrated around the same voltage by the controllable magnetic field, so that the writing error is reduced, the overshoot is avoided, and the loss is reduced.

The invention relates to the technical field of spectrum analysis instruments, in particular to a memristor spectrum in-situ reconstruction system and a spectrum in-situ decoding operation method. The system comprises a front-end coding assembly which is used for collecting an optical signal and coding the optical signal into a current signal; the data interface is used for converting the current signal into a target voltage signal and applying the target voltage signal to a bit line of the memristor array; and the memristor array is used for multiplying the voltage applied by the bit line by the conductance of the memristor in the corresponding row, and performing current accumulation on the source line according to a product result to obtain a reconstructed spectrum. Therefore, the calculation reconstruction type spectrometer in-situ reconstruction architecture based on the memristor array is provided, and the problems that in the prior art, the physical sizes of a front-end encoder and a rear-end decoder are not matched with a data interface, and rear-end decoding hardware generally adopts a traditional von-Noiemann architecture are solved; the decoding speed is low; and the energy consumption is high. The overall performance of the calculation reconstruction type spectrometer is improved.