6 results about "Source lines" patented technology

The application discloses a source line abnormality detection circuit and method based on charge sharing. The circuit comprises a source drive array, a display panel, a comparator and a reference module. The application adds a reference capacitor with a capacitance not greater than the parasitic capacitance of the source line, and converts the size of the parasitic capacitance of the source line which is difficult to directly measure into a detection voltage which can be compared with a reference voltage by using the voltage division principle after charge sharing, so that the faults such as disconnection or short circuit with adjacent lines of the source line can be accurately judged. The application realizes online and non-invasive abnormality monitoring of the source line, and can effectively improve the reliability and maintainability of the display chip and the display panel.

The present disclosure relates to the technical field of circuits. Provided are a power carrier circuit and a lighting device. A carrier modulates a carrier signal into an alternating current of a first power source line, so as to obtain an alternating-current carrier control signal; a rectifier converts into a direct current the alternating-current carrier control signal transmitted by the first power source line; a first coupler is used for filtering out a direct-current signal and a low-frequency signal in the alternating-current carrier control signal, and retaining a high-frequency signal in the alternating-current carrier control signal, where the target carrier signal and the first direct-current signal are modulated in a second power source line; a second coupler is used for performing coupling on the direct-current power source carrier signal to obtain the target carrier signal, and transmitting the target carrier signal to a lighting module.

This invention provides a memory device capable of high-speed operation. One embodiment of the memory device includes a bit line, a source line, a first unit transistor between the bit line and the source line, a second unit transistor between the first unit transistor and the bit line, a third unit transistor between the first unit transistor and the source line, a first word line connected to the gate of the first unit transistor, a second word line connected to the gate of the second unit transistor, and a third word line connected to the gate of the third unit transistor. A first voltage is applied to the source line during a first period. At a first moment within the first period, a second voltage greater than or equal to the threshold voltage of the first, second, and third unit transistors is applied to at least one of the second and third word lines. At a second moment later than the first moment within the first period, a third voltage greater than or equal to the threshold voltage of the first, second, and third unit transistors is applied to the first word line.

The embodiment of the invention provides a storage device which can restrain manufacturing cost. According to one embodiment, a memory device includes a substrate (W1), a first circuit layer, and a second circuit layer. The substrate has a first region and a second region. The second circuit layer includes: a laminated body including first insulator layers and first conductor layers alternately laminated in the second direction in the first region; a plurality of first pillars that pass through the stacked body in the second direction in the first region and are electrically connected to the source line above the stacked body; and at least one first contact having a portion provided at the same height as the laminated body in the second region. The source line includes a second conductor layer (51) having a portion provided so as to cover an upper portion of each of the plurality of first pillars in the first region, and a portion provided so as to cover an upper portion of at least one first contact in the second region. The surface of the second conductor layer is provided in a non-planar shape above at least one of the plurality of first pillars and the at least one first contact.

The invention discloses a source line anomaly detection circuit and anomaly detection method based on charge sharing. The circuit comprises a source electrode driving array, a display panel, a comparator and a reference module. According to the invention, the reference capacitor whose capacitance value is not greater than the parasitic capacitance of the source line is added, and the voltage division principle after charge sharing is utilized, so that the parasitic capacitance of the source line, which is difficult to directly measure, is converted into the detection voltage which can be compared with the reference voltage; therefore, faults such as disconnection of the source line or short circuit between the source line and an adjacent line can be accurately judged. According to the invention, on-line and non-intrusive abnormity monitoring of the source line is realized, and the reliability and maintainability of the display chip and the display panel can be effectively improved.

A memory device includes a first memory block containing first word lines and a first source layer segment, and a second memory block containing second word lines and a second source layer segment which is electrically isolated from the first source layer segment. The first word lines in the first memory block are electrically connected to the respective second word lines in the second memory block.