2829 results about "Source lines" patented technology

A method and system for providing a magnetic memory. The magnetic memory includes magnetic storage cells in an array, bit lines, and source lines. Each magnetic storage cell includes at least one magnetic element. The magnetic element(s) are programmable by write currents driven through the magnetic element(s). Each magnetic element has free and pinned layer(s) and a dominant spacer. The magnetic memory is configured such that either the read current(s) flow from the free layer(s) to the dominant spacer if the maximum low resistance state read current divided by the minimum low resistance state write current is greater than the maximum high resistance state read current divided by the minimum high resistance state write current or the read current(s) flow from the dominant spacer to the free layer(s) if the maximum low resistance state read current divided by the minimum low resistance state write current is less than the maximum high resistance state read current divided by the minimum high resistance state write current.

A method and system for providing a magnetic memory is described. The magnetic memory includes a plurality of magnetic storage cell and at least one bit line and a plurality of source lines corresponding to the plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element that is programmed to a high resistance state by a first write current driven through the magnetic element in a first direction and to a low resistance state by a second write current driven through the magnetic element in a second direction. The bit line(s) and the source lines are configured to drive the first write current through the magnetic element in the first direction, to drive the second write current through the magnetic element in the second direction, and to drive at least one read current through the magnetic element in a third direction that does not destabilize the low resistance state.

A nonvolatile semiconductor memory device includes a memory cell array which includes a memory cell string including a plurality of memory cells each having a variable resistor element and a switching element having a current path with one end and the other end, between which the variable resistor element is connected, the plurality of memory cells having current paths thereof being connected in series, the memory cell array further including a first select element connected to one end of a current path of the memory cell string, and a second select element connected to the other end of the current path of the memory cell string, a bit line which is electrically connected to one end of a current path of the first select element, and a source line which is electrically connected to one end of a current path of the second select element.

A thin-film transistor includes a gate electrode having first and second gate electrode edges on opposed sides, and a drain electrode having a first edge that overlaps the first gate electrode edge, and a second edge that overlaps the second gate electrode edge. A diode array is fabricated by successive deposition of a conductive layer, a doped semiconductor layer and an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line. Another display pixel unit provides reduced pixel electrode voltage shifts using a source line and a balance line.

The present invention employs a memory cell structure in that one end of a variable resistance element (1) for storing information by change of electric resistance is connected to a source of a selection transistor (2) to form a memory cell (3) and, in a memory cell array (4), a drain of the selection transistor (2) is connected to a common bit line (BL) in a column direction, the other end of the variable resistance element (1) is connected to a source line (SL) and a gate of the selection transistor (2) is connected to a common word line (WL) in a row direction. In the memory cell structure, an operation of resetting data stored in the memory cell (3) is carried out for each of sectors including the plural memory cells (3) commonly connected to the source line (SL).

A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.