2760 results about "Source lines" patented technology

A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line.

A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. A source diffusion layer, which is common to the first and second blocks, is disposed in a semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above at least three conductive layers, is interposed between the first and second blocks.

A DRAM-like non-volatile memory array includes a cell array of non-volatile cell units with a DRAM-like cross-coupled latch-type sense amplifier. Each non-volatile cell unit has two non-volatile cell devices with respective bit lines and source lines running in parallel and laid out perpendicular to the word line associated with the non-volatile cell unit. The two non-volatile cell devices are programmed with erased and programmed threshold voltages as a pair for storing a single bit of binary data. The two bit lines of each non-volatile cell unit are coupled through a Y-decoder and a latch device to the two respective inputs of the latch-type sense amplifier which provides a large sensing margin for the cell array to operate properly even with a narrowed threshold voltage gap. Each non-volatile cell device may be a 2 T FLOTOX-based EEPROM cell, a 2 T flash cell, 11 T flash cell or a 1.5 T split-gate flash cell.

A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies.

A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and at least one non-planar selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells.

A 3D memory device includes a plurality of ridge-shaped stacks of memory cells. Word lines are arranged over the stacks of memory cells. Bit lines structures are coupled to multiple locations along the stacks of memory cells. Source line structures are coupled to multiple locations along each of the semiconductor material strips of the stacks. The bit line structures and the source line structures are between adjacent ones of the word lines.

A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and a plurality of unidirectional polarity selection devices. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The unidirectional polarity selection devices are connected in parallel and such that they have opposing polarities. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells.

A liquid crystal display device according to the present invention includes a first substrate, a second substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. The first substrate includes: a plurality of gate lines; a plurality of source lines arranged to cross with the plurality of gate lines; a plurality of switching elements disposed in the vicinity of crossings of the plurality of gate lines and the plurality of source lines; and a plurality of pixel electrodes connected to the plurality of switching elements. The second substrate includes a counter electrode. A plurality of pixel regions are defined by the plurality of pixel electrodes, the counter electrode, and the liquid crystal layer interposed between the plurality of pixel electrodes and the counter electrode, and each of the plurality of pixel regions includes a reflection region and a transmission region.

The present invention provides an image display device that reduces variations in brightness of the light emitting elements included in the device due to a voltage drop on the power source line of the device and TFT threshold voltage variations and displays good quality images. The image display device is equipped with a pixel circuit voltage detecting means to selectively output a voltage internal to a pixel circuit included in each of a plurality of pixels of the device to a signal line to which the pixel circuit connects. Its drive circuit is equipped with a voltage addition means to add the signal line voltage and a signal voltage corresponding to image data to be displayed and output a sum voltage to the signal line again.

An object of the invention is to provide a nonvolatile semiconductor memory device and an erase method for a memory cell array that have high degree of freedom and that are capable of quickly and securely implementing data erase and reprogramming. In a memory cell array, memory cells each configured of a variable resistor element for storing information through variations in electric resistance and a selected transistor are arranged in a matrix, and word lines (WL1, . . . , WLm) and bit lines (BL1, . . . , BLn) are arranged to select a predetermined memory cell. For the memory cell array, erase means is provided that sets the electric resistance of the variable resistor element to a predetermined erased state by applying voltage under a predetermined application condition to the word line (WL), bit line (BL), and source line (SL). The erase means switches between a batch-erase mode and an individual-erase mode. The batch-erase mode is used to perform batch erase of all the memory cells in the memory cell array, and the individual-erase mode is used to perform individual erase of a part of the memory cells in the memory cell array.

An organic light emitting display including a scan signal line forwarding a scan signal, a data line sending a data signal and a pixel coupled to the scan signal line and the data line, the organic light emitting diode display, wherein the pixel includes a first switching transistor transmitting a data signal from the data line in response to the scan signal of the scan signal line, a driving transistor, coupled to the first switching transistor, controlling driving current from a first power source line, a storage capacitor coupled between the driving transistor and the first power source line, an organic light emitting diode, coupled between the driving transistor and a second power source line, displaying an image with the driving current controlled by the driving transistor, an initial switching transistor, coupled between the storage capacitor and an initial power source line, initializing the storage capacitor, and a switching transistor for applying a reverse bias, coupled between the second power source line and the initial power source line, applying a reverse bias voltage to the organic light emitting diode.

The present invention employs a memory cell structure in that one end of a variable resistance element (1) for storing information by change of electric resistance is connected to a source of a selection transistor (2) to form a memory cell (3) and, in a memory cell array (4), a drain of the selection transistor (2) is connected to a common bit line (BL) in a column direction, the other end of the variable resistance element (1) is connected to a source line (SL) and a gate of the selection transistor (2) is connected to a common word line (WL) in a row direction. In the memory cell structure, an operation of resetting data stored in the memory cell (3) is carried out for each of sectors including the plural memory cells (3) commonly connected to the source line (SL).

A drive transistor is connected, via its drain region, to a power supply line, and, via its source region, to a transparent electrode of an organic EL element. The channel region is formed bent into a substantially L shape. This arrangement is able to simplify the arrangement of a gate electrode by providing the gate electrode so as to run straight over a channel region in parallel to the power source line. Accordingly, the aperture ratio is increased.

When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge line is driven from an H level (power supply potential) to an L level (reference potential). By the GIDL current from a source line, accumulation of holes is initiated again for a storage node subsequent to discharge of holes, whereby the potential of the storage node rises towards an H level (period α). When the charge line is driven to an H level from an L level, the potential of the storage node further rises (period β).

A semiconductor memory device comprises an array of memory cells each comprising a variable resistance element and a cell access transistor, and a voltage supplying means for applying the first voltage between the bit and source lines connected to the selected memory cell, the third voltage to the word line to apply the first write voltage between the two ports of the variable resistance element for shifting the resistance from the first state to the second state, and the second voltage opposite in polarity to the first voltage between the bit and source lines, the third voltage to the word line to apply the second write voltage opposite in polarity to and different in the absolute value from the first write voltage between the two ports for shifting the resistance from the second state to the first state, the voltage supplying means comprising an n-channel MOSFET and a p-channel MOSFET.

Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.

When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. Then, a hole current is produced near a third gate insulation layer due to a potential difference between the first and third voltage. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state.

An objective is to provide a technique for reducing the size of the picture-frame region of the active-matrix substrate and improve the freedom of design, such as the freedom in designing the active-matrix substrate. An active-matrix substrate includes a group of gate lines and a group of source lines crossing the gate lines. At least some of the gate lines have a length that is smaller than the maximum value of the width of the active-matrix substrate as measured in the direction in which the gate lines extend. The active-matrix substrate further includes pixel electrodes connected with the gate lines and source lines, and gate line driving units (11) provided in the display region for switching the gate lines to the selected or non-selected state in response to a supplied control signal. First terminals (12s) for providing data signals from the source driver and second terminals (12g) for providing control signals from the display control circuit are provided in the portion of the picture-frame region that is adjacent a side of the display region.